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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
0d75590d | 27 | #include "qemu/osdep.h" |
da34e65c | 28 | #include "qapi/error.h" |
fa98fbfc | 29 | #include "qapi/visitor.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
e35704ba | 31 | #include "sysemu/numa.h" |
83c9f4ca | 32 | #include "hw/hw.h" |
03dd024f | 33 | #include "qemu/log.h" |
71461b0f | 34 | #include "hw/fw-path-provider.h" |
9fdf0c29 | 35 | #include "elf.h" |
1422e32d | 36 | #include "net/net.h" |
ad440b4a | 37 | #include "sysemu/device_tree.h" |
9c17d615 | 38 | #include "sysemu/cpus.h" |
b3946626 | 39 | #include "sysemu/hw_accel.h" |
e97c3636 | 40 | #include "kvm_ppc.h" |
c4b63b7c | 41 | #include "migration/misc.h" |
84a899de | 42 | #include "migration/global_state.h" |
f2a8f0a6 | 43 | #include "migration/register.h" |
4be21d56 | 44 | #include "mmu-hash64.h" |
b4db5413 | 45 | #include "mmu-book3s-v3.h" |
7abd43ba | 46 | #include "cpu-models.h" |
3794d548 | 47 | #include "qom/cpu.h" |
9fdf0c29 DG |
48 | |
49 | #include "hw/boards.h" | |
0d09e41a | 50 | #include "hw/ppc/ppc.h" |
9fdf0c29 DG |
51 | #include "hw/loader.h" |
52 | ||
7804c353 | 53 | #include "hw/ppc/fdt.h" |
0d09e41a PB |
54 | #include "hw/ppc/spapr.h" |
55 | #include "hw/ppc/spapr_vio.h" | |
56 | #include "hw/pci-host/spapr.h" | |
a2cb15b0 | 57 | #include "hw/pci/msi.h" |
9fdf0c29 | 58 | |
83c9f4ca | 59 | #include "hw/pci/pci.h" |
71461b0f AK |
60 | #include "hw/scsi/scsi.h" |
61 | #include "hw/virtio/virtio-scsi.h" | |
c4e13492 | 62 | #include "hw/virtio/vhost-scsi-common.h" |
f61b4bed | 63 | |
022c62cb | 64 | #include "exec/address-spaces.h" |
2309832a | 65 | #include "exec/ram_addr.h" |
35139a59 | 66 | #include "hw/usb.h" |
1de7afc9 | 67 | #include "qemu/config-file.h" |
135a129a | 68 | #include "qemu/error-report.h" |
2a6593cb | 69 | #include "trace.h" |
34316482 | 70 | #include "hw/nmi.h" |
6449da45 | 71 | #include "hw/intc/intc.h" |
890c2b77 | 72 | |
68a27b20 | 73 | #include "hw/compat.h" |
f348b6d1 | 74 | #include "qemu/cutils.h" |
94a94e4c | 75 | #include "hw/ppc/spapr_cpu_core.h" |
2cc0e2e8 | 76 | #include "hw/mem/memory-device.h" |
68a27b20 | 77 | |
9fdf0c29 DG |
78 | #include <libfdt.h> |
79 | ||
4d8d5467 BH |
80 | /* SLOF memory layout: |
81 | * | |
82 | * SLOF raw image loaded at 0, copies its romfs right below the flat | |
83 | * device-tree, then position SLOF itself 31M below that | |
84 | * | |
85 | * So we set FW_OVERHEAD to 40MB which should account for all of that | |
86 | * and more | |
87 | * | |
88 | * We load our kernel at 4M, leaving space for SLOF initial image | |
89 | */ | |
38b02bd8 | 90 | #define FDT_MAX_SIZE 0x100000 |
39ac8455 | 91 | #define RTAS_MAX_SIZE 0x10000 |
b7d1f77a | 92 | #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ |
a9f8ad8f DG |
93 | #define FW_MAX_SIZE 0x400000 |
94 | #define FW_FILE_NAME "slof.bin" | |
4d8d5467 BH |
95 | #define FW_OVERHEAD 0x2800000 |
96 | #define KERNEL_LOAD_ADDR FW_MAX_SIZE | |
a9f8ad8f | 97 | |
4d8d5467 | 98 | #define MIN_RMA_SLOF 128UL |
9fdf0c29 | 99 | |
0c103f8e DG |
100 | #define PHANDLE_XICP 0x00001111 |
101 | ||
5d0fb150 GK |
102 | /* These two functions implement the VCPU id numbering: one to compute them |
103 | * all and one to identify thread 0 of a VCORE. Any change to the first one | |
104 | * is likely to have an impact on the second one, so let's keep them close. | |
105 | */ | |
106 | static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index) | |
107 | { | |
1a5008fc | 108 | assert(spapr->vsmt); |
5d0fb150 GK |
109 | return |
110 | (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; | |
111 | } | |
112 | static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr, | |
113 | PowerPCCPU *cpu) | |
114 | { | |
1a5008fc | 115 | assert(spapr->vsmt); |
5d0fb150 GK |
116 | return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; |
117 | } | |
118 | ||
46f7afa3 GK |
119 | static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) |
120 | { | |
121 | /* Dummy entries correspond to unused ICPState objects in older QEMUs, | |
122 | * and newer QEMUs don't even have them. In both cases, we don't want | |
123 | * to send anything on the wire. | |
124 | */ | |
125 | return false; | |
126 | } | |
127 | ||
128 | static const VMStateDescription pre_2_10_vmstate_dummy_icp = { | |
129 | .name = "icp/server", | |
130 | .version_id = 1, | |
131 | .minimum_version_id = 1, | |
132 | .needed = pre_2_10_vmstate_dummy_icp_needed, | |
133 | .fields = (VMStateField[]) { | |
134 | VMSTATE_UNUSED(4), /* uint32_t xirr */ | |
135 | VMSTATE_UNUSED(1), /* uint8_t pending_priority */ | |
136 | VMSTATE_UNUSED(1), /* uint8_t mfrr */ | |
137 | VMSTATE_END_OF_LIST() | |
138 | }, | |
139 | }; | |
140 | ||
141 | static void pre_2_10_vmstate_register_dummy_icp(int i) | |
142 | { | |
143 | vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, | |
144 | (void *)(uintptr_t) i); | |
145 | } | |
146 | ||
147 | static void pre_2_10_vmstate_unregister_dummy_icp(int i) | |
148 | { | |
149 | vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, | |
150 | (void *)(uintptr_t) i); | |
151 | } | |
152 | ||
1a518e76 | 153 | int spapr_max_server_number(sPAPRMachineState *spapr) |
46f7afa3 | 154 | { |
1a5008fc | 155 | assert(spapr->vsmt); |
72194664 | 156 | return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads); |
46f7afa3 GK |
157 | } |
158 | ||
833d4668 AK |
159 | static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, |
160 | int smt_threads) | |
161 | { | |
162 | int i, ret = 0; | |
163 | uint32_t servers_prop[smt_threads]; | |
164 | uint32_t gservers_prop[smt_threads * 2]; | |
14bb4486 | 165 | int index = spapr_get_vcpu_id(cpu); |
833d4668 | 166 | |
d6e166c0 DG |
167 | if (cpu->compat_pvr) { |
168 | ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); | |
6d9412ea AK |
169 | if (ret < 0) { |
170 | return ret; | |
171 | } | |
172 | } | |
173 | ||
833d4668 AK |
174 | /* Build interrupt servers and gservers properties */ |
175 | for (i = 0; i < smt_threads; i++) { | |
176 | servers_prop[i] = cpu_to_be32(index + i); | |
177 | /* Hack, direct the group queues back to cpu 0 */ | |
178 | gservers_prop[i*2] = cpu_to_be32(index + i); | |
179 | gservers_prop[i*2 + 1] = 0; | |
180 | } | |
181 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", | |
182 | servers_prop, sizeof(servers_prop)); | |
183 | if (ret < 0) { | |
184 | return ret; | |
185 | } | |
186 | ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", | |
187 | gservers_prop, sizeof(gservers_prop)); | |
188 | ||
189 | return ret; | |
190 | } | |
191 | ||
99861ecb | 192 | static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) |
0da6f3fe | 193 | { |
14bb4486 | 194 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
195 | uint32_t associativity[] = {cpu_to_be32(0x5), |
196 | cpu_to_be32(0x0), | |
197 | cpu_to_be32(0x0), | |
198 | cpu_to_be32(0x0), | |
15f8b142 | 199 | cpu_to_be32(cpu->node_id), |
0da6f3fe BR |
200 | cpu_to_be32(index)}; |
201 | ||
202 | /* Advertise NUMA via ibm,associativity */ | |
99861ecb | 203 | return fdt_setprop(fdt, offset, "ibm,associativity", associativity, |
0da6f3fe | 204 | sizeof(associativity)); |
0da6f3fe BR |
205 | } |
206 | ||
86d5771a | 207 | /* Populate the "ibm,pa-features" property */ |
ee76a09f DG |
208 | static void spapr_populate_pa_features(sPAPRMachineState *spapr, |
209 | PowerPCCPU *cpu, | |
210 | void *fdt, int offset, | |
7abd43ba | 211 | bool legacy_guest) |
86d5771a SB |
212 | { |
213 | uint8_t pa_features_206[] = { 6, 0, | |
214 | 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; | |
215 | uint8_t pa_features_207[] = { 24, 0, | |
216 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, | |
217 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, | |
218 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, | |
219 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; | |
9fb4541f SB |
220 | uint8_t pa_features_300[] = { 66, 0, |
221 | /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ | |
222 | /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ | |
223 | 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ | |
224 | /* 6: DS207 */ | |
225 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ | |
226 | /* 16: Vector */ | |
86d5771a | 227 | 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ |
9fb4541f | 228 | /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ |
9bf502fe | 229 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ |
9fb4541f SB |
230 | /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ |
231 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ | |
232 | /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ | |
233 | 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ | |
234 | /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ | |
235 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ | |
236 | /* 42: PM, 44: PC RA, 46: SC vec'd */ | |
237 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ | |
238 | /* 48: SIMD, 50: QP BFP, 52: String */ | |
239 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ | |
240 | /* 54: DecFP, 56: DecI, 58: SHA */ | |
241 | 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ | |
242 | /* 60: NM atomic, 62: RNG */ | |
243 | 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ | |
244 | }; | |
7abd43ba | 245 | uint8_t *pa_features = NULL; |
86d5771a SB |
246 | size_t pa_size; |
247 | ||
7abd43ba | 248 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { |
86d5771a SB |
249 | pa_features = pa_features_206; |
250 | pa_size = sizeof(pa_features_206); | |
7abd43ba SJS |
251 | } |
252 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { | |
86d5771a SB |
253 | pa_features = pa_features_207; |
254 | pa_size = sizeof(pa_features_207); | |
7abd43ba SJS |
255 | } |
256 | if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { | |
86d5771a SB |
257 | pa_features = pa_features_300; |
258 | pa_size = sizeof(pa_features_300); | |
7abd43ba SJS |
259 | } |
260 | if (!pa_features) { | |
86d5771a SB |
261 | return; |
262 | } | |
263 | ||
26cd35b8 | 264 | if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { |
86d5771a SB |
265 | /* |
266 | * Note: we keep CI large pages off by default because a 64K capable | |
267 | * guest provisioned with large pages might otherwise try to map a qemu | |
268 | * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages | |
269 | * even if that qemu runs on a 4k host. | |
270 | * We dd this bit back here if we are confident this is not an issue | |
271 | */ | |
272 | pa_features[3] |= 0x20; | |
273 | } | |
4e5fe368 | 274 | if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { |
86d5771a SB |
275 | pa_features[24] |= 0x80; /* Transactional memory support */ |
276 | } | |
e957f6a9 SB |
277 | if (legacy_guest && pa_size > 40) { |
278 | /* Workaround for broken kernels that attempt (guest) radix | |
279 | * mode when they can't handle it, if they see the radix bit set | |
280 | * in pa-features. So hide it from them. */ | |
281 | pa_features[40 + 2] &= ~0x80; /* Radix MMU */ | |
282 | } | |
86d5771a SB |
283 | |
284 | _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); | |
285 | } | |
286 | ||
28e02042 | 287 | static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) |
6e806cc3 | 288 | { |
82677ed2 AK |
289 | int ret = 0, offset, cpus_offset; |
290 | CPUState *cs; | |
6e806cc3 | 291 | char cpu_model[32]; |
7f763a5d | 292 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
6e806cc3 | 293 | |
82677ed2 AK |
294 | CPU_FOREACH(cs) { |
295 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
296 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 297 | int index = spapr_get_vcpu_id(cpu); |
abbc1247 | 298 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
6e806cc3 | 299 | |
5d0fb150 | 300 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
6e806cc3 BR |
301 | continue; |
302 | } | |
303 | ||
82677ed2 | 304 | snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); |
6e806cc3 | 305 | |
82677ed2 AK |
306 | cpus_offset = fdt_path_offset(fdt, "/cpus"); |
307 | if (cpus_offset < 0) { | |
a4f3885c | 308 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); |
82677ed2 AK |
309 | if (cpus_offset < 0) { |
310 | return cpus_offset; | |
311 | } | |
312 | } | |
313 | offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); | |
6e806cc3 | 314 | if (offset < 0) { |
82677ed2 AK |
315 | offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); |
316 | if (offset < 0) { | |
317 | return offset; | |
318 | } | |
6e806cc3 BR |
319 | } |
320 | ||
7f763a5d DG |
321 | ret = fdt_setprop(fdt, offset, "ibm,pft-size", |
322 | pft_size_prop, sizeof(pft_size_prop)); | |
6e806cc3 BR |
323 | if (ret < 0) { |
324 | return ret; | |
325 | } | |
833d4668 | 326 | |
99861ecb IM |
327 | if (nb_numa_nodes > 1) { |
328 | ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); | |
329 | if (ret < 0) { | |
330 | return ret; | |
331 | } | |
0da6f3fe BR |
332 | } |
333 | ||
12dbeb16 | 334 | ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); |
833d4668 AK |
335 | if (ret < 0) { |
336 | return ret; | |
337 | } | |
e957f6a9 | 338 | |
ee76a09f DG |
339 | spapr_populate_pa_features(spapr, cpu, fdt, offset, |
340 | spapr->cas_legacy_guest_workaround); | |
6e806cc3 BR |
341 | } |
342 | return ret; | |
343 | } | |
344 | ||
c86c1aff | 345 | static hwaddr spapr_node0_size(MachineState *machine) |
b082d65a AK |
346 | { |
347 | if (nb_numa_nodes) { | |
348 | int i; | |
349 | for (i = 0; i < nb_numa_nodes; ++i) { | |
350 | if (numa_info[i].node_mem) { | |
fb164994 DG |
351 | return MIN(pow2floor(numa_info[i].node_mem), |
352 | machine->ram_size); | |
b082d65a AK |
353 | } |
354 | } | |
355 | } | |
fb164994 | 356 | return machine->ram_size; |
b082d65a AK |
357 | } |
358 | ||
a1d59c0f AK |
359 | static void add_str(GString *s, const gchar *s1) |
360 | { | |
361 | g_string_append_len(s, s1, strlen(s1) + 1); | |
362 | } | |
7f763a5d | 363 | |
03d196b7 | 364 | static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, |
26a8c353 AK |
365 | hwaddr size) |
366 | { | |
367 | uint32_t associativity[] = { | |
368 | cpu_to_be32(0x4), /* length */ | |
369 | cpu_to_be32(0x0), cpu_to_be32(0x0), | |
c3b4f589 | 370 | cpu_to_be32(0x0), cpu_to_be32(nodeid) |
26a8c353 AK |
371 | }; |
372 | char mem_name[32]; | |
373 | uint64_t mem_reg_property[2]; | |
374 | int off; | |
375 | ||
376 | mem_reg_property[0] = cpu_to_be64(start); | |
377 | mem_reg_property[1] = cpu_to_be64(size); | |
378 | ||
379 | sprintf(mem_name, "memory@" TARGET_FMT_lx, start); | |
380 | off = fdt_add_subnode(fdt, 0, mem_name); | |
381 | _FDT(off); | |
382 | _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); | |
383 | _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, | |
384 | sizeof(mem_reg_property)))); | |
385 | _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, | |
386 | sizeof(associativity)))); | |
03d196b7 | 387 | return off; |
26a8c353 AK |
388 | } |
389 | ||
28e02042 | 390 | static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) |
7f763a5d | 391 | { |
fb164994 | 392 | MachineState *machine = MACHINE(spapr); |
7db8a127 AK |
393 | hwaddr mem_start, node_size; |
394 | int i, nb_nodes = nb_numa_nodes; | |
395 | NodeInfo *nodes = numa_info; | |
396 | NodeInfo ramnode; | |
397 | ||
398 | /* No NUMA nodes, assume there is just one node with whole RAM */ | |
399 | if (!nb_numa_nodes) { | |
400 | nb_nodes = 1; | |
fb164994 | 401 | ramnode.node_mem = machine->ram_size; |
7db8a127 | 402 | nodes = &ramnode; |
5fe269b1 | 403 | } |
7f763a5d | 404 | |
7db8a127 AK |
405 | for (i = 0, mem_start = 0; i < nb_nodes; ++i) { |
406 | if (!nodes[i].node_mem) { | |
407 | continue; | |
408 | } | |
fb164994 | 409 | if (mem_start >= machine->ram_size) { |
5fe269b1 PM |
410 | node_size = 0; |
411 | } else { | |
7db8a127 | 412 | node_size = nodes[i].node_mem; |
fb164994 DG |
413 | if (node_size > machine->ram_size - mem_start) { |
414 | node_size = machine->ram_size - mem_start; | |
5fe269b1 PM |
415 | } |
416 | } | |
7db8a127 | 417 | if (!mem_start) { |
b472b1a7 DHB |
418 | /* spapr_machine_init() checks for rma_size <= node0_size |
419 | * already */ | |
e8f986fc | 420 | spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); |
7db8a127 AK |
421 | mem_start += spapr->rma_size; |
422 | node_size -= spapr->rma_size; | |
423 | } | |
6010818c AK |
424 | for ( ; node_size; ) { |
425 | hwaddr sizetmp = pow2floor(node_size); | |
426 | ||
427 | /* mem_start != 0 here */ | |
428 | if (ctzl(mem_start) < ctzl(sizetmp)) { | |
429 | sizetmp = 1ULL << ctzl(mem_start); | |
430 | } | |
431 | ||
432 | spapr_populate_memory_node(fdt, i, mem_start, sizetmp); | |
433 | node_size -= sizetmp; | |
434 | mem_start += sizetmp; | |
435 | } | |
7f763a5d DG |
436 | } |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
0da6f3fe BR |
441 | static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, |
442 | sPAPRMachineState *spapr) | |
443 | { | |
444 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
445 | CPUPPCState *env = &cpu->env; | |
446 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); | |
14bb4486 | 447 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
448 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
449 | 0xffffffff, 0xffffffff}; | |
afd10a0f BR |
450 | uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() |
451 | : SPAPR_TIMEBASE_FREQ; | |
0da6f3fe BR |
452 | uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; |
453 | uint32_t page_sizes_prop[64]; | |
454 | size_t page_sizes_prop_size; | |
22419c2a | 455 | uint32_t vcpus_per_socket = smp_threads * smp_cores; |
0da6f3fe | 456 | uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; |
abbc1247 | 457 | int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); |
af81cf32 | 458 | sPAPRDRConnector *drc; |
af81cf32 | 459 | int drc_index; |
c64abd1f SB |
460 | uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; |
461 | int i; | |
af81cf32 | 462 | |
fbf55397 | 463 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); |
af81cf32 | 464 | if (drc) { |
0b55aa91 | 465 | drc_index = spapr_drc_index(drc); |
af81cf32 BR |
466 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); |
467 | } | |
0da6f3fe BR |
468 | |
469 | _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); | |
470 | _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); | |
471 | ||
472 | _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); | |
473 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", | |
474 | env->dcache_line_size))); | |
475 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", | |
476 | env->dcache_line_size))); | |
477 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", | |
478 | env->icache_line_size))); | |
479 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", | |
480 | env->icache_line_size))); | |
481 | ||
482 | if (pcc->l1_dcache_size) { | |
483 | _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", | |
484 | pcc->l1_dcache_size))); | |
485 | } else { | |
3dc6f869 | 486 | warn_report("Unknown L1 dcache size for cpu"); |
0da6f3fe BR |
487 | } |
488 | if (pcc->l1_icache_size) { | |
489 | _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", | |
490 | pcc->l1_icache_size))); | |
491 | } else { | |
3dc6f869 | 492 | warn_report("Unknown L1 icache size for cpu"); |
0da6f3fe BR |
493 | } |
494 | ||
495 | _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); | |
496 | _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); | |
67d7d66f DG |
497 | _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); |
498 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); | |
0da6f3fe BR |
499 | _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); |
500 | _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); | |
501 | ||
502 | if (env->spr_cb[SPR_PURR].oea_read) { | |
503 | _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); | |
504 | } | |
505 | ||
58969eee | 506 | if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { |
0da6f3fe BR |
507 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", |
508 | segs, sizeof(segs)))); | |
509 | } | |
510 | ||
29386642 | 511 | /* Advertise VSX (vector extensions) if available |
0da6f3fe | 512 | * 1 == VMX / Altivec available |
29386642 DG |
513 | * 2 == VSX available |
514 | * | |
515 | * Only CPUs for which we create core types in spapr_cpu_core.c | |
516 | * are possible, and all of those have VMX */ | |
4e5fe368 | 517 | if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { |
29386642 DG |
518 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); |
519 | } else { | |
520 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); | |
0da6f3fe BR |
521 | } |
522 | ||
523 | /* Advertise DFP (Decimal Floating Point) if available | |
524 | * 0 / no property == no DFP | |
525 | * 1 == DFP available */ | |
4e5fe368 | 526 | if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { |
0da6f3fe BR |
527 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); |
528 | } | |
529 | ||
644a2c99 DG |
530 | page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, |
531 | sizeof(page_sizes_prop)); | |
0da6f3fe BR |
532 | if (page_sizes_prop_size) { |
533 | _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", | |
534 | page_sizes_prop, page_sizes_prop_size))); | |
535 | } | |
536 | ||
ee76a09f | 537 | spapr_populate_pa_features(spapr, cpu, fdt, offset, false); |
90da0d5a | 538 | |
0da6f3fe | 539 | _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", |
22419c2a | 540 | cs->cpu_index / vcpus_per_socket))); |
0da6f3fe BR |
541 | |
542 | _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", | |
543 | pft_size_prop, sizeof(pft_size_prop)))); | |
544 | ||
99861ecb IM |
545 | if (nb_numa_nodes > 1) { |
546 | _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); | |
547 | } | |
0da6f3fe | 548 | |
12dbeb16 | 549 | _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); |
c64abd1f SB |
550 | |
551 | if (pcc->radix_page_info) { | |
552 | for (i = 0; i < pcc->radix_page_info->count; i++) { | |
553 | radix_AP_encodings[i] = | |
554 | cpu_to_be32(pcc->radix_page_info->entries[i]); | |
555 | } | |
556 | _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", | |
557 | radix_AP_encodings, | |
558 | pcc->radix_page_info->count * | |
559 | sizeof(radix_AP_encodings[0])))); | |
560 | } | |
0da6f3fe BR |
561 | } |
562 | ||
563 | static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) | |
564 | { | |
04d595b3 | 565 | CPUState **rev; |
0da6f3fe | 566 | CPUState *cs; |
04d595b3 | 567 | int n_cpus; |
0da6f3fe BR |
568 | int cpus_offset; |
569 | char *nodename; | |
04d595b3 | 570 | int i; |
0da6f3fe BR |
571 | |
572 | cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); | |
573 | _FDT(cpus_offset); | |
574 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); | |
575 | _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); | |
576 | ||
577 | /* | |
578 | * We walk the CPUs in reverse order to ensure that CPU DT nodes | |
579 | * created by fdt_add_subnode() end up in the right order in FDT | |
580 | * for the guest kernel the enumerate the CPUs correctly. | |
04d595b3 EC |
581 | * |
582 | * The CPU list cannot be traversed in reverse order, so we need | |
583 | * to do extra work. | |
0da6f3fe | 584 | */ |
04d595b3 EC |
585 | n_cpus = 0; |
586 | rev = NULL; | |
587 | CPU_FOREACH(cs) { | |
588 | rev = g_renew(CPUState *, rev, n_cpus + 1); | |
589 | rev[n_cpus++] = cs; | |
590 | } | |
591 | ||
592 | for (i = n_cpus - 1; i >= 0; i--) { | |
593 | CPUState *cs = rev[i]; | |
0da6f3fe | 594 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
14bb4486 | 595 | int index = spapr_get_vcpu_id(cpu); |
0da6f3fe BR |
596 | DeviceClass *dc = DEVICE_GET_CLASS(cs); |
597 | int offset; | |
598 | ||
5d0fb150 | 599 | if (!spapr_is_thread0_in_vcore(spapr, cpu)) { |
0da6f3fe BR |
600 | continue; |
601 | } | |
602 | ||
603 | nodename = g_strdup_printf("%s@%x", dc->fw_name, index); | |
604 | offset = fdt_add_subnode(fdt, cpus_offset, nodename); | |
605 | g_free(nodename); | |
606 | _FDT(offset); | |
607 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
608 | } | |
609 | ||
eceba347 | 610 | g_free(rev); |
0da6f3fe BR |
611 | } |
612 | ||
0e947a89 TH |
613 | static int spapr_rng_populate_dt(void *fdt) |
614 | { | |
615 | int node; | |
616 | int ret; | |
617 | ||
618 | node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); | |
619 | if (node <= 0) { | |
620 | return -1; | |
621 | } | |
622 | ret = fdt_setprop_string(fdt, node, "device_type", | |
623 | "ibm,platform-facilities"); | |
624 | ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); | |
625 | ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); | |
626 | ||
627 | node = fdt_add_subnode(fdt, node, "ibm,random-v1"); | |
628 | if (node <= 0) { | |
629 | return -1; | |
630 | } | |
631 | ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); | |
632 | ||
633 | return ret ? -1 : 0; | |
634 | } | |
635 | ||
f47bd1c8 IM |
636 | static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) |
637 | { | |
638 | MemoryDeviceInfoList *info; | |
639 | ||
640 | for (info = list; info; info = info->next) { | |
641 | MemoryDeviceInfo *value = info->value; | |
642 | ||
643 | if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { | |
644 | PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; | |
645 | ||
ccc2cef8 | 646 | if (addr >= pcdimm_info->addr && |
f47bd1c8 IM |
647 | addr < (pcdimm_info->addr + pcdimm_info->size)) { |
648 | return pcdimm_info->node; | |
649 | } | |
650 | } | |
651 | } | |
652 | ||
653 | return -1; | |
654 | } | |
655 | ||
a324d6f1 BR |
656 | struct sPAPRDrconfCellV2 { |
657 | uint32_t seq_lmbs; | |
658 | uint64_t base_addr; | |
659 | uint32_t drc_index; | |
660 | uint32_t aa_index; | |
661 | uint32_t flags; | |
662 | } QEMU_PACKED; | |
663 | ||
664 | typedef struct DrconfCellQueue { | |
665 | struct sPAPRDrconfCellV2 cell; | |
666 | QSIMPLEQ_ENTRY(DrconfCellQueue) entry; | |
667 | } DrconfCellQueue; | |
668 | ||
669 | static DrconfCellQueue * | |
670 | spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, | |
671 | uint32_t drc_index, uint32_t aa_index, | |
672 | uint32_t flags) | |
03d196b7 | 673 | { |
a324d6f1 BR |
674 | DrconfCellQueue *elem; |
675 | ||
676 | elem = g_malloc0(sizeof(*elem)); | |
677 | elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); | |
678 | elem->cell.base_addr = cpu_to_be64(base_addr); | |
679 | elem->cell.drc_index = cpu_to_be32(drc_index); | |
680 | elem->cell.aa_index = cpu_to_be32(aa_index); | |
681 | elem->cell.flags = cpu_to_be32(flags); | |
682 | ||
683 | return elem; | |
684 | } | |
685 | ||
686 | /* ibm,dynamic-memory-v2 */ | |
687 | static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, | |
688 | int offset, MemoryDeviceInfoList *dimms) | |
689 | { | |
b0c14ec4 | 690 | MachineState *machine = MACHINE(spapr); |
a324d6f1 BR |
691 | uint8_t *int_buf, *cur_index, buf_len; |
692 | int ret; | |
693 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
694 | uint64_t addr, cur_addr, size; | |
b0c14ec4 DH |
695 | uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); |
696 | uint64_t mem_end = machine->device_memory->base + | |
697 | memory_region_size(&machine->device_memory->mr); | |
a324d6f1 BR |
698 | uint32_t node, nr_entries = 0; |
699 | sPAPRDRConnector *drc; | |
700 | DrconfCellQueue *elem, *next; | |
701 | MemoryDeviceInfoList *info; | |
702 | QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue | |
703 | = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); | |
704 | ||
705 | /* Entry to cover RAM and the gap area */ | |
706 | elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, | |
707 | SPAPR_LMB_FLAGS_RESERVED | | |
708 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
709 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
710 | nr_entries++; | |
711 | ||
b0c14ec4 | 712 | cur_addr = machine->device_memory->base; |
a324d6f1 BR |
713 | for (info = dimms; info; info = info->next) { |
714 | PCDIMMDeviceInfo *di = info->value->u.dimm.data; | |
715 | ||
716 | addr = di->addr; | |
717 | size = di->size; | |
718 | node = di->node; | |
719 | ||
720 | /* Entry for hot-pluggable area */ | |
721 | if (cur_addr < addr) { | |
722 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
723 | g_assert(drc); | |
724 | elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, | |
725 | cur_addr, spapr_drc_index(drc), -1, 0); | |
726 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
727 | nr_entries++; | |
728 | } | |
729 | ||
730 | /* Entry for DIMM */ | |
731 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); | |
732 | g_assert(drc); | |
733 | elem = spapr_get_drconf_cell(size / lmb_size, addr, | |
734 | spapr_drc_index(drc), node, | |
735 | SPAPR_LMB_FLAGS_ASSIGNED); | |
736 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
737 | nr_entries++; | |
738 | cur_addr = addr + size; | |
739 | } | |
740 | ||
741 | /* Entry for remaining hotpluggable area */ | |
742 | if (cur_addr < mem_end) { | |
743 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); | |
744 | g_assert(drc); | |
745 | elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, | |
746 | cur_addr, spapr_drc_index(drc), -1, 0); | |
747 | QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); | |
748 | nr_entries++; | |
749 | } | |
750 | ||
751 | buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); | |
752 | int_buf = cur_index = g_malloc0(buf_len); | |
753 | *(uint32_t *)int_buf = cpu_to_be32(nr_entries); | |
754 | cur_index += sizeof(nr_entries); | |
755 | ||
756 | QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { | |
757 | memcpy(cur_index, &elem->cell, sizeof(elem->cell)); | |
758 | cur_index += sizeof(elem->cell); | |
759 | QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); | |
760 | g_free(elem); | |
761 | } | |
762 | ||
763 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); | |
764 | g_free(int_buf); | |
765 | if (ret < 0) { | |
766 | return -1; | |
767 | } | |
768 | return 0; | |
769 | } | |
770 | ||
771 | /* ibm,dynamic-memory */ | |
772 | static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, | |
773 | int offset, MemoryDeviceInfoList *dimms) | |
774 | { | |
b0c14ec4 | 775 | MachineState *machine = MACHINE(spapr); |
a324d6f1 | 776 | int i, ret; |
03d196b7 | 777 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; |
0c9269a5 | 778 | uint32_t device_lmb_start = machine->device_memory->base / lmb_size; |
b0c14ec4 DH |
779 | uint32_t nr_lmbs = (machine->device_memory->base + |
780 | memory_region_size(&machine->device_memory->mr)) / | |
d0e5a8f2 | 781 | lmb_size; |
03d196b7 | 782 | uint32_t *int_buf, *cur_index, buf_len; |
16c25aef | 783 | |
ef001f06 TH |
784 | /* |
785 | * Allocate enough buffer size to fit in ibm,dynamic-memory | |
ef001f06 | 786 | */ |
a324d6f1 | 787 | buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); |
03d196b7 | 788 | cur_index = int_buf = g_malloc0(buf_len); |
03d196b7 BR |
789 | int_buf[0] = cpu_to_be32(nr_lmbs); |
790 | cur_index++; | |
791 | for (i = 0; i < nr_lmbs; i++) { | |
d0e5a8f2 | 792 | uint64_t addr = i * lmb_size; |
03d196b7 BR |
793 | uint32_t *dynamic_memory = cur_index; |
794 | ||
0c9269a5 | 795 | if (i >= device_lmb_start) { |
d0e5a8f2 | 796 | sPAPRDRConnector *drc; |
d0e5a8f2 | 797 | |
fbf55397 | 798 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); |
d0e5a8f2 | 799 | g_assert(drc); |
d0e5a8f2 BR |
800 | |
801 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
802 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
0b55aa91 | 803 | dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); |
d0e5a8f2 | 804 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ |
f47bd1c8 | 805 | dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); |
d0e5a8f2 BR |
806 | if (memory_region_present(get_system_memory(), addr)) { |
807 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); | |
808 | } else { | |
809 | dynamic_memory[5] = cpu_to_be32(0); | |
810 | } | |
03d196b7 | 811 | } else { |
d0e5a8f2 BR |
812 | /* |
813 | * LMB information for RMA, boot time RAM and gap b/n RAM and | |
0c9269a5 | 814 | * device memory region -- all these are marked as reserved |
d0e5a8f2 BR |
815 | * and as having no valid DRC. |
816 | */ | |
817 | dynamic_memory[0] = cpu_to_be32(addr >> 32); | |
818 | dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); | |
819 | dynamic_memory[2] = cpu_to_be32(0); | |
820 | dynamic_memory[3] = cpu_to_be32(0); /* reserved */ | |
821 | dynamic_memory[4] = cpu_to_be32(-1); | |
822 | dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | | |
823 | SPAPR_LMB_FLAGS_DRC_INVALID); | |
03d196b7 BR |
824 | } |
825 | ||
826 | cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; | |
827 | } | |
828 | ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); | |
a324d6f1 | 829 | g_free(int_buf); |
03d196b7 | 830 | if (ret < 0) { |
a324d6f1 BR |
831 | return -1; |
832 | } | |
833 | return 0; | |
834 | } | |
835 | ||
836 | /* | |
837 | * Adds ibm,dynamic-reconfiguration-memory node. | |
838 | * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation | |
839 | * of this device tree node. | |
840 | */ | |
841 | static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) | |
842 | { | |
843 | MachineState *machine = MACHINE(spapr); | |
844 | int ret, i, offset; | |
845 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
846 | uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; | |
847 | uint32_t *int_buf, *cur_index, buf_len; | |
848 | int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; | |
849 | MemoryDeviceInfoList *dimms = NULL; | |
850 | ||
851 | /* | |
0c9269a5 | 852 | * Don't create the node if there is no device memory |
a324d6f1 BR |
853 | */ |
854 | if (machine->ram_size == machine->maxram_size) { | |
855 | return 0; | |
856 | } | |
857 | ||
858 | offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); | |
859 | ||
860 | ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, | |
861 | sizeof(prop_lmb_size)); | |
862 | if (ret < 0) { | |
863 | return ret; | |
864 | } | |
865 | ||
866 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); | |
867 | if (ret < 0) { | |
868 | return ret; | |
869 | } | |
870 | ||
871 | ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); | |
872 | if (ret < 0) { | |
873 | return ret; | |
874 | } | |
875 | ||
876 | /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ | |
2cc0e2e8 | 877 | dimms = qmp_memory_device_list(); |
a324d6f1 BR |
878 | if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { |
879 | ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); | |
880 | } else { | |
881 | ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); | |
882 | } | |
883 | qapi_free_MemoryDeviceInfoList(dimms); | |
884 | ||
885 | if (ret < 0) { | |
886 | return ret; | |
03d196b7 BR |
887 | } |
888 | ||
889 | /* ibm,associativity-lookup-arrays */ | |
a324d6f1 BR |
890 | buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); |
891 | cur_index = int_buf = g_malloc0(buf_len); | |
6663864e | 892 | int_buf[0] = cpu_to_be32(nr_nodes); |
03d196b7 BR |
893 | int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ |
894 | cur_index += 2; | |
6663864e | 895 | for (i = 0; i < nr_nodes; i++) { |
03d196b7 BR |
896 | uint32_t associativity[] = { |
897 | cpu_to_be32(0x0), | |
898 | cpu_to_be32(0x0), | |
899 | cpu_to_be32(0x0), | |
900 | cpu_to_be32(i) | |
901 | }; | |
902 | memcpy(cur_index, associativity, sizeof(associativity)); | |
903 | cur_index += 4; | |
904 | } | |
905 | ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, | |
906 | (cur_index - int_buf) * sizeof(uint32_t)); | |
03d196b7 | 907 | g_free(int_buf); |
a324d6f1 | 908 | |
03d196b7 BR |
909 | return ret; |
910 | } | |
911 | ||
6787d27b MR |
912 | static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, |
913 | sPAPROptionVector *ov5_updates) | |
914 | { | |
915 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); | |
417ece33 | 916 | int ret = 0, offset; |
6787d27b MR |
917 | |
918 | /* Generate ibm,dynamic-reconfiguration-memory node if required */ | |
919 | if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { | |
920 | g_assert(smc->dr_lmb_enabled); | |
921 | ret = spapr_populate_drconf_memory(spapr, fdt); | |
417ece33 MR |
922 | if (ret) { |
923 | goto out; | |
924 | } | |
6787d27b MR |
925 | } |
926 | ||
417ece33 MR |
927 | offset = fdt_path_offset(fdt, "/chosen"); |
928 | if (offset < 0) { | |
929 | offset = fdt_add_subnode(fdt, 0, "chosen"); | |
930 | if (offset < 0) { | |
931 | return offset; | |
932 | } | |
933 | } | |
934 | ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, | |
935 | "ibm,architecture-vec-5"); | |
936 | ||
937 | out: | |
6787d27b MR |
938 | return ret; |
939 | } | |
940 | ||
10f12e64 DHB |
941 | static bool spapr_hotplugged_dev_before_cas(void) |
942 | { | |
943 | Object *drc_container, *obj; | |
944 | ObjectProperty *prop; | |
945 | ObjectPropertyIterator iter; | |
946 | ||
947 | drc_container = container_get(object_get_root(), "/dr-connector"); | |
948 | object_property_iter_init(&iter, drc_container); | |
949 | while ((prop = object_property_iter_next(&iter))) { | |
950 | if (!strstart(prop->type, "link<", NULL)) { | |
951 | continue; | |
952 | } | |
953 | obj = object_property_get_link(drc_container, prop->name, NULL); | |
954 | if (spapr_drc_needed(obj)) { | |
955 | return true; | |
956 | } | |
957 | } | |
958 | return false; | |
959 | } | |
960 | ||
03d196b7 BR |
961 | int spapr_h_cas_compose_response(sPAPRMachineState *spapr, |
962 | target_ulong addr, target_ulong size, | |
6787d27b | 963 | sPAPROptionVector *ov5_updates) |
03d196b7 BR |
964 | { |
965 | void *fdt, *fdt_skel; | |
966 | sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; | |
03d196b7 | 967 | |
10f12e64 DHB |
968 | if (spapr_hotplugged_dev_before_cas()) { |
969 | return 1; | |
970 | } | |
971 | ||
827b17c4 GK |
972 | if (size < sizeof(hdr) || size > FW_MAX_SIZE) { |
973 | error_report("SLOF provided an unexpected CAS buffer size " | |
974 | TARGET_FMT_lu " (min: %zu, max: %u)", | |
975 | size, sizeof(hdr), FW_MAX_SIZE); | |
976 | exit(EXIT_FAILURE); | |
977 | } | |
978 | ||
03d196b7 BR |
979 | size -= sizeof(hdr); |
980 | ||
10f12e64 | 981 | /* Create skeleton */ |
03d196b7 BR |
982 | fdt_skel = g_malloc0(size); |
983 | _FDT((fdt_create(fdt_skel, size))); | |
127f03e4 | 984 | _FDT((fdt_finish_reservemap(fdt_skel))); |
03d196b7 BR |
985 | _FDT((fdt_begin_node(fdt_skel, ""))); |
986 | _FDT((fdt_end_node(fdt_skel))); | |
987 | _FDT((fdt_finish(fdt_skel))); | |
988 | fdt = g_malloc0(size); | |
989 | _FDT((fdt_open_into(fdt_skel, fdt, size))); | |
990 | g_free(fdt_skel); | |
991 | ||
992 | /* Fixup cpu nodes */ | |
5b120785 | 993 | _FDT((spapr_fixup_cpu_dt(fdt, spapr))); |
03d196b7 | 994 | |
6787d27b MR |
995 | if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { |
996 | return -1; | |
03d196b7 BR |
997 | } |
998 | ||
999 | /* Pack resulting tree */ | |
1000 | _FDT((fdt_pack(fdt))); | |
1001 | ||
1002 | if (fdt_totalsize(fdt) + sizeof(hdr) > size) { | |
1003 | trace_spapr_cas_failed(size); | |
1004 | return -1; | |
1005 | } | |
1006 | ||
1007 | cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); | |
1008 | cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); | |
1009 | trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); | |
1010 | g_free(fdt); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
3f5dabce DG |
1015 | static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) |
1016 | { | |
1017 | int rtas; | |
1018 | GString *hypertas = g_string_sized_new(256); | |
1019 | GString *qemu_hypertas = g_string_sized_new(256); | |
1020 | uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; | |
0c9269a5 | 1021 | uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + |
b0c14ec4 | 1022 | memory_region_size(&MACHINE(spapr)->device_memory->mr); |
3f5dabce | 1023 | uint32_t lrdr_capacity[] = { |
0c9269a5 DH |
1024 | cpu_to_be32(max_device_addr >> 32), |
1025 | cpu_to_be32(max_device_addr & 0xffffffff), | |
3f5dabce DG |
1026 | 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), |
1027 | cpu_to_be32(max_cpus / smp_threads), | |
1028 | }; | |
da9f80fb SP |
1029 | uint32_t maxdomains[] = { |
1030 | cpu_to_be32(4), | |
1031 | cpu_to_be32(0), | |
1032 | cpu_to_be32(0), | |
1033 | cpu_to_be32(0), | |
3908a24f | 1034 | cpu_to_be32(nb_numa_nodes ? nb_numa_nodes : 1), |
da9f80fb | 1035 | }; |
3f5dabce DG |
1036 | |
1037 | _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); | |
1038 | ||
1039 | /* hypertas */ | |
1040 | add_str(hypertas, "hcall-pft"); | |
1041 | add_str(hypertas, "hcall-term"); | |
1042 | add_str(hypertas, "hcall-dabr"); | |
1043 | add_str(hypertas, "hcall-interrupt"); | |
1044 | add_str(hypertas, "hcall-tce"); | |
1045 | add_str(hypertas, "hcall-vio"); | |
1046 | add_str(hypertas, "hcall-splpar"); | |
1047 | add_str(hypertas, "hcall-bulk"); | |
1048 | add_str(hypertas, "hcall-set-mode"); | |
1049 | add_str(hypertas, "hcall-sprg0"); | |
1050 | add_str(hypertas, "hcall-copy"); | |
1051 | add_str(hypertas, "hcall-debug"); | |
1052 | add_str(qemu_hypertas, "hcall-memop1"); | |
1053 | ||
1054 | if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { | |
1055 | add_str(hypertas, "hcall-multi-tce"); | |
1056 | } | |
30f4b05b DG |
1057 | |
1058 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
1059 | add_str(hypertas, "hcall-hpt-resize"); | |
1060 | } | |
1061 | ||
3f5dabce DG |
1062 | _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", |
1063 | hypertas->str, hypertas->len)); | |
1064 | g_string_free(hypertas, TRUE); | |
1065 | _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", | |
1066 | qemu_hypertas->str, qemu_hypertas->len)); | |
1067 | g_string_free(qemu_hypertas, TRUE); | |
1068 | ||
1069 | _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", | |
1070 | refpoints, sizeof(refpoints))); | |
1071 | ||
da9f80fb SP |
1072 | _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", |
1073 | maxdomains, sizeof(maxdomains))); | |
1074 | ||
3f5dabce DG |
1075 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", |
1076 | RTAS_ERROR_LOG_MAX)); | |
1077 | _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", | |
1078 | RTAS_EVENT_SCAN_RATE)); | |
1079 | ||
4f441474 DG |
1080 | g_assert(msi_nonbroken); |
1081 | _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); | |
3f5dabce DG |
1082 | |
1083 | /* | |
1084 | * According to PAPR, rtas ibm,os-term does not guarantee a return | |
1085 | * back to the guest cpu. | |
1086 | * | |
1087 | * While an additional ibm,extended-os-term property indicates | |
1088 | * that rtas call return will always occur. Set this property. | |
1089 | */ | |
1090 | _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); | |
1091 | ||
1092 | _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", | |
1093 | lrdr_capacity, sizeof(lrdr_capacity))); | |
1094 | ||
1095 | spapr_dt_rtas_tokens(fdt, rtas); | |
1096 | } | |
1097 | ||
9fb4541f SB |
1098 | /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features |
1099 | * that the guest may request and thus the valid values for bytes 24..26 of | |
1100 | * option vector 5: */ | |
1101 | static void spapr_dt_ov5_platform_support(void *fdt, int chosen) | |
1102 | { | |
545d6e2b SJS |
1103 | PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); |
1104 | ||
f2b14e3a | 1105 | char val[2 * 4] = { |
21f3f8db | 1106 | 23, 0x00, /* Xive mode, filled in below. */ |
9fb4541f SB |
1107 | 24, 0x00, /* Hash/Radix, filled in below. */ |
1108 | 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ | |
1109 | 26, 0x40, /* Radix options: GTSE == yes. */ | |
1110 | }; | |
1111 | ||
7abd43ba SJS |
1112 | if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, |
1113 | first_ppc_cpu->compat_pvr)) { | |
1114 | /* If we're in a pre POWER9 compat mode then the guest should do hash */ | |
1115 | val[3] = 0x00; /* Hash */ | |
1116 | } else if (kvm_enabled()) { | |
9fb4541f | 1117 | if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { |
f2b14e3a | 1118 | val[3] = 0x80; /* OV5_MMU_BOTH */ |
9fb4541f | 1119 | } else if (kvmppc_has_cap_mmu_radix()) { |
f2b14e3a | 1120 | val[3] = 0x40; /* OV5_MMU_RADIX_300 */ |
9fb4541f | 1121 | } else { |
f2b14e3a | 1122 | val[3] = 0x00; /* Hash */ |
9fb4541f SB |
1123 | } |
1124 | } else { | |
7abd43ba SJS |
1125 | /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ |
1126 | val[3] = 0xC0; | |
9fb4541f SB |
1127 | } |
1128 | _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", | |
1129 | val, sizeof(val))); | |
1130 | } | |
1131 | ||
7c866c6a DG |
1132 | static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) |
1133 | { | |
1134 | MachineState *machine = MACHINE(spapr); | |
1135 | int chosen; | |
1136 | const char *boot_device = machine->boot_order; | |
1137 | char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); | |
1138 | size_t cb = 0; | |
907aac2f | 1139 | char *bootlist = get_boot_devices_list(&cb); |
7c866c6a DG |
1140 | |
1141 | _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); | |
1142 | ||
7c866c6a DG |
1143 | _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); |
1144 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", | |
1145 | spapr->initrd_base)); | |
1146 | _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", | |
1147 | spapr->initrd_base + spapr->initrd_size)); | |
1148 | ||
1149 | if (spapr->kernel_size) { | |
1150 | uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), | |
1151 | cpu_to_be64(spapr->kernel_size) }; | |
1152 | ||
1153 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", | |
1154 | &kprop, sizeof(kprop))); | |
1155 | if (spapr->kernel_le) { | |
1156 | _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); | |
1157 | } | |
1158 | } | |
1159 | if (boot_menu) { | |
1160 | _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); | |
1161 | } | |
1162 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); | |
1163 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); | |
1164 | _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); | |
1165 | ||
1166 | if (cb && bootlist) { | |
1167 | int i; | |
1168 | ||
1169 | for (i = 0; i < cb; i++) { | |
1170 | if (bootlist[i] == '\n') { | |
1171 | bootlist[i] = ' '; | |
1172 | } | |
1173 | } | |
1174 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); | |
1175 | } | |
1176 | ||
1177 | if (boot_device && strlen(boot_device)) { | |
1178 | _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); | |
1179 | } | |
1180 | ||
1181 | if (!spapr->has_graphics && stdout_path) { | |
90ee4e01 ND |
1182 | /* |
1183 | * "linux,stdout-path" and "stdout" properties are deprecated by linux | |
1184 | * kernel. New platforms should only use the "stdout-path" property. Set | |
1185 | * the new property and continue using older property to remain | |
1186 | * compatible with the existing firmware. | |
1187 | */ | |
7c866c6a | 1188 | _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); |
90ee4e01 | 1189 | _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); |
7c866c6a DG |
1190 | } |
1191 | ||
9fb4541f SB |
1192 | spapr_dt_ov5_platform_support(fdt, chosen); |
1193 | ||
7c866c6a DG |
1194 | g_free(stdout_path); |
1195 | g_free(bootlist); | |
1196 | } | |
1197 | ||
fca5f2dc DG |
1198 | static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) |
1199 | { | |
1200 | /* The /hypervisor node isn't in PAPR - this is a hack to allow PR | |
1201 | * KVM to work under pHyp with some guest co-operation */ | |
1202 | int hypervisor; | |
1203 | uint8_t hypercall[16]; | |
1204 | ||
1205 | _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); | |
1206 | /* indicate KVM hypercall interface */ | |
1207 | _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); | |
1208 | if (kvmppc_has_cap_fixup_hcalls()) { | |
1209 | /* | |
1210 | * Older KVM versions with older guest kernels were broken | |
1211 | * with the magic page, don't allow the guest to map it. | |
1212 | */ | |
1213 | if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, | |
1214 | sizeof(hypercall))) { | |
1215 | _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", | |
1216 | hypercall, sizeof(hypercall))); | |
1217 | } | |
1218 | } | |
1219 | } | |
1220 | ||
997b6cfc DG |
1221 | static void *spapr_build_fdt(sPAPRMachineState *spapr, |
1222 | hwaddr rtas_addr, | |
1223 | hwaddr rtas_size) | |
a3467baa | 1224 | { |
c86c1aff | 1225 | MachineState *machine = MACHINE(spapr); |
3c0c47e3 | 1226 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
c20d332a | 1227 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
7c866c6a | 1228 | int ret; |
a3467baa | 1229 | void *fdt; |
3384f95c | 1230 | sPAPRPHBState *phb; |
398a0bd5 | 1231 | char *buf; |
a3467baa | 1232 | |
398a0bd5 DG |
1233 | fdt = g_malloc0(FDT_MAX_SIZE); |
1234 | _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); | |
a3467baa | 1235 | |
398a0bd5 DG |
1236 | /* Root node */ |
1237 | _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); | |
1238 | _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); | |
1239 | _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); | |
1240 | ||
1241 | /* | |
1242 | * Add info to guest to indentify which host is it being run on | |
1243 | * and what is the uuid of the guest | |
1244 | */ | |
1245 | if (kvmppc_get_host_model(&buf)) { | |
1246 | _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); | |
1247 | g_free(buf); | |
1248 | } | |
1249 | if (kvmppc_get_host_serial(&buf)) { | |
1250 | _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); | |
1251 | g_free(buf); | |
1252 | } | |
1253 | ||
1254 | buf = qemu_uuid_unparse_strdup(&qemu_uuid); | |
1255 | ||
1256 | _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); | |
1257 | if (qemu_uuid_set) { | |
1258 | _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); | |
1259 | } | |
1260 | g_free(buf); | |
1261 | ||
1262 | if (qemu_get_vm_name()) { | |
1263 | _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", | |
1264 | qemu_get_vm_name())); | |
1265 | } | |
1266 | ||
1267 | _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); | |
1268 | _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); | |
4040ab72 | 1269 | |
fc7e0765 | 1270 | /* /interrupt controller */ |
6e21de4a CLG |
1271 | smc->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt, |
1272 | PHANDLE_XICP); | |
fc7e0765 | 1273 | |
e8f986fc BR |
1274 | ret = spapr_populate_memory(spapr, fdt); |
1275 | if (ret < 0) { | |
ce9863b7 | 1276 | error_report("couldn't setup memory nodes in fdt"); |
e8f986fc | 1277 | exit(1); |
7f763a5d DG |
1278 | } |
1279 | ||
bf5a6696 DG |
1280 | /* /vdevice */ |
1281 | spapr_dt_vdevice(spapr->vio_bus, fdt); | |
4040ab72 | 1282 | |
4d9392be TH |
1283 | if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { |
1284 | ret = spapr_rng_populate_dt(fdt); | |
1285 | if (ret < 0) { | |
ce9863b7 | 1286 | error_report("could not set up rng device in the fdt"); |
4d9392be TH |
1287 | exit(1); |
1288 | } | |
1289 | } | |
1290 | ||
3384f95c | 1291 | QLIST_FOREACH(phb, &spapr->phbs, list) { |
0976efd5 | 1292 | ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, smc->irq->nr_msis); |
da34fed7 TH |
1293 | if (ret < 0) { |
1294 | error_report("couldn't setup PCI devices in fdt"); | |
1295 | exit(1); | |
1296 | } | |
3384f95c DG |
1297 | } |
1298 | ||
0da6f3fe BR |
1299 | /* cpus */ |
1300 | spapr_populate_cpus_dt_node(fdt, spapr); | |
6e806cc3 | 1301 | |
c20d332a BR |
1302 | if (smc->dr_lmb_enabled) { |
1303 | _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); | |
1304 | } | |
1305 | ||
c5514d0e | 1306 | if (mc->has_hotpluggable_cpus) { |
af81cf32 BR |
1307 | int offset = fdt_path_offset(fdt, "/cpus"); |
1308 | ret = spapr_drc_populate_dt(fdt, offset, NULL, | |
1309 | SPAPR_DR_CONNECTOR_TYPE_CPU); | |
1310 | if (ret < 0) { | |
1311 | error_report("Couldn't set up CPU DR device tree properties"); | |
1312 | exit(1); | |
1313 | } | |
1314 | } | |
1315 | ||
ffb1e275 | 1316 | /* /event-sources */ |
ffbb1705 | 1317 | spapr_dt_events(spapr, fdt); |
ffb1e275 | 1318 | |
3f5dabce DG |
1319 | /* /rtas */ |
1320 | spapr_dt_rtas(spapr, fdt); | |
1321 | ||
7c866c6a DG |
1322 | /* /chosen */ |
1323 | spapr_dt_chosen(spapr, fdt); | |
cf6e5223 | 1324 | |
fca5f2dc DG |
1325 | /* /hypervisor */ |
1326 | if (kvm_enabled()) { | |
1327 | spapr_dt_hypervisor(spapr, fdt); | |
1328 | } | |
1329 | ||
cf6e5223 DG |
1330 | /* Build memory reserve map */ |
1331 | if (spapr->kernel_size) { | |
1332 | _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); | |
1333 | } | |
1334 | if (spapr->initrd_size) { | |
1335 | _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); | |
1336 | } | |
1337 | ||
6787d27b MR |
1338 | /* ibm,client-architecture-support updates */ |
1339 | ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); | |
1340 | if (ret < 0) { | |
1341 | error_report("couldn't setup CAS properties fdt"); | |
1342 | exit(1); | |
1343 | } | |
1344 | ||
997b6cfc | 1345 | return fdt; |
9fdf0c29 DG |
1346 | } |
1347 | ||
1348 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
1349 | { | |
1350 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
1351 | } | |
1352 | ||
1d1be34d DG |
1353 | static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, |
1354 | PowerPCCPU *cpu) | |
9fdf0c29 | 1355 | { |
1b14670a AF |
1356 | CPUPPCState *env = &cpu->env; |
1357 | ||
8d04fb55 JK |
1358 | /* The TCG path should also be holding the BQL at this point */ |
1359 | g_assert(qemu_mutex_iothread_locked()); | |
1360 | ||
efcb9383 DG |
1361 | if (msr_pr) { |
1362 | hcall_dprintf("Hypercall made with MSR[PR]=1\n"); | |
1363 | env->gpr[3] = H_PRIVILEGE; | |
1364 | } else { | |
aa100fa4 | 1365 | env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); |
efcb9383 | 1366 | } |
9fdf0c29 DG |
1367 | } |
1368 | ||
9861bb3e SJS |
1369 | static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) |
1370 | { | |
1371 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1372 | ||
1373 | return spapr->patb_entry; | |
1374 | } | |
1375 | ||
e6b8fd24 SMJ |
1376 | #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) |
1377 | #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) | |
1378 | #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) | |
1379 | #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) | |
1380 | #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) | |
1381 | ||
715c5407 DG |
1382 | /* |
1383 | * Get the fd to access the kernel htab, re-opening it if necessary | |
1384 | */ | |
1385 | static int get_htab_fd(sPAPRMachineState *spapr) | |
1386 | { | |
14b0d748 GK |
1387 | Error *local_err = NULL; |
1388 | ||
715c5407 DG |
1389 | if (spapr->htab_fd >= 0) { |
1390 | return spapr->htab_fd; | |
1391 | } | |
1392 | ||
14b0d748 | 1393 | spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); |
715c5407 | 1394 | if (spapr->htab_fd < 0) { |
14b0d748 | 1395 | error_report_err(local_err); |
715c5407 DG |
1396 | } |
1397 | ||
1398 | return spapr->htab_fd; | |
1399 | } | |
1400 | ||
b4db5413 | 1401 | void close_htab_fd(sPAPRMachineState *spapr) |
715c5407 DG |
1402 | { |
1403 | if (spapr->htab_fd >= 0) { | |
1404 | close(spapr->htab_fd); | |
1405 | } | |
1406 | spapr->htab_fd = -1; | |
1407 | } | |
1408 | ||
e57ca75c DG |
1409 | static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) |
1410 | { | |
1411 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1412 | ||
1413 | return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; | |
1414 | } | |
1415 | ||
1ec26c75 GK |
1416 | static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) |
1417 | { | |
1418 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1419 | ||
1420 | assert(kvm_enabled()); | |
1421 | ||
1422 | if (!spapr->htab) { | |
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); | |
1427 | } | |
1428 | ||
e57ca75c DG |
1429 | static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, |
1430 | hwaddr ptex, int n) | |
1431 | { | |
1432 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1433 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; | |
1434 | ||
1435 | if (!spapr->htab) { | |
1436 | /* | |
1437 | * HTAB is controlled by KVM. Fetch into temporary buffer | |
1438 | */ | |
1439 | ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); | |
1440 | kvmppc_read_hptes(hptes, ptex, n); | |
1441 | return hptes; | |
1442 | } | |
1443 | ||
1444 | /* | |
1445 | * HTAB is controlled by QEMU. Just point to the internally | |
1446 | * accessible PTEG. | |
1447 | */ | |
1448 | return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); | |
1449 | } | |
1450 | ||
1451 | static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, | |
1452 | const ppc_hash_pte64_t *hptes, | |
1453 | hwaddr ptex, int n) | |
1454 | { | |
1455 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1456 | ||
1457 | if (!spapr->htab) { | |
1458 | g_free((void *)hptes); | |
1459 | } | |
1460 | ||
1461 | /* Nothing to do for qemu managed HPT */ | |
1462 | } | |
1463 | ||
1464 | static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, | |
1465 | uint64_t pte0, uint64_t pte1) | |
1466 | { | |
1467 | sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); | |
1468 | hwaddr offset = ptex * HASH_PTE_SIZE_64; | |
1469 | ||
1470 | if (!spapr->htab) { | |
1471 | kvmppc_write_hpte(ptex, pte0, pte1); | |
1472 | } else { | |
1473 | stq_p(spapr->htab + offset, pte0); | |
1474 | stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
1475 | } | |
1476 | } | |
1477 | ||
0b0b8310 | 1478 | int spapr_hpt_shift_for_ramsize(uint64_t ramsize) |
8dfe8e7f DG |
1479 | { |
1480 | int shift; | |
1481 | ||
1482 | /* We aim for a hash table of size 1/128 the size of RAM (rounded | |
1483 | * up). The PAPR recommendation is actually 1/64 of RAM size, but | |
1484 | * that's much more than is needed for Linux guests */ | |
1485 | shift = ctz64(pow2ceil(ramsize)) - 7; | |
1486 | shift = MAX(shift, 18); /* Minimum architected size */ | |
1487 | shift = MIN(shift, 46); /* Maximum architected size */ | |
1488 | return shift; | |
1489 | } | |
1490 | ||
06ec79e8 BR |
1491 | void spapr_free_hpt(sPAPRMachineState *spapr) |
1492 | { | |
1493 | g_free(spapr->htab); | |
1494 | spapr->htab = NULL; | |
1495 | spapr->htab_shift = 0; | |
1496 | close_htab_fd(spapr); | |
1497 | } | |
1498 | ||
2772cf6b DG |
1499 | void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, |
1500 | Error **errp) | |
7f763a5d | 1501 | { |
c5f54f3e DG |
1502 | long rc; |
1503 | ||
1504 | /* Clean up any HPT info from a previous boot */ | |
06ec79e8 | 1505 | spapr_free_hpt(spapr); |
c5f54f3e DG |
1506 | |
1507 | rc = kvmppc_reset_htab(shift); | |
1508 | if (rc < 0) { | |
1509 | /* kernel-side HPT needed, but couldn't allocate one */ | |
1510 | error_setg_errno(errp, errno, | |
1511 | "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", | |
1512 | shift); | |
1513 | /* This is almost certainly fatal, but if the caller really | |
1514 | * wants to carry on with shift == 0, it's welcome to try */ | |
1515 | } else if (rc > 0) { | |
1516 | /* kernel-side HPT allocated */ | |
1517 | if (rc != shift) { | |
1518 | error_setg(errp, | |
1519 | "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", | |
1520 | shift, rc); | |
7735feda BR |
1521 | } |
1522 | ||
7f763a5d | 1523 | spapr->htab_shift = shift; |
c18ad9a5 | 1524 | spapr->htab = NULL; |
b817772a | 1525 | } else { |
c5f54f3e DG |
1526 | /* kernel-side HPT not needed, allocate in userspace instead */ |
1527 | size_t size = 1ULL << shift; | |
1528 | int i; | |
b817772a | 1529 | |
c5f54f3e DG |
1530 | spapr->htab = qemu_memalign(size, size); |
1531 | if (!spapr->htab) { | |
1532 | error_setg_errno(errp, errno, | |
1533 | "Could not allocate HPT of order %d", shift); | |
1534 | return; | |
7735feda BR |
1535 | } |
1536 | ||
c5f54f3e DG |
1537 | memset(spapr->htab, 0, size); |
1538 | spapr->htab_shift = shift; | |
e6b8fd24 | 1539 | |
c5f54f3e DG |
1540 | for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { |
1541 | DIRTY_HPTE(HPTE(spapr->htab, i)); | |
e6b8fd24 | 1542 | } |
7f763a5d | 1543 | } |
ee4d9ecc SJS |
1544 | /* We're setting up a hash table, so that means we're not radix */ |
1545 | spapr->patb_entry = 0; | |
9fdf0c29 DG |
1546 | } |
1547 | ||
b4db5413 SJS |
1548 | void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) |
1549 | { | |
2772cf6b DG |
1550 | int hpt_shift; |
1551 | ||
1552 | if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) | |
1553 | || (spapr->cas_reboot | |
1554 | && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { | |
1555 | hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); | |
1556 | } else { | |
768a20f3 DG |
1557 | uint64_t current_ram_size; |
1558 | ||
1559 | current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); | |
1560 | hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); | |
2772cf6b DG |
1561 | } |
1562 | spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); | |
1563 | ||
b4db5413 | 1564 | if (spapr->vrma_adjust) { |
c86c1aff | 1565 | spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), |
b4db5413 SJS |
1566 | spapr->htab_shift); |
1567 | } | |
b4db5413 SJS |
1568 | } |
1569 | ||
82512483 GK |
1570 | static int spapr_reset_drcs(Object *child, void *opaque) |
1571 | { | |
1572 | sPAPRDRConnector *drc = | |
1573 | (sPAPRDRConnector *) object_dynamic_cast(child, | |
1574 | TYPE_SPAPR_DR_CONNECTOR); | |
1575 | ||
1576 | if (drc) { | |
1577 | spapr_drc_reset(drc); | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
bcb5ce08 | 1583 | static void spapr_machine_reset(void) |
a3467baa | 1584 | { |
c5f54f3e DG |
1585 | MachineState *machine = MACHINE(qdev_get_machine()); |
1586 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); | |
182735ef | 1587 | PowerPCCPU *first_ppc_cpu; |
b7d1f77a | 1588 | uint32_t rtas_limit; |
cae172ab | 1589 | hwaddr rtas_addr, fdt_addr; |
997b6cfc DG |
1590 | void *fdt; |
1591 | int rc; | |
259186a7 | 1592 | |
9f6edd06 | 1593 | spapr_caps_apply(spapr); |
33face6b | 1594 | |
1481fe5f LV |
1595 | first_ppc_cpu = POWERPC_CPU(first_cpu); |
1596 | if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && | |
ad99d04c DG |
1597 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
1598 | spapr->max_compat_pvr)) { | |
b4db5413 SJS |
1599 | /* If using KVM with radix mode available, VCPUs can be started |
1600 | * without a HPT because KVM will start them in radix mode. | |
1601 | * Set the GR bit in PATB so that we know there is no HPT. */ | |
1602 | spapr->patb_entry = PATBE1_GR; | |
1603 | } else { | |
b4db5413 | 1604 | spapr_setup_hpt_and_vrma(spapr); |
c5f54f3e | 1605 | } |
a3467baa | 1606 | |
9012a53f GK |
1607 | /* if this reset wasn't generated by CAS, we should reset our |
1608 | * negotiated options and start from scratch */ | |
1609 | if (!spapr->cas_reboot) { | |
1610 | spapr_ovec_cleanup(spapr->ov5_cas); | |
1611 | spapr->ov5_cas = spapr_ovec_new(); | |
1612 | ||
1613 | ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal); | |
1614 | } | |
1615 | ||
82cffa2e CLG |
1616 | if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { |
1617 | spapr_irq_msi_reset(spapr); | |
1618 | } | |
1619 | ||
c8787ad4 | 1620 | qemu_devices_reset(); |
82512483 GK |
1621 | |
1622 | /* DRC reset may cause a device to be unplugged. This will cause troubles | |
1623 | * if this device is used by another device (eg, a running vhost backend | |
1624 | * will crash QEMU if the DIMM holding the vring goes away). To avoid such | |
1625 | * situations, we reset DRCs after all devices have been reset. | |
1626 | */ | |
1627 | object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL); | |
1628 | ||
56258174 | 1629 | spapr_clear_pending_events(spapr); |
a3467baa | 1630 | |
b7d1f77a BH |
1631 | /* |
1632 | * We place the device tree and RTAS just below either the top of the RMA, | |
1633 | * or just below 2GB, whichever is lowere, so that it can be | |
1634 | * processed with 32-bit real mode code if necessary | |
1635 | */ | |
1636 | rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); | |
cae172ab DG |
1637 | rtas_addr = rtas_limit - RTAS_MAX_SIZE; |
1638 | fdt_addr = rtas_addr - FDT_MAX_SIZE; | |
b7d1f77a | 1639 | |
cae172ab | 1640 | fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); |
a3467baa | 1641 | |
2cac78c1 | 1642 | spapr_load_rtas(spapr, fdt, rtas_addr); |
b7d1f77a | 1643 | |
997b6cfc DG |
1644 | rc = fdt_pack(fdt); |
1645 | ||
1646 | /* Should only fail if we've built a corrupted tree */ | |
1647 | assert(rc == 0); | |
1648 | ||
1649 | if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { | |
1650 | error_report("FDT too big ! 0x%x bytes (max is 0x%x)", | |
1651 | fdt_totalsize(fdt), FDT_MAX_SIZE); | |
1652 | exit(1); | |
1653 | } | |
1654 | ||
1655 | /* Load the fdt */ | |
1656 | qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); | |
cae172ab | 1657 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
997b6cfc DG |
1658 | g_free(fdt); |
1659 | ||
a3467baa | 1660 | /* Set up the entry state */ |
84369f63 | 1661 | spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); |
182735ef | 1662 | first_ppc_cpu->env.gpr[5] = 0; |
a3467baa | 1663 | |
6787d27b | 1664 | spapr->cas_reboot = false; |
a3467baa DG |
1665 | } |
1666 | ||
28e02042 | 1667 | static void spapr_create_nvram(sPAPRMachineState *spapr) |
639e8102 | 1668 | { |
2ff3de68 | 1669 | DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); |
3978b863 | 1670 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
639e8102 | 1671 | |
3978b863 | 1672 | if (dinfo) { |
6231a6da MA |
1673 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), |
1674 | &error_fatal); | |
639e8102 DG |
1675 | } |
1676 | ||
1677 | qdev_init_nofail(dev); | |
1678 | ||
1679 | spapr->nvram = (struct sPAPRNVRAM *)dev; | |
1680 | } | |
1681 | ||
28e02042 | 1682 | static void spapr_rtc_create(sPAPRMachineState *spapr) |
28df36a1 | 1683 | { |
147ff807 CLG |
1684 | object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); |
1685 | object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), | |
1686 | &error_fatal); | |
1687 | object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", | |
1688 | &error_fatal); | |
1689 | object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), | |
1690 | "date", &error_fatal); | |
28df36a1 DG |
1691 | } |
1692 | ||
8c57b867 | 1693 | /* Returns whether we want to use VGA or not */ |
14c6a894 | 1694 | static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) |
f28359d8 | 1695 | { |
8c57b867 | 1696 | switch (vga_interface_type) { |
8c57b867 | 1697 | case VGA_NONE: |
7effdaa3 MW |
1698 | return false; |
1699 | case VGA_DEVICE: | |
1700 | return true; | |
1ddcae82 | 1701 | case VGA_STD: |
b798c190 | 1702 | case VGA_VIRTIO: |
1ddcae82 | 1703 | return pci_vga_init(pci_bus) != NULL; |
8c57b867 | 1704 | default: |
14c6a894 DG |
1705 | error_setg(errp, |
1706 | "Unsupported VGA mode, only -vga std or -vga virtio is supported"); | |
1707 | return false; | |
f28359d8 | 1708 | } |
f28359d8 LZ |
1709 | } |
1710 | ||
4e5fe368 SJS |
1711 | static int spapr_pre_load(void *opaque) |
1712 | { | |
1713 | int rc; | |
1714 | ||
1715 | rc = spapr_caps_pre_load(opaque); | |
1716 | if (rc) { | |
1717 | return rc; | |
1718 | } | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
880ae7de DG |
1723 | static int spapr_post_load(void *opaque, int version_id) |
1724 | { | |
28e02042 | 1725 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; |
880ae7de DG |
1726 | int err = 0; |
1727 | ||
be85537d DG |
1728 | err = spapr_caps_post_migration(spapr); |
1729 | if (err) { | |
1730 | return err; | |
1731 | } | |
1732 | ||
a7ff1212 | 1733 | if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { |
5bc8d26d CLG |
1734 | CPUState *cs; |
1735 | CPU_FOREACH(cs) { | |
1736 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1737 | icp_resend(ICP(cpu->intc)); | |
a7ff1212 CLG |
1738 | } |
1739 | } | |
1740 | ||
631b22ea | 1741 | /* In earlier versions, there was no separate qdev for the PAPR |
880ae7de DG |
1742 | * RTC, so the RTC offset was stored directly in sPAPREnvironment. |
1743 | * So when migrating from those versions, poke the incoming offset | |
1744 | * value into the RTC device */ | |
1745 | if (version_id < 3) { | |
147ff807 | 1746 | err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); |
880ae7de DG |
1747 | } |
1748 | ||
0c86b2df | 1749 | if (kvm_enabled() && spapr->patb_entry) { |
d39c90f5 BR |
1750 | PowerPCCPU *cpu = POWERPC_CPU(first_cpu); |
1751 | bool radix = !!(spapr->patb_entry & PATBE1_GR); | |
1752 | bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); | |
1753 | ||
1754 | err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); | |
1755 | if (err) { | |
1756 | error_report("Process table config unsupported by the host"); | |
1757 | return -EINVAL; | |
1758 | } | |
1759 | } | |
1760 | ||
880ae7de DG |
1761 | return err; |
1762 | } | |
1763 | ||
4e5fe368 SJS |
1764 | static int spapr_pre_save(void *opaque) |
1765 | { | |
1766 | int rc; | |
1767 | ||
1768 | rc = spapr_caps_pre_save(opaque); | |
1769 | if (rc) { | |
1770 | return rc; | |
1771 | } | |
1772 | ||
1773 | return 0; | |
1774 | } | |
1775 | ||
880ae7de DG |
1776 | static bool version_before_3(void *opaque, int version_id) |
1777 | { | |
1778 | return version_id < 3; | |
1779 | } | |
1780 | ||
fd38804b DHB |
1781 | static bool spapr_pending_events_needed(void *opaque) |
1782 | { | |
1783 | sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; | |
1784 | return !QTAILQ_EMPTY(&spapr->pending_events); | |
1785 | } | |
1786 | ||
1787 | static const VMStateDescription vmstate_spapr_event_entry = { | |
1788 | .name = "spapr_event_log_entry", | |
1789 | .version_id = 1, | |
1790 | .minimum_version_id = 1, | |
1791 | .fields = (VMStateField[]) { | |
5341258e DG |
1792 | VMSTATE_UINT32(summary, sPAPREventLogEntry), |
1793 | VMSTATE_UINT32(extended_length, sPAPREventLogEntry), | |
fd38804b | 1794 | VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, |
5341258e | 1795 | NULL, extended_length), |
fd38804b DHB |
1796 | VMSTATE_END_OF_LIST() |
1797 | }, | |
1798 | }; | |
1799 | ||
1800 | static const VMStateDescription vmstate_spapr_pending_events = { | |
1801 | .name = "spapr_pending_events", | |
1802 | .version_id = 1, | |
1803 | .minimum_version_id = 1, | |
1804 | .needed = spapr_pending_events_needed, | |
1805 | .fields = (VMStateField[]) { | |
1806 | VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, | |
1807 | vmstate_spapr_event_entry, sPAPREventLogEntry, next), | |
1808 | VMSTATE_END_OF_LIST() | |
1809 | }, | |
1810 | }; | |
1811 | ||
62ef3760 MR |
1812 | static bool spapr_ov5_cas_needed(void *opaque) |
1813 | { | |
1814 | sPAPRMachineState *spapr = opaque; | |
1815 | sPAPROptionVector *ov5_mask = spapr_ovec_new(); | |
1816 | sPAPROptionVector *ov5_legacy = spapr_ovec_new(); | |
1817 | sPAPROptionVector *ov5_removed = spapr_ovec_new(); | |
1818 | bool cas_needed; | |
1819 | ||
1820 | /* Prior to the introduction of sPAPROptionVector, we had two option | |
1821 | * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. | |
1822 | * Both of these options encode machine topology into the device-tree | |
1823 | * in such a way that the now-booted OS should still be able to interact | |
1824 | * appropriately with QEMU regardless of what options were actually | |
1825 | * negotiatied on the source side. | |
1826 | * | |
1827 | * As such, we can avoid migrating the CAS-negotiated options if these | |
1828 | * are the only options available on the current machine/platform. | |
1829 | * Since these are the only options available for pseries-2.7 and | |
1830 | * earlier, this allows us to maintain old->new/new->old migration | |
1831 | * compatibility. | |
1832 | * | |
1833 | * For QEMU 2.8+, there are additional CAS-negotiatable options available | |
1834 | * via default pseries-2.8 machines and explicit command-line parameters. | |
1835 | * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware | |
1836 | * of the actual CAS-negotiated values to continue working properly. For | |
1837 | * example, availability of memory unplug depends on knowing whether | |
1838 | * OV5_HP_EVT was negotiated via CAS. | |
1839 | * | |
1840 | * Thus, for any cases where the set of available CAS-negotiatable | |
1841 | * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we | |
aef19c04 GK |
1842 | * include the CAS-negotiated options in the migration stream, unless |
1843 | * if they affect boot time behaviour only. | |
62ef3760 MR |
1844 | */ |
1845 | spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); | |
1846 | spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); | |
aef19c04 | 1847 | spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); |
62ef3760 MR |
1848 | |
1849 | /* spapr_ovec_diff returns true if bits were removed. we avoid using | |
1850 | * the mask itself since in the future it's possible "legacy" bits may be | |
1851 | * removed via machine options, which could generate a false positive | |
1852 | * that breaks migration. | |
1853 | */ | |
1854 | spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); | |
1855 | cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); | |
1856 | ||
1857 | spapr_ovec_cleanup(ov5_mask); | |
1858 | spapr_ovec_cleanup(ov5_legacy); | |
1859 | spapr_ovec_cleanup(ov5_removed); | |
1860 | ||
1861 | return cas_needed; | |
1862 | } | |
1863 | ||
1864 | static const VMStateDescription vmstate_spapr_ov5_cas = { | |
1865 | .name = "spapr_option_vector_ov5_cas", | |
1866 | .version_id = 1, | |
1867 | .minimum_version_id = 1, | |
1868 | .needed = spapr_ov5_cas_needed, | |
1869 | .fields = (VMStateField[]) { | |
1870 | VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, | |
1871 | vmstate_spapr_ovec, sPAPROptionVector), | |
1872 | VMSTATE_END_OF_LIST() | |
1873 | }, | |
1874 | }; | |
1875 | ||
9861bb3e SJS |
1876 | static bool spapr_patb_entry_needed(void *opaque) |
1877 | { | |
1878 | sPAPRMachineState *spapr = opaque; | |
1879 | ||
1880 | return !!spapr->patb_entry; | |
1881 | } | |
1882 | ||
1883 | static const VMStateDescription vmstate_spapr_patb_entry = { | |
1884 | .name = "spapr_patb_entry", | |
1885 | .version_id = 1, | |
1886 | .minimum_version_id = 1, | |
1887 | .needed = spapr_patb_entry_needed, | |
1888 | .fields = (VMStateField[]) { | |
1889 | VMSTATE_UINT64(patb_entry, sPAPRMachineState), | |
1890 | VMSTATE_END_OF_LIST() | |
1891 | }, | |
1892 | }; | |
1893 | ||
82cffa2e CLG |
1894 | static bool spapr_irq_map_needed(void *opaque) |
1895 | { | |
1896 | sPAPRMachineState *spapr = opaque; | |
1897 | ||
1898 | return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); | |
1899 | } | |
1900 | ||
1901 | static const VMStateDescription vmstate_spapr_irq_map = { | |
1902 | .name = "spapr_irq_map", | |
1903 | .version_id = 1, | |
1904 | .minimum_version_id = 1, | |
1905 | .needed = spapr_irq_map_needed, | |
1906 | .fields = (VMStateField[]) { | |
1907 | VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr), | |
1908 | VMSTATE_END_OF_LIST() | |
1909 | }, | |
1910 | }; | |
1911 | ||
4be21d56 DG |
1912 | static const VMStateDescription vmstate_spapr = { |
1913 | .name = "spapr", | |
880ae7de | 1914 | .version_id = 3, |
4be21d56 | 1915 | .minimum_version_id = 1, |
4e5fe368 | 1916 | .pre_load = spapr_pre_load, |
880ae7de | 1917 | .post_load = spapr_post_load, |
4e5fe368 | 1918 | .pre_save = spapr_pre_save, |
3aff6c2f | 1919 | .fields = (VMStateField[]) { |
880ae7de DG |
1920 | /* used to be @next_irq */ |
1921 | VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), | |
4be21d56 DG |
1922 | |
1923 | /* RTC offset */ | |
28e02042 | 1924 | VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), |
880ae7de | 1925 | |
28e02042 | 1926 | VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), |
4be21d56 DG |
1927 | VMSTATE_END_OF_LIST() |
1928 | }, | |
62ef3760 MR |
1929 | .subsections = (const VMStateDescription*[]) { |
1930 | &vmstate_spapr_ov5_cas, | |
9861bb3e | 1931 | &vmstate_spapr_patb_entry, |
fd38804b | 1932 | &vmstate_spapr_pending_events, |
4e5fe368 SJS |
1933 | &vmstate_spapr_cap_htm, |
1934 | &vmstate_spapr_cap_vsx, | |
1935 | &vmstate_spapr_cap_dfp, | |
8f38eaf8 | 1936 | &vmstate_spapr_cap_cfpc, |
09114fd8 | 1937 | &vmstate_spapr_cap_sbbc, |
4be8d4e7 | 1938 | &vmstate_spapr_cap_ibs, |
82cffa2e | 1939 | &vmstate_spapr_irq_map, |
b9a477b7 | 1940 | &vmstate_spapr_cap_nested_kvm_hv, |
62ef3760 MR |
1941 | NULL |
1942 | } | |
4be21d56 DG |
1943 | }; |
1944 | ||
4be21d56 DG |
1945 | static int htab_save_setup(QEMUFile *f, void *opaque) |
1946 | { | |
28e02042 | 1947 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 1948 | |
4be21d56 | 1949 | /* "Iteration" header */ |
3a384297 BR |
1950 | if (!spapr->htab_shift) { |
1951 | qemu_put_be32(f, -1); | |
1952 | } else { | |
1953 | qemu_put_be32(f, spapr->htab_shift); | |
1954 | } | |
4be21d56 | 1955 | |
e68cb8b4 AK |
1956 | if (spapr->htab) { |
1957 | spapr->htab_save_index = 0; | |
1958 | spapr->htab_first_pass = true; | |
1959 | } else { | |
3a384297 BR |
1960 | if (spapr->htab_shift) { |
1961 | assert(kvm_enabled()); | |
1962 | } | |
e68cb8b4 AK |
1963 | } |
1964 | ||
1965 | ||
4be21d56 DG |
1966 | return 0; |
1967 | } | |
1968 | ||
332f7721 GK |
1969 | static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, |
1970 | int chunkstart, int n_valid, int n_invalid) | |
1971 | { | |
1972 | qemu_put_be32(f, chunkstart); | |
1973 | qemu_put_be16(f, n_valid); | |
1974 | qemu_put_be16(f, n_invalid); | |
1975 | qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), | |
1976 | HASH_PTE_SIZE_64 * n_valid); | |
1977 | } | |
1978 | ||
1979 | static void htab_save_end_marker(QEMUFile *f) | |
1980 | { | |
1981 | qemu_put_be32(f, 0); | |
1982 | qemu_put_be16(f, 0); | |
1983 | qemu_put_be16(f, 0); | |
1984 | } | |
1985 | ||
28e02042 | 1986 | static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, |
4be21d56 DG |
1987 | int64_t max_ns) |
1988 | { | |
378bc217 | 1989 | bool has_timeout = max_ns != -1; |
4be21d56 DG |
1990 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; |
1991 | int index = spapr->htab_save_index; | |
bc72ad67 | 1992 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
1993 | |
1994 | assert(spapr->htab_first_pass); | |
1995 | ||
1996 | do { | |
1997 | int chunkstart; | |
1998 | ||
1999 | /* Consume invalid HPTEs */ | |
2000 | while ((index < htabslots) | |
2001 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
4be21d56 | 2002 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2003 | index++; |
4be21d56 DG |
2004 | } |
2005 | ||
2006 | /* Consume valid HPTEs */ | |
2007 | chunkstart = index; | |
338c25b6 | 2008 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 | 2009 | && HPTE_VALID(HPTE(spapr->htab, index))) { |
4be21d56 | 2010 | CLEAN_HPTE(HPTE(spapr->htab, index)); |
24ec2863 | 2011 | index++; |
4be21d56 DG |
2012 | } |
2013 | ||
2014 | if (index > chunkstart) { | |
2015 | int n_valid = index - chunkstart; | |
2016 | ||
332f7721 | 2017 | htab_save_chunk(f, spapr, chunkstart, n_valid, 0); |
4be21d56 | 2018 | |
378bc217 DG |
2019 | if (has_timeout && |
2020 | (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { | |
4be21d56 DG |
2021 | break; |
2022 | } | |
2023 | } | |
2024 | } while ((index < htabslots) && !qemu_file_rate_limit(f)); | |
2025 | ||
2026 | if (index >= htabslots) { | |
2027 | assert(index == htabslots); | |
2028 | index = 0; | |
2029 | spapr->htab_first_pass = false; | |
2030 | } | |
2031 | spapr->htab_save_index = index; | |
2032 | } | |
2033 | ||
28e02042 | 2034 | static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, |
e68cb8b4 | 2035 | int64_t max_ns) |
4be21d56 DG |
2036 | { |
2037 | bool final = max_ns < 0; | |
2038 | int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; | |
2039 | int examined = 0, sent = 0; | |
2040 | int index = spapr->htab_save_index; | |
bc72ad67 | 2041 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
4be21d56 DG |
2042 | |
2043 | assert(!spapr->htab_first_pass); | |
2044 | ||
2045 | do { | |
2046 | int chunkstart, invalidstart; | |
2047 | ||
2048 | /* Consume non-dirty HPTEs */ | |
2049 | while ((index < htabslots) | |
2050 | && !HPTE_DIRTY(HPTE(spapr->htab, index))) { | |
2051 | index++; | |
2052 | examined++; | |
2053 | } | |
2054 | ||
2055 | chunkstart = index; | |
2056 | /* Consume valid dirty HPTEs */ | |
338c25b6 | 2057 | while ((index < htabslots) && (index - chunkstart < USHRT_MAX) |
4be21d56 DG |
2058 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2059 | && HPTE_VALID(HPTE(spapr->htab, index))) { | |
2060 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2061 | index++; | |
2062 | examined++; | |
2063 | } | |
2064 | ||
2065 | invalidstart = index; | |
2066 | /* Consume invalid dirty HPTEs */ | |
338c25b6 | 2067 | while ((index < htabslots) && (index - invalidstart < USHRT_MAX) |
4be21d56 DG |
2068 | && HPTE_DIRTY(HPTE(spapr->htab, index)) |
2069 | && !HPTE_VALID(HPTE(spapr->htab, index))) { | |
2070 | CLEAN_HPTE(HPTE(spapr->htab, index)); | |
2071 | index++; | |
2072 | examined++; | |
2073 | } | |
2074 | ||
2075 | if (index > chunkstart) { | |
2076 | int n_valid = invalidstart - chunkstart; | |
2077 | int n_invalid = index - invalidstart; | |
2078 | ||
332f7721 | 2079 | htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); |
4be21d56 DG |
2080 | sent += index - chunkstart; |
2081 | ||
bc72ad67 | 2082 | if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { |
4be21d56 DG |
2083 | break; |
2084 | } | |
2085 | } | |
2086 | ||
2087 | if (examined >= htabslots) { | |
2088 | break; | |
2089 | } | |
2090 | ||
2091 | if (index >= htabslots) { | |
2092 | assert(index == htabslots); | |
2093 | index = 0; | |
2094 | } | |
2095 | } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); | |
2096 | ||
2097 | if (index >= htabslots) { | |
2098 | assert(index == htabslots); | |
2099 | index = 0; | |
2100 | } | |
2101 | ||
2102 | spapr->htab_save_index = index; | |
2103 | ||
e68cb8b4 | 2104 | return (examined >= htabslots) && (sent == 0) ? 1 : 0; |
4be21d56 DG |
2105 | } |
2106 | ||
e68cb8b4 AK |
2107 | #define MAX_ITERATION_NS 5000000 /* 5 ms */ |
2108 | #define MAX_KVM_BUF_SIZE 2048 | |
2109 | ||
4be21d56 DG |
2110 | static int htab_save_iterate(QEMUFile *f, void *opaque) |
2111 | { | |
28e02042 | 2112 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2113 | int fd; |
e68cb8b4 | 2114 | int rc = 0; |
4be21d56 DG |
2115 | |
2116 | /* Iteration header */ | |
3a384297 BR |
2117 | if (!spapr->htab_shift) { |
2118 | qemu_put_be32(f, -1); | |
e8cd4247 | 2119 | return 1; |
3a384297 BR |
2120 | } else { |
2121 | qemu_put_be32(f, 0); | |
2122 | } | |
4be21d56 | 2123 | |
e68cb8b4 AK |
2124 | if (!spapr->htab) { |
2125 | assert(kvm_enabled()); | |
2126 | ||
715c5407 DG |
2127 | fd = get_htab_fd(spapr); |
2128 | if (fd < 0) { | |
2129 | return fd; | |
01a57972 SMJ |
2130 | } |
2131 | ||
715c5407 | 2132 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); |
e68cb8b4 AK |
2133 | if (rc < 0) { |
2134 | return rc; | |
2135 | } | |
2136 | } else if (spapr->htab_first_pass) { | |
4be21d56 DG |
2137 | htab_save_first_pass(f, spapr, MAX_ITERATION_NS); |
2138 | } else { | |
e68cb8b4 | 2139 | rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); |
4be21d56 DG |
2140 | } |
2141 | ||
332f7721 | 2142 | htab_save_end_marker(f); |
4be21d56 | 2143 | |
e68cb8b4 | 2144 | return rc; |
4be21d56 DG |
2145 | } |
2146 | ||
2147 | static int htab_save_complete(QEMUFile *f, void *opaque) | |
2148 | { | |
28e02042 | 2149 | sPAPRMachineState *spapr = opaque; |
715c5407 | 2150 | int fd; |
4be21d56 DG |
2151 | |
2152 | /* Iteration header */ | |
3a384297 BR |
2153 | if (!spapr->htab_shift) { |
2154 | qemu_put_be32(f, -1); | |
2155 | return 0; | |
2156 | } else { | |
2157 | qemu_put_be32(f, 0); | |
2158 | } | |
4be21d56 | 2159 | |
e68cb8b4 AK |
2160 | if (!spapr->htab) { |
2161 | int rc; | |
2162 | ||
2163 | assert(kvm_enabled()); | |
2164 | ||
715c5407 DG |
2165 | fd = get_htab_fd(spapr); |
2166 | if (fd < 0) { | |
2167 | return fd; | |
01a57972 SMJ |
2168 | } |
2169 | ||
715c5407 | 2170 | rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); |
e68cb8b4 AK |
2171 | if (rc < 0) { |
2172 | return rc; | |
2173 | } | |
e68cb8b4 | 2174 | } else { |
378bc217 DG |
2175 | if (spapr->htab_first_pass) { |
2176 | htab_save_first_pass(f, spapr, -1); | |
2177 | } | |
e68cb8b4 AK |
2178 | htab_save_later_pass(f, spapr, -1); |
2179 | } | |
4be21d56 DG |
2180 | |
2181 | /* End marker */ | |
332f7721 | 2182 | htab_save_end_marker(f); |
4be21d56 DG |
2183 | |
2184 | return 0; | |
2185 | } | |
2186 | ||
2187 | static int htab_load(QEMUFile *f, void *opaque, int version_id) | |
2188 | { | |
28e02042 | 2189 | sPAPRMachineState *spapr = opaque; |
4be21d56 | 2190 | uint32_t section_hdr; |
e68cb8b4 | 2191 | int fd = -1; |
14b0d748 | 2192 | Error *local_err = NULL; |
4be21d56 DG |
2193 | |
2194 | if (version_id < 1 || version_id > 1) { | |
98a5d100 | 2195 | error_report("htab_load() bad version"); |
4be21d56 DG |
2196 | return -EINVAL; |
2197 | } | |
2198 | ||
2199 | section_hdr = qemu_get_be32(f); | |
2200 | ||
3a384297 BR |
2201 | if (section_hdr == -1) { |
2202 | spapr_free_hpt(spapr); | |
2203 | return 0; | |
2204 | } | |
2205 | ||
4be21d56 | 2206 | if (section_hdr) { |
c5f54f3e DG |
2207 | /* First section gives the htab size */ |
2208 | spapr_reallocate_hpt(spapr, section_hdr, &local_err); | |
2209 | if (local_err) { | |
2210 | error_report_err(local_err); | |
4be21d56 DG |
2211 | return -EINVAL; |
2212 | } | |
2213 | return 0; | |
2214 | } | |
2215 | ||
e68cb8b4 AK |
2216 | if (!spapr->htab) { |
2217 | assert(kvm_enabled()); | |
2218 | ||
14b0d748 | 2219 | fd = kvmppc_get_htab_fd(true, 0, &local_err); |
e68cb8b4 | 2220 | if (fd < 0) { |
14b0d748 | 2221 | error_report_err(local_err); |
82be8e73 | 2222 | return fd; |
e68cb8b4 AK |
2223 | } |
2224 | } | |
2225 | ||
4be21d56 DG |
2226 | while (true) { |
2227 | uint32_t index; | |
2228 | uint16_t n_valid, n_invalid; | |
2229 | ||
2230 | index = qemu_get_be32(f); | |
2231 | n_valid = qemu_get_be16(f); | |
2232 | n_invalid = qemu_get_be16(f); | |
2233 | ||
2234 | if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { | |
2235 | /* End of Stream */ | |
2236 | break; | |
2237 | } | |
2238 | ||
e68cb8b4 | 2239 | if ((index + n_valid + n_invalid) > |
4be21d56 DG |
2240 | (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { |
2241 | /* Bad index in stream */ | |
98a5d100 DG |
2242 | error_report( |
2243 | "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", | |
2244 | index, n_valid, n_invalid, spapr->htab_shift); | |
4be21d56 DG |
2245 | return -EINVAL; |
2246 | } | |
2247 | ||
e68cb8b4 AK |
2248 | if (spapr->htab) { |
2249 | if (n_valid) { | |
2250 | qemu_get_buffer(f, HPTE(spapr->htab, index), | |
2251 | HASH_PTE_SIZE_64 * n_valid); | |
2252 | } | |
2253 | if (n_invalid) { | |
2254 | memset(HPTE(spapr->htab, index + n_valid), 0, | |
2255 | HASH_PTE_SIZE_64 * n_invalid); | |
2256 | } | |
2257 | } else { | |
2258 | int rc; | |
2259 | ||
2260 | assert(fd >= 0); | |
2261 | ||
2262 | rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); | |
2263 | if (rc < 0) { | |
2264 | return rc; | |
2265 | } | |
4be21d56 DG |
2266 | } |
2267 | } | |
2268 | ||
e68cb8b4 AK |
2269 | if (!spapr->htab) { |
2270 | assert(fd >= 0); | |
2271 | close(fd); | |
2272 | } | |
2273 | ||
4be21d56 DG |
2274 | return 0; |
2275 | } | |
2276 | ||
70f794fc | 2277 | static void htab_save_cleanup(void *opaque) |
c573fc03 TH |
2278 | { |
2279 | sPAPRMachineState *spapr = opaque; | |
2280 | ||
2281 | close_htab_fd(spapr); | |
2282 | } | |
2283 | ||
4be21d56 | 2284 | static SaveVMHandlers savevm_htab_handlers = { |
9907e842 | 2285 | .save_setup = htab_save_setup, |
4be21d56 | 2286 | .save_live_iterate = htab_save_iterate, |
a3e06c3d | 2287 | .save_live_complete_precopy = htab_save_complete, |
70f794fc | 2288 | .save_cleanup = htab_save_cleanup, |
4be21d56 DG |
2289 | .load_state = htab_load, |
2290 | }; | |
2291 | ||
5b2128d2 AG |
2292 | static void spapr_boot_set(void *opaque, const char *boot_device, |
2293 | Error **errp) | |
2294 | { | |
c86c1aff | 2295 | MachineState *machine = MACHINE(opaque); |
5b2128d2 AG |
2296 | machine->boot_order = g_strdup(boot_device); |
2297 | } | |
2298 | ||
224245bf DG |
2299 | static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) |
2300 | { | |
2301 | MachineState *machine = MACHINE(spapr); | |
2302 | uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; | |
e8f986fc | 2303 | uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; |
224245bf DG |
2304 | int i; |
2305 | ||
2306 | for (i = 0; i < nr_lmbs; i++) { | |
224245bf DG |
2307 | uint64_t addr; |
2308 | ||
b0c14ec4 | 2309 | addr = i * lmb_size + machine->device_memory->base; |
6caf3ac6 DG |
2310 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, |
2311 | addr / lmb_size); | |
224245bf DG |
2312 | } |
2313 | } | |
2314 | ||
2315 | /* | |
2316 | * If RAM size, maxmem size and individual node mem sizes aren't aligned | |
2317 | * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest | |
2318 | * since we can't support such unaligned sizes with DRCONF_MEMORY. | |
2319 | */ | |
7c150d6f | 2320 | static void spapr_validate_node_memory(MachineState *machine, Error **errp) |
224245bf DG |
2321 | { |
2322 | int i; | |
2323 | ||
7c150d6f DG |
2324 | if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { |
2325 | error_setg(errp, "Memory size 0x" RAM_ADDR_FMT | |
ab3dd749 | 2326 | " is not aligned to %" PRIu64 " MiB", |
7c150d6f | 2327 | machine->ram_size, |
d23b6caa | 2328 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f DG |
2329 | return; |
2330 | } | |
2331 | ||
2332 | if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { | |
2333 | error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT | |
ab3dd749 | 2334 | " is not aligned to %" PRIu64 " MiB", |
7c150d6f | 2335 | machine->ram_size, |
d23b6caa | 2336 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f | 2337 | return; |
224245bf DG |
2338 | } |
2339 | ||
2340 | for (i = 0; i < nb_numa_nodes; i++) { | |
2341 | if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { | |
7c150d6f DG |
2342 | error_setg(errp, |
2343 | "Node %d memory size 0x%" PRIx64 | |
ab3dd749 | 2344 | " is not aligned to %" PRIu64 " MiB", |
7c150d6f | 2345 | i, numa_info[i].node_mem, |
d23b6caa | 2346 | SPAPR_MEMORY_BLOCK_SIZE / MiB); |
7c150d6f | 2347 | return; |
224245bf DG |
2348 | } |
2349 | } | |
2350 | } | |
2351 | ||
535455fd IM |
2352 | /* find cpu slot in machine->possible_cpus by core_id */ |
2353 | static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) | |
2354 | { | |
2355 | int index = id / smp_threads; | |
2356 | ||
2357 | if (index >= ms->possible_cpus->len) { | |
2358 | return NULL; | |
2359 | } | |
2360 | if (idx) { | |
2361 | *idx = index; | |
2362 | } | |
2363 | return &ms->possible_cpus->cpus[index]; | |
2364 | } | |
2365 | ||
fa98fbfc SB |
2366 | static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) |
2367 | { | |
2368 | Error *local_err = NULL; | |
2369 | bool vsmt_user = !!spapr->vsmt; | |
2370 | int kvm_smt = kvmppc_smt_threads(); | |
2371 | int ret; | |
2372 | ||
2373 | if (!kvm_enabled() && (smp_threads > 1)) { | |
2374 | error_setg(&local_err, "TCG cannot support more than 1 thread/core " | |
2375 | "on a pseries machine"); | |
2376 | goto out; | |
2377 | } | |
2378 | if (!is_power_of_2(smp_threads)) { | |
2379 | error_setg(&local_err, "Cannot support %d threads/core on a pseries " | |
2380 | "machine because it must be a power of 2", smp_threads); | |
2381 | goto out; | |
2382 | } | |
2383 | ||
2384 | /* Detemine the VSMT mode to use: */ | |
2385 | if (vsmt_user) { | |
2386 | if (spapr->vsmt < smp_threads) { | |
2387 | error_setg(&local_err, "Cannot support VSMT mode %d" | |
2388 | " because it must be >= threads/core (%d)", | |
2389 | spapr->vsmt, smp_threads); | |
2390 | goto out; | |
2391 | } | |
2392 | /* In this case, spapr->vsmt has been set by the command line */ | |
2393 | } else { | |
8904e5a7 DG |
2394 | /* |
2395 | * Default VSMT value is tricky, because we need it to be as | |
2396 | * consistent as possible (for migration), but this requires | |
2397 | * changing it for at least some existing cases. We pick 8 as | |
2398 | * the value that we'd get with KVM on POWER8, the | |
2399 | * overwhelmingly common case in production systems. | |
2400 | */ | |
4ad64cbd | 2401 | spapr->vsmt = MAX(8, smp_threads); |
fa98fbfc SB |
2402 | } |
2403 | ||
2404 | /* KVM: If necessary, set the SMT mode: */ | |
2405 | if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { | |
2406 | ret = kvmppc_set_smt_threads(spapr->vsmt); | |
2407 | if (ret) { | |
1f20f2e0 | 2408 | /* Looks like KVM isn't able to change VSMT mode */ |
fa98fbfc SB |
2409 | error_setg(&local_err, |
2410 | "Failed to set KVM's VSMT mode to %d (errno %d)", | |
2411 | spapr->vsmt, ret); | |
1f20f2e0 DG |
2412 | /* We can live with that if the default one is big enough |
2413 | * for the number of threads, and a submultiple of the one | |
2414 | * we want. In this case we'll waste some vcpu ids, but | |
2415 | * behaviour will be correct */ | |
2416 | if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { | |
2417 | warn_report_err(local_err); | |
2418 | local_err = NULL; | |
2419 | goto out; | |
2420 | } else { | |
2421 | if (!vsmt_user) { | |
2422 | error_append_hint(&local_err, | |
2423 | "On PPC, a VM with %d threads/core" | |
2424 | " on a host with %d threads/core" | |
2425 | " requires the use of VSMT mode %d.\n", | |
2426 | smp_threads, kvm_smt, spapr->vsmt); | |
2427 | } | |
2428 | kvmppc_hint_smt_possible(&local_err); | |
2429 | goto out; | |
fa98fbfc | 2430 | } |
fa98fbfc SB |
2431 | } |
2432 | } | |
2433 | /* else TCG: nothing to do currently */ | |
2434 | out: | |
2435 | error_propagate(errp, local_err); | |
2436 | } | |
2437 | ||
1a5008fc GK |
2438 | static void spapr_init_cpus(sPAPRMachineState *spapr) |
2439 | { | |
2440 | MachineState *machine = MACHINE(spapr); | |
2441 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
2442 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); | |
2443 | const char *type = spapr_get_cpu_core_type(machine->cpu_type); | |
2444 | const CPUArchIdList *possible_cpus; | |
2445 | int boot_cores_nr = smp_cpus / smp_threads; | |
2446 | int i; | |
2447 | ||
2448 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
2449 | if (mc->has_hotpluggable_cpus) { | |
2450 | if (smp_cpus % smp_threads) { | |
2451 | error_report("smp_cpus (%u) must be multiple of threads (%u)", | |
2452 | smp_cpus, smp_threads); | |
2453 | exit(1); | |
2454 | } | |
2455 | if (max_cpus % smp_threads) { | |
2456 | error_report("max_cpus (%u) must be multiple of threads (%u)", | |
2457 | max_cpus, smp_threads); | |
2458 | exit(1); | |
2459 | } | |
2460 | } else { | |
2461 | if (max_cpus != smp_cpus) { | |
2462 | error_report("This machine version does not support CPU hotplug"); | |
2463 | exit(1); | |
2464 | } | |
2465 | boot_cores_nr = possible_cpus->len; | |
2466 | } | |
2467 | ||
1a5008fc GK |
2468 | if (smc->pre_2_10_has_unused_icps) { |
2469 | int i; | |
2470 | ||
1a518e76 | 2471 | for (i = 0; i < spapr_max_server_number(spapr); i++) { |
1a5008fc GK |
2472 | /* Dummy entries get deregistered when real ICPState objects |
2473 | * are registered during CPU core hotplug. | |
2474 | */ | |
2475 | pre_2_10_vmstate_register_dummy_icp(i); | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | for (i = 0; i < possible_cpus->len; i++) { | |
2480 | int core_id = i * smp_threads; | |
2481 | ||
2482 | if (mc->has_hotpluggable_cpus) { | |
2483 | spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, | |
2484 | spapr_vcpu_id(spapr, core_id)); | |
2485 | } | |
2486 | ||
2487 | if (i < boot_cores_nr) { | |
2488 | Object *core = object_new(type); | |
2489 | int nr_threads = smp_threads; | |
2490 | ||
2491 | /* Handle the partially filled core for older machine types */ | |
2492 | if ((i + 1) * smp_threads >= smp_cpus) { | |
2493 | nr_threads = smp_cpus - i * smp_threads; | |
2494 | } | |
2495 | ||
2496 | object_property_set_int(core, nr_threads, "nr-threads", | |
2497 | &error_fatal); | |
2498 | object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, | |
2499 | &error_fatal); | |
2500 | object_property_set_bool(core, true, "realized", &error_fatal); | |
ecda255e SB |
2501 | |
2502 | object_unref(core); | |
1a5008fc GK |
2503 | } |
2504 | } | |
2505 | } | |
2506 | ||
9fdf0c29 | 2507 | /* pSeries LPAR / sPAPR hardware init */ |
bcb5ce08 | 2508 | static void spapr_machine_init(MachineState *machine) |
9fdf0c29 | 2509 | { |
28e02042 | 2510 | sPAPRMachineState *spapr = SPAPR_MACHINE(machine); |
224245bf | 2511 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); |
3ef96221 | 2512 | const char *kernel_filename = machine->kernel_filename; |
3ef96221 | 2513 | const char *initrd_filename = machine->initrd_filename; |
8c9f64df | 2514 | PCIHostState *phb; |
9fdf0c29 | 2515 | int i; |
890c2b77 AK |
2516 | MemoryRegion *sysmem = get_system_memory(); |
2517 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
c86c1aff | 2518 | hwaddr node0_size = spapr_node0_size(machine); |
b7d1f77a | 2519 | long load_limit, fw_size; |
39ac8455 | 2520 | char *filename; |
30f4b05b | 2521 | Error *resize_hpt_err = NULL; |
9fdf0c29 | 2522 | |
226419d6 | 2523 | msi_nonbroken = true; |
0ee2c058 | 2524 | |
d43b45e2 | 2525 | QLIST_INIT(&spapr->phbs); |
0cffce56 | 2526 | QTAILQ_INIT(&spapr->pending_dimm_unplugs); |
d43b45e2 | 2527 | |
9f6edd06 DG |
2528 | /* Determine capabilities to run with */ |
2529 | spapr_caps_init(spapr); | |
2530 | ||
30f4b05b DG |
2531 | kvmppc_check_papr_resize_hpt(&resize_hpt_err); |
2532 | if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { | |
2533 | /* | |
2534 | * If the user explicitly requested a mode we should either | |
2535 | * supply it, or fail completely (which we do below). But if | |
2536 | * it's not set explicitly, we reset our mode to something | |
2537 | * that works | |
2538 | */ | |
2539 | if (resize_hpt_err) { | |
2540 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
2541 | error_free(resize_hpt_err); | |
2542 | resize_hpt_err = NULL; | |
2543 | } else { | |
2544 | spapr->resize_hpt = smc->resize_hpt_default; | |
2545 | } | |
2546 | } | |
2547 | ||
2548 | assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); | |
2549 | ||
2550 | if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { | |
2551 | /* | |
2552 | * User requested HPT resize, but this host can't supply it. Bail out | |
2553 | */ | |
2554 | error_report_err(resize_hpt_err); | |
2555 | exit(1); | |
2556 | } | |
2557 | ||
090052aa | 2558 | spapr->rma_size = node0_size; |
354ac20a | 2559 | |
090052aa DG |
2560 | /* With KVM, we don't actually know whether KVM supports an |
2561 | * unbounded RMA (PR KVM) or is limited by the hash table size | |
2562 | * (HV KVM using VRMA), so we always assume the latter | |
2563 | * | |
2564 | * In that case, we also limit the initial allocations for RTAS | |
2565 | * etc... to 256M since we have no way to know what the VRMA size | |
2566 | * is going to be as it depends on the size of the hash table | |
2567 | * which isn't determined yet. | |
2568 | */ | |
2569 | if (kvm_enabled()) { | |
2570 | spapr->vrma_adjust = 1; | |
2571 | spapr->rma_size = MIN(spapr->rma_size, 0x10000000); | |
354ac20a | 2572 | } |
7f763a5d | 2573 | |
090052aa DG |
2574 | /* Actually we don't support unbounded RMA anymore since we added |
2575 | * proper emulation of HV mode. The max we can get is 16G which | |
2576 | * also happens to be what we configure for PAPR mode so make sure | |
2577 | * we don't do anything bigger than that | |
2578 | */ | |
2579 | spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); | |
354ac20a | 2580 | |
c4177479 | 2581 | if (spapr->rma_size > node0_size) { |
d54e4d76 DG |
2582 | error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", |
2583 | spapr->rma_size); | |
c4177479 AK |
2584 | exit(1); |
2585 | } | |
2586 | ||
b7d1f77a BH |
2587 | /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ |
2588 | load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; | |
9fdf0c29 | 2589 | |
482969d6 CLG |
2590 | /* |
2591 | * VSMT must be set in order to be able to compute VCPU ids, ie to | |
1a518e76 | 2592 | * call spapr_max_server_number() or spapr_vcpu_id(). |
482969d6 CLG |
2593 | */ |
2594 | spapr_set_vsmt_mode(spapr, &error_fatal); | |
2595 | ||
7b565160 | 2596 | /* Set up Interrupt Controller before we create the VCPUs */ |
fab397d8 | 2597 | spapr_irq_init(spapr, &error_fatal); |
7b565160 | 2598 | |
dc1b5eee GK |
2599 | /* Set up containers for ibm,client-architecture-support negotiated options |
2600 | */ | |
facdb8b6 MR |
2601 | spapr->ov5 = spapr_ovec_new(); |
2602 | spapr->ov5_cas = spapr_ovec_new(); | |
2603 | ||
224245bf | 2604 | if (smc->dr_lmb_enabled) { |
facdb8b6 | 2605 | spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); |
7c150d6f | 2606 | spapr_validate_node_memory(machine, &error_fatal); |
224245bf DG |
2607 | } |
2608 | ||
417ece33 MR |
2609 | spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); |
2610 | ||
ffbb1705 MR |
2611 | /* advertise support for dedicated HP event source to guests */ |
2612 | if (spapr->use_hotplug_event_source) { | |
2613 | spapr_ovec_set(spapr->ov5, OV5_HP_EVT); | |
2614 | } | |
2615 | ||
2772cf6b DG |
2616 | /* advertise support for HPT resizing */ |
2617 | if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { | |
2618 | spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); | |
2619 | } | |
2620 | ||
a324d6f1 BR |
2621 | /* advertise support for ibm,dyamic-memory-v2 */ |
2622 | spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); | |
2623 | ||
9fdf0c29 | 2624 | /* init CPUs */ |
0c86d0fd | 2625 | spapr_init_cpus(spapr); |
9fdf0c29 | 2626 | |
0550b120 | 2627 | if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && |
ad99d04c DG |
2628 | ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, |
2629 | spapr->max_compat_pvr)) { | |
0550b120 GK |
2630 | /* KVM and TCG always allow GTSE with radix... */ |
2631 | spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); | |
2632 | } | |
2633 | /* ... but not with hash (currently). */ | |
2634 | ||
026bfd89 DG |
2635 | if (kvm_enabled()) { |
2636 | /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ | |
2637 | kvmppc_enable_logical_ci_hcalls(); | |
ef9971dd | 2638 | kvmppc_enable_set_mode_hcall(); |
5145ad4f NW |
2639 | |
2640 | /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ | |
2641 | kvmppc_enable_clear_ref_mod_hcalls(); | |
026bfd89 DG |
2642 | } |
2643 | ||
9fdf0c29 | 2644 | /* allocate RAM */ |
f92f5da1 | 2645 | memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", |
fb164994 | 2646 | machine->ram_size); |
f92f5da1 | 2647 | memory_region_add_subregion(sysmem, 0, ram); |
9fdf0c29 | 2648 | |
b0c14ec4 DH |
2649 | /* always allocate the device memory information */ |
2650 | machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); | |
2651 | ||
4a1c9cf0 BR |
2652 | /* initialize hotplug memory address space */ |
2653 | if (machine->ram_size < machine->maxram_size) { | |
0c9269a5 | 2654 | ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; |
71c9a3dd BR |
2655 | /* |
2656 | * Limit the number of hotpluggable memory slots to half the number | |
2657 | * slots that KVM supports, leaving the other half for PCI and other | |
2658 | * devices. However ensure that number of slots doesn't drop below 32. | |
2659 | */ | |
2660 | int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : | |
2661 | SPAPR_MAX_RAM_SLOTS; | |
4a1c9cf0 | 2662 | |
71c9a3dd BR |
2663 | if (max_memslots < SPAPR_MAX_RAM_SLOTS) { |
2664 | max_memslots = SPAPR_MAX_RAM_SLOTS; | |
2665 | } | |
2666 | if (machine->ram_slots > max_memslots) { | |
d54e4d76 DG |
2667 | error_report("Specified number of memory slots %" |
2668 | PRIu64" exceeds max supported %d", | |
71c9a3dd | 2669 | machine->ram_slots, max_memslots); |
d54e4d76 | 2670 | exit(1); |
4a1c9cf0 BR |
2671 | } |
2672 | ||
b0c14ec4 | 2673 | machine->device_memory->base = ROUND_UP(machine->ram_size, |
0c9269a5 | 2674 | SPAPR_DEVICE_MEM_ALIGN); |
b0c14ec4 | 2675 | memory_region_init(&machine->device_memory->mr, OBJECT(spapr), |
0c9269a5 | 2676 | "device-memory", device_mem_size); |
b0c14ec4 DH |
2677 | memory_region_add_subregion(sysmem, machine->device_memory->base, |
2678 | &machine->device_memory->mr); | |
4a1c9cf0 BR |
2679 | } |
2680 | ||
224245bf DG |
2681 | if (smc->dr_lmb_enabled) { |
2682 | spapr_create_lmb_dr_connectors(spapr); | |
2683 | } | |
2684 | ||
39ac8455 | 2685 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
4c56440d | 2686 | if (!filename) { |
730fce59 | 2687 | error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); |
4c56440d SW |
2688 | exit(1); |
2689 | } | |
b7d1f77a | 2690 | spapr->rtas_size = get_image_size(filename); |
8afc22a2 ZJ |
2691 | if (spapr->rtas_size < 0) { |
2692 | error_report("Could not get size of LPAR rtas '%s'", filename); | |
2693 | exit(1); | |
2694 | } | |
b7d1f77a BH |
2695 | spapr->rtas_blob = g_malloc(spapr->rtas_size); |
2696 | if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { | |
730fce59 | 2697 | error_report("Could not load LPAR rtas '%s'", filename); |
39ac8455 DG |
2698 | exit(1); |
2699 | } | |
4d8d5467 | 2700 | if (spapr->rtas_size > RTAS_MAX_SIZE) { |
730fce59 TH |
2701 | error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", |
2702 | (size_t)spapr->rtas_size, RTAS_MAX_SIZE); | |
4d8d5467 BH |
2703 | exit(1); |
2704 | } | |
7267c094 | 2705 | g_free(filename); |
39ac8455 | 2706 | |
ffbb1705 | 2707 | /* Set up RTAS event infrastructure */ |
74d042e5 DG |
2708 | spapr_events_init(spapr); |
2709 | ||
12f42174 | 2710 | /* Set up the RTC RTAS interfaces */ |
28df36a1 | 2711 | spapr_rtc_create(spapr); |
12f42174 | 2712 | |
b5cec4c5 | 2713 | /* Set up VIO bus */ |
4040ab72 DG |
2714 | spapr->vio_bus = spapr_vio_bus_init(); |
2715 | ||
b8846a4d | 2716 | for (i = 0; i < serial_max_hds(); i++) { |
9bca0edb PM |
2717 | if (serial_hd(i)) { |
2718 | spapr_vty_create(spapr->vio_bus, serial_hd(i)); | |
4040ab72 DG |
2719 | } |
2720 | } | |
9fdf0c29 | 2721 | |
639e8102 DG |
2722 | /* We always have at least the nvram device on VIO */ |
2723 | spapr_create_nvram(spapr); | |
2724 | ||
3384f95c | 2725 | /* Set up PCI */ |
fa28f71b AK |
2726 | spapr_pci_rtas_init(); |
2727 | ||
89dfd6e1 | 2728 | phb = spapr_create_phb(spapr, 0); |
3384f95c | 2729 | |
277f9acf | 2730 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
2731 | NICInfo *nd = &nd_table[i]; |
2732 | ||
2733 | if (!nd->model) { | |
3c3a4e7a | 2734 | nd->model = g_strdup("spapr-vlan"); |
8d90ad90 DG |
2735 | } |
2736 | ||
3c3a4e7a TH |
2737 | if (g_str_equal(nd->model, "spapr-vlan") || |
2738 | g_str_equal(nd->model, "ibmveth")) { | |
d601fac4 | 2739 | spapr_vlan_create(spapr->vio_bus, nd); |
8d90ad90 | 2740 | } else { |
29b358f9 | 2741 | pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); |
8d90ad90 DG |
2742 | } |
2743 | } | |
2744 | ||
6e270446 | 2745 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
d601fac4 | 2746 | spapr_vscsi_create(spapr->vio_bus); |
6e270446 BH |
2747 | } |
2748 | ||
f28359d8 | 2749 | /* Graphics */ |
14c6a894 | 2750 | if (spapr_vga_init(phb->bus, &error_fatal)) { |
3fc5acde | 2751 | spapr->has_graphics = true; |
c6e76503 | 2752 | machine->usb |= defaults_enabled() && !machine->usb_disabled; |
f28359d8 LZ |
2753 | } |
2754 | ||
4ee9ced9 | 2755 | if (machine->usb) { |
57040d45 TH |
2756 | if (smc->use_ohci_by_default) { |
2757 | pci_create_simple(phb->bus, -1, "pci-ohci"); | |
2758 | } else { | |
2759 | pci_create_simple(phb->bus, -1, "nec-usb-xhci"); | |
2760 | } | |
c86580b8 | 2761 | |
35139a59 | 2762 | if (spapr->has_graphics) { |
c86580b8 MA |
2763 | USBBus *usb_bus = usb_bus_find(-1); |
2764 | ||
2765 | usb_create_simple(usb_bus, "usb-kbd"); | |
2766 | usb_create_simple(usb_bus, "usb-mouse"); | |
35139a59 DG |
2767 | } |
2768 | } | |
2769 | ||
ab3dd749 | 2770 | if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) { |
d54e4d76 DG |
2771 | error_report( |
2772 | "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", | |
2773 | MIN_RMA_SLOF); | |
4d8d5467 BH |
2774 | exit(1); |
2775 | } | |
2776 | ||
9fdf0c29 DG |
2777 | if (kernel_filename) { |
2778 | uint64_t lowaddr = 0; | |
2779 | ||
a19f7fb0 DG |
2780 | spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, |
2781 | NULL, NULL, &lowaddr, NULL, 1, | |
2782 | PPC_ELF_MACHINE, 0, 0); | |
2783 | if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { | |
2784 | spapr->kernel_size = load_elf(kernel_filename, | |
2785 | translate_kernel_address, NULL, NULL, | |
2786 | &lowaddr, NULL, 0, PPC_ELF_MACHINE, | |
2787 | 0, 0); | |
2788 | spapr->kernel_le = spapr->kernel_size > 0; | |
16457e7f | 2789 | } |
a19f7fb0 DG |
2790 | if (spapr->kernel_size < 0) { |
2791 | error_report("error loading %s: %s", kernel_filename, | |
2792 | load_elf_strerror(spapr->kernel_size)); | |
9fdf0c29 DG |
2793 | exit(1); |
2794 | } | |
2795 | ||
2796 | /* load initrd */ | |
2797 | if (initrd_filename) { | |
4d8d5467 BH |
2798 | /* Try to locate the initrd in the gap between the kernel |
2799 | * and the firmware. Add a bit of space just in case | |
2800 | */ | |
a19f7fb0 DG |
2801 | spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size |
2802 | + 0x1ffff) & ~0xffff; | |
2803 | spapr->initrd_size = load_image_targphys(initrd_filename, | |
2804 | spapr->initrd_base, | |
2805 | load_limit | |
2806 | - spapr->initrd_base); | |
2807 | if (spapr->initrd_size < 0) { | |
d54e4d76 DG |
2808 | error_report("could not load initial ram disk '%s'", |
2809 | initrd_filename); | |
9fdf0c29 DG |
2810 | exit(1); |
2811 | } | |
9fdf0c29 | 2812 | } |
4d8d5467 | 2813 | } |
a3467baa | 2814 | |
8e7ea787 AF |
2815 | if (bios_name == NULL) { |
2816 | bios_name = FW_FILE_NAME; | |
2817 | } | |
2818 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4c56440d | 2819 | if (!filename) { |
68fea5a0 | 2820 | error_report("Could not find LPAR firmware '%s'", bios_name); |
4c56440d SW |
2821 | exit(1); |
2822 | } | |
4d8d5467 | 2823 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); |
68fea5a0 TH |
2824 | if (fw_size <= 0) { |
2825 | error_report("Could not load LPAR firmware '%s'", filename); | |
4d8d5467 BH |
2826 | exit(1); |
2827 | } | |
2828 | g_free(filename); | |
4d8d5467 | 2829 | |
28e02042 DG |
2830 | /* FIXME: Should register things through the MachineState's qdev |
2831 | * interface, this is a legacy from the sPAPREnvironment structure | |
2832 | * which predated MachineState but had a similar function */ | |
4be21d56 DG |
2833 | vmstate_register(NULL, 0, &vmstate_spapr, spapr); |
2834 | register_savevm_live(NULL, "spapr/htab", -1, 1, | |
2835 | &savevm_htab_handlers, spapr); | |
2836 | ||
5b2128d2 | 2837 | qemu_register_boot_set(spapr_boot_set, spapr); |
42043e4f | 2838 | |
42043e4f | 2839 | if (kvm_enabled()) { |
3dc410ae | 2840 | /* to stop and start vmclock */ |
42043e4f LV |
2841 | qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, |
2842 | &spapr->tb); | |
3dc410ae AK |
2843 | |
2844 | kvmppc_spapr_enable_inkernel_multitce(); | |
42043e4f | 2845 | } |
9fdf0c29 DG |
2846 | } |
2847 | ||
135a129a AK |
2848 | static int spapr_kvm_type(const char *vm_type) |
2849 | { | |
2850 | if (!vm_type) { | |
2851 | return 0; | |
2852 | } | |
2853 | ||
2854 | if (!strcmp(vm_type, "HV")) { | |
2855 | return 1; | |
2856 | } | |
2857 | ||
2858 | if (!strcmp(vm_type, "PR")) { | |
2859 | return 2; | |
2860 | } | |
2861 | ||
2862 | error_report("Unknown kvm-type specified '%s'", vm_type); | |
2863 | exit(1); | |
2864 | } | |
2865 | ||
71461b0f | 2866 | /* |
627b84f4 | 2867 | * Implementation of an interface to adjust firmware path |
71461b0f AK |
2868 | * for the bootindex property handling. |
2869 | */ | |
2870 | static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, | |
2871 | DeviceState *dev) | |
2872 | { | |
2873 | #define CAST(type, obj, name) \ | |
2874 | ((type *)object_dynamic_cast(OBJECT(obj), (name))) | |
2875 | SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); | |
2876 | sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); | |
c4e13492 | 2877 | VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); |
71461b0f AK |
2878 | |
2879 | if (d) { | |
2880 | void *spapr = CAST(void, bus->parent, "spapr-vscsi"); | |
2881 | VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); | |
2882 | USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); | |
2883 | ||
2884 | if (spapr) { | |
2885 | /* | |
2886 | * Replace "channel@0/disk@0,0" with "disk@8000000000000000": | |
2887 | * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun | |
2888 | * in the top 16 bits of the 64-bit LUN | |
2889 | */ | |
2890 | unsigned id = 0x8000 | (d->id << 8) | d->lun; | |
2891 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2892 | (uint64_t)id << 48); | |
2893 | } else if (virtio) { | |
2894 | /* | |
2895 | * We use SRP luns of the form 01000000 | (target << 8) | lun | |
2896 | * in the top 32 bits of the 64-bit LUN | |
2897 | * Note: the quote above is from SLOF and it is wrong, | |
2898 | * the actual binding is: | |
2899 | * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) | |
2900 | */ | |
2901 | unsigned id = 0x1000000 | (d->id << 16) | d->lun; | |
bac658d1 TH |
2902 | if (d->lun >= 256) { |
2903 | /* Use the LUN "flat space addressing method" */ | |
2904 | id |= 0x4000; | |
2905 | } | |
71461b0f AK |
2906 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), |
2907 | (uint64_t)id << 32); | |
2908 | } else if (usb) { | |
2909 | /* | |
2910 | * We use SRP luns of the form 01000000 | (usb-port << 16) | lun | |
2911 | * in the top 32 bits of the 64-bit LUN | |
2912 | */ | |
2913 | unsigned usb_port = atoi(usb->port->path); | |
2914 | unsigned id = 0x1000000 | (usb_port << 16) | d->lun; | |
2915 | return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), | |
2916 | (uint64_t)id << 32); | |
2917 | } | |
2918 | } | |
2919 | ||
b99260eb TH |
2920 | /* |
2921 | * SLOF probes the USB devices, and if it recognizes that the device is a | |
2922 | * storage device, it changes its name to "storage" instead of "usb-host", | |
2923 | * and additionally adds a child node for the SCSI LUN, so the correct | |
2924 | * boot path in SLOF is something like .../storage@1/disk@xxx" instead. | |
2925 | */ | |
2926 | if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { | |
2927 | USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); | |
2928 | if (usb_host_dev_is_scsi_storage(usbdev)) { | |
2929 | return g_strdup_printf("storage@%s/disk", usbdev->port->path); | |
2930 | } | |
2931 | } | |
2932 | ||
71461b0f AK |
2933 | if (phb) { |
2934 | /* Replace "pci" with "pci@800000020000000" */ | |
2935 | return g_strdup_printf("pci@%"PRIX64, phb->buid); | |
2936 | } | |
2937 | ||
c4e13492 FF |
2938 | if (vsc) { |
2939 | /* Same logic as virtio above */ | |
2940 | unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; | |
2941 | return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); | |
2942 | } | |
2943 | ||
4871dd4c TH |
2944 | if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { |
2945 | /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ | |
2946 | PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); | |
2947 | return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); | |
2948 | } | |
2949 | ||
71461b0f AK |
2950 | return NULL; |
2951 | } | |
2952 | ||
23825581 EH |
2953 | static char *spapr_get_kvm_type(Object *obj, Error **errp) |
2954 | { | |
28e02042 | 2955 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2956 | |
28e02042 | 2957 | return g_strdup(spapr->kvm_type); |
23825581 EH |
2958 | } |
2959 | ||
2960 | static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) | |
2961 | { | |
28e02042 | 2962 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
23825581 | 2963 | |
28e02042 DG |
2964 | g_free(spapr->kvm_type); |
2965 | spapr->kvm_type = g_strdup(value); | |
23825581 EH |
2966 | } |
2967 | ||
f6229214 MR |
2968 | static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) |
2969 | { | |
2970 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2971 | ||
2972 | return spapr->use_hotplug_event_source; | |
2973 | } | |
2974 | ||
2975 | static void spapr_set_modern_hotplug_events(Object *obj, bool value, | |
2976 | Error **errp) | |
2977 | { | |
2978 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2979 | ||
2980 | spapr->use_hotplug_event_source = value; | |
2981 | } | |
2982 | ||
fcad0d21 AK |
2983 | static bool spapr_get_msix_emulation(Object *obj, Error **errp) |
2984 | { | |
2985 | return true; | |
2986 | } | |
2987 | ||
30f4b05b DG |
2988 | static char *spapr_get_resize_hpt(Object *obj, Error **errp) |
2989 | { | |
2990 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
2991 | ||
2992 | switch (spapr->resize_hpt) { | |
2993 | case SPAPR_RESIZE_HPT_DEFAULT: | |
2994 | return g_strdup("default"); | |
2995 | case SPAPR_RESIZE_HPT_DISABLED: | |
2996 | return g_strdup("disabled"); | |
2997 | case SPAPR_RESIZE_HPT_ENABLED: | |
2998 | return g_strdup("enabled"); | |
2999 | case SPAPR_RESIZE_HPT_REQUIRED: | |
3000 | return g_strdup("required"); | |
3001 | } | |
3002 | g_assert_not_reached(); | |
3003 | } | |
3004 | ||
3005 | static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) | |
3006 | { | |
3007 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
3008 | ||
3009 | if (strcmp(value, "default") == 0) { | |
3010 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; | |
3011 | } else if (strcmp(value, "disabled") == 0) { | |
3012 | spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; | |
3013 | } else if (strcmp(value, "enabled") == 0) { | |
3014 | spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; | |
3015 | } else if (strcmp(value, "required") == 0) { | |
3016 | spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; | |
3017 | } else { | |
3018 | error_setg(errp, "Bad value for \"resize-hpt\" property"); | |
3019 | } | |
3020 | } | |
3021 | ||
fa98fbfc SB |
3022 | static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, |
3023 | void *opaque, Error **errp) | |
3024 | { | |
3025 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
3026 | } | |
3027 | ||
3028 | static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, | |
3029 | void *opaque, Error **errp) | |
3030 | { | |
3031 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
3032 | } | |
3033 | ||
bcb5ce08 | 3034 | static void spapr_instance_init(Object *obj) |
23825581 | 3035 | { |
715c5407 DG |
3036 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); |
3037 | ||
3038 | spapr->htab_fd = -1; | |
f6229214 | 3039 | spapr->use_hotplug_event_source = true; |
23825581 EH |
3040 | object_property_add_str(obj, "kvm-type", |
3041 | spapr_get_kvm_type, spapr_set_kvm_type, NULL); | |
49d2e648 MA |
3042 | object_property_set_description(obj, "kvm-type", |
3043 | "Specifies the KVM virtualization mode (HV, PR)", | |
3044 | NULL); | |
f6229214 MR |
3045 | object_property_add_bool(obj, "modern-hotplug-events", |
3046 | spapr_get_modern_hotplug_events, | |
3047 | spapr_set_modern_hotplug_events, | |
3048 | NULL); | |
3049 | object_property_set_description(obj, "modern-hotplug-events", | |
3050 | "Use dedicated hotplug event mechanism in" | |
3051 | " place of standard EPOW events when possible" | |
3052 | " (required for memory hot-unplug support)", | |
3053 | NULL); | |
7843c0d6 DG |
3054 | ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, |
3055 | "Maximum permitted CPU compatibility mode", | |
3056 | &error_fatal); | |
30f4b05b DG |
3057 | |
3058 | object_property_add_str(obj, "resize-hpt", | |
3059 | spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); | |
3060 | object_property_set_description(obj, "resize-hpt", | |
3061 | "Resizing of the Hash Page Table (enabled, disabled, required)", | |
3062 | NULL); | |
fa98fbfc SB |
3063 | object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, |
3064 | spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); | |
3065 | object_property_set_description(obj, "vsmt", | |
3066 | "Virtual SMT: KVM behaves as if this were" | |
3067 | " the host's SMT mode", &error_abort); | |
fcad0d21 AK |
3068 | object_property_add_bool(obj, "vfio-no-msix-emulation", |
3069 | spapr_get_msix_emulation, NULL, NULL); | |
23825581 EH |
3070 | } |
3071 | ||
87bbdd9c DG |
3072 | static void spapr_machine_finalizefn(Object *obj) |
3073 | { | |
3074 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
3075 | ||
3076 | g_free(spapr->kvm_type); | |
3077 | } | |
3078 | ||
1c7ad77e | 3079 | void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) |
34316482 | 3080 | { |
34316482 AK |
3081 | cpu_synchronize_state(cs); |
3082 | ppc_cpu_do_system_reset(cs); | |
3083 | } | |
3084 | ||
3085 | static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) | |
3086 | { | |
3087 | CPUState *cs; | |
3088 | ||
3089 | CPU_FOREACH(cs) { | |
1c7ad77e | 3090 | async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); |
34316482 AK |
3091 | } |
3092 | } | |
3093 | ||
79b78a6b MR |
3094 | static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, |
3095 | uint32_t node, bool dedicated_hp_event_source, | |
3096 | Error **errp) | |
c20d332a BR |
3097 | { |
3098 | sPAPRDRConnector *drc; | |
c20d332a BR |
3099 | uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; |
3100 | int i, fdt_offset, fdt_size; | |
3101 | void *fdt; | |
79b78a6b | 3102 | uint64_t addr = addr_start; |
94fd9cba | 3103 | bool hotplugged = spapr_drc_hotplugged(dev); |
160bb678 | 3104 | Error *local_err = NULL; |
c20d332a | 3105 | |
c20d332a | 3106 | for (i = 0; i < nr_lmbs; i++) { |
fbf55397 DG |
3107 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3108 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
c20d332a BR |
3109 | g_assert(drc); |
3110 | ||
3111 | fdt = create_device_tree(&fdt_size); | |
3112 | fdt_offset = spapr_populate_memory_node(fdt, node, addr, | |
3113 | SPAPR_MEMORY_BLOCK_SIZE); | |
3114 | ||
160bb678 GK |
3115 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
3116 | if (local_err) { | |
3117 | while (addr > addr_start) { | |
3118 | addr -= SPAPR_MEMORY_BLOCK_SIZE; | |
3119 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, | |
3120 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
a8dc47fd | 3121 | spapr_drc_detach(drc); |
160bb678 GK |
3122 | } |
3123 | g_free(fdt); | |
3124 | error_propagate(errp, local_err); | |
3125 | return; | |
3126 | } | |
94fd9cba LV |
3127 | if (!hotplugged) { |
3128 | spapr_drc_reset(drc); | |
3129 | } | |
c20d332a BR |
3130 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3131 | } | |
5dd5238c JD |
3132 | /* send hotplug notification to the |
3133 | * guest only in case of hotplugged memory | |
3134 | */ | |
94fd9cba | 3135 | if (hotplugged) { |
79b78a6b | 3136 | if (dedicated_hp_event_source) { |
fbf55397 DG |
3137 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3138 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
79b78a6b MR |
3139 | spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
3140 | nr_lmbs, | |
0b55aa91 | 3141 | spapr_drc_index(drc)); |
79b78a6b MR |
3142 | } else { |
3143 | spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, | |
3144 | nr_lmbs); | |
3145 | } | |
5dd5238c | 3146 | } |
c20d332a BR |
3147 | } |
3148 | ||
3149 | static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
81985f3b | 3150 | Error **errp) |
c20d332a BR |
3151 | { |
3152 | Error *local_err = NULL; | |
3153 | sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); | |
3154 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
b0e62443 | 3155 | uint64_t size, addr; |
81985f3b | 3156 | uint32_t node; |
04790978 | 3157 | |
946d6154 | 3158 | size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); |
df587133 | 3159 | |
fd3416f5 | 3160 | pc_dimm_plug(dimm, MACHINE(ms), &local_err); |
c20d332a BR |
3161 | if (local_err) { |
3162 | goto out; | |
3163 | } | |
3164 | ||
9ed442b8 MAL |
3165 | addr = object_property_get_uint(OBJECT(dimm), |
3166 | PC_DIMM_ADDR_PROP, &local_err); | |
c20d332a | 3167 | if (local_err) { |
160bb678 | 3168 | goto out_unplug; |
c20d332a BR |
3169 | } |
3170 | ||
81985f3b DH |
3171 | node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, |
3172 | &error_abort); | |
79b78a6b MR |
3173 | spapr_add_lmbs(dev, addr, size, node, |
3174 | spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), | |
160bb678 GK |
3175 | &local_err); |
3176 | if (local_err) { | |
3177 | goto out_unplug; | |
3178 | } | |
3179 | ||
3180 | return; | |
c20d332a | 3181 | |
160bb678 | 3182 | out_unplug: |
fd3416f5 | 3183 | pc_dimm_unplug(dimm, MACHINE(ms)); |
c20d332a BR |
3184 | out: |
3185 | error_propagate(errp, local_err); | |
3186 | } | |
3187 | ||
c871bc70 LV |
3188 | static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
3189 | Error **errp) | |
3190 | { | |
4e8a01bd | 3191 | const sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); |
123eec65 | 3192 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
c871bc70 | 3193 | PCDIMMDevice *dimm = PC_DIMM(dev); |
8f1ffe5b | 3194 | Error *local_err = NULL; |
04790978 | 3195 | uint64_t size; |
123eec65 DG |
3196 | Object *memdev; |
3197 | hwaddr pagesize; | |
c871bc70 | 3198 | |
4e8a01bd DH |
3199 | if (!smc->dr_lmb_enabled) { |
3200 | error_setg(errp, "Memory hotplug not supported for this machine"); | |
3201 | return; | |
3202 | } | |
3203 | ||
946d6154 DH |
3204 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); |
3205 | if (local_err) { | |
3206 | error_propagate(errp, local_err); | |
04790978 TH |
3207 | return; |
3208 | } | |
04790978 | 3209 | |
c871bc70 LV |
3210 | if (size % SPAPR_MEMORY_BLOCK_SIZE) { |
3211 | error_setg(errp, "Hotplugged memory size must be a multiple of " | |
ab3dd749 | 3212 | "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); |
c871bc70 LV |
3213 | return; |
3214 | } | |
3215 | ||
123eec65 DG |
3216 | memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, |
3217 | &error_abort); | |
3218 | pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); | |
8f1ffe5b DH |
3219 | spapr_check_pagesize(spapr, pagesize, &local_err); |
3220 | if (local_err) { | |
3221 | error_propagate(errp, local_err); | |
3222 | return; | |
3223 | } | |
3224 | ||
fd3416f5 | 3225 | pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); |
c871bc70 LV |
3226 | } |
3227 | ||
0cffce56 DG |
3228 | struct sPAPRDIMMState { |
3229 | PCDIMMDevice *dimm; | |
cf632463 | 3230 | uint32_t nr_lmbs; |
0cffce56 DG |
3231 | QTAILQ_ENTRY(sPAPRDIMMState) next; |
3232 | }; | |
3233 | ||
3234 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, | |
3235 | PCDIMMDevice *dimm) | |
3236 | { | |
3237 | sPAPRDIMMState *dimm_state = NULL; | |
3238 | ||
3239 | QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { | |
3240 | if (dimm_state->dimm == dimm) { | |
3241 | break; | |
3242 | } | |
3243 | } | |
3244 | return dimm_state; | |
3245 | } | |
3246 | ||
8d5981c4 BR |
3247 | static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, |
3248 | uint32_t nr_lmbs, | |
3249 | PCDIMMDevice *dimm) | |
0cffce56 | 3250 | { |
8d5981c4 BR |
3251 | sPAPRDIMMState *ds = NULL; |
3252 | ||
3253 | /* | |
3254 | * If this request is for a DIMM whose removal had failed earlier | |
3255 | * (due to guest's refusal to remove the LMBs), we would have this | |
3256 | * dimm already in the pending_dimm_unplugs list. In that | |
3257 | * case don't add again. | |
3258 | */ | |
3259 | ds = spapr_pending_dimm_unplugs_find(spapr, dimm); | |
3260 | if (!ds) { | |
3261 | ds = g_malloc0(sizeof(sPAPRDIMMState)); | |
3262 | ds->nr_lmbs = nr_lmbs; | |
3263 | ds->dimm = dimm; | |
3264 | QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); | |
3265 | } | |
3266 | return ds; | |
0cffce56 DG |
3267 | } |
3268 | ||
3269 | static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, | |
3270 | sPAPRDIMMState *dimm_state) | |
3271 | { | |
3272 | QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); | |
3273 | g_free(dimm_state); | |
3274 | } | |
cf632463 | 3275 | |
16ee9980 DHB |
3276 | static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, |
3277 | PCDIMMDevice *dimm) | |
3278 | { | |
3279 | sPAPRDRConnector *drc; | |
946d6154 DH |
3280 | uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), |
3281 | &error_abort); | |
16ee9980 DHB |
3282 | uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3283 | uint32_t avail_lmbs = 0; | |
3284 | uint64_t addr_start, addr; | |
3285 | int i; | |
16ee9980 DHB |
3286 | |
3287 | addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, | |
3288 | &error_abort); | |
3289 | ||
3290 | addr = addr_start; | |
3291 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3292 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3293 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
16ee9980 | 3294 | g_assert(drc); |
454b580a | 3295 | if (drc->dev) { |
16ee9980 DHB |
3296 | avail_lmbs++; |
3297 | } | |
3298 | addr += SPAPR_MEMORY_BLOCK_SIZE; | |
3299 | } | |
3300 | ||
8d5981c4 | 3301 | return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); |
16ee9980 DHB |
3302 | } |
3303 | ||
31834723 DHB |
3304 | /* Callback to be called during DRC release. */ |
3305 | void spapr_lmb_release(DeviceState *dev) | |
cf632463 | 3306 | { |
3ec71474 DH |
3307 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3308 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); | |
0cffce56 | 3309 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); |
cf632463 | 3310 | |
16ee9980 DHB |
3311 | /* This information will get lost if a migration occurs |
3312 | * during the unplug process. In this case recover it. */ | |
3313 | if (ds == NULL) { | |
3314 | ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); | |
8d5981c4 | 3315 | g_assert(ds); |
454b580a DG |
3316 | /* The DRC being examined by the caller at least must be counted */ |
3317 | g_assert(ds->nr_lmbs); | |
3318 | } | |
3319 | ||
3320 | if (--ds->nr_lmbs) { | |
cf632463 BR |
3321 | return; |
3322 | } | |
3323 | ||
cf632463 BR |
3324 | /* |
3325 | * Now that all the LMBs have been removed by the guest, call the | |
3ec71474 | 3326 | * unplug handler chain. This can never fail. |
cf632463 | 3327 | */ |
3ec71474 DH |
3328 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); |
3329 | } | |
3330 | ||
3331 | static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3332 | { | |
3333 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); | |
3334 | sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); | |
3335 | ||
fd3416f5 | 3336 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); |
cf632463 | 3337 | object_unparent(OBJECT(dev)); |
2a129767 | 3338 | spapr_pending_dimm_unplugs_remove(spapr, ds); |
cf632463 BR |
3339 | } |
3340 | ||
3341 | static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, | |
3342 | DeviceState *dev, Error **errp) | |
3343 | { | |
0cffce56 | 3344 | sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); |
cf632463 BR |
3345 | Error *local_err = NULL; |
3346 | PCDIMMDevice *dimm = PC_DIMM(dev); | |
04790978 TH |
3347 | uint32_t nr_lmbs; |
3348 | uint64_t size, addr_start, addr; | |
0cffce56 DG |
3349 | int i; |
3350 | sPAPRDRConnector *drc; | |
04790978 | 3351 | |
946d6154 | 3352 | size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); |
04790978 TH |
3353 | nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; |
3354 | ||
9ed442b8 | 3355 | addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, |
0cffce56 | 3356 | &local_err); |
cf632463 BR |
3357 | if (local_err) { |
3358 | goto out; | |
3359 | } | |
3360 | ||
2a129767 DHB |
3361 | /* |
3362 | * An existing pending dimm state for this DIMM means that there is an | |
3363 | * unplug operation in progress, waiting for the spapr_lmb_release | |
3364 | * callback to complete the job (BQL can't cover that far). In this case, | |
3365 | * bail out to avoid detaching DRCs that were already released. | |
3366 | */ | |
3367 | if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { | |
3368 | error_setg(&local_err, | |
3369 | "Memory unplug already in progress for device %s", | |
3370 | dev->id); | |
3371 | goto out; | |
3372 | } | |
3373 | ||
8d5981c4 | 3374 | spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); |
0cffce56 DG |
3375 | |
3376 | addr = addr_start; | |
3377 | for (i = 0; i < nr_lmbs; i++) { | |
fbf55397 DG |
3378 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3379 | addr / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 DG |
3380 | g_assert(drc); |
3381 | ||
a8dc47fd | 3382 | spapr_drc_detach(drc); |
0cffce56 DG |
3383 | addr += SPAPR_MEMORY_BLOCK_SIZE; |
3384 | } | |
3385 | ||
fbf55397 DG |
3386 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, |
3387 | addr_start / SPAPR_MEMORY_BLOCK_SIZE); | |
0cffce56 | 3388 | spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, |
0b55aa91 | 3389 | nr_lmbs, spapr_drc_index(drc)); |
cf632463 BR |
3390 | out: |
3391 | error_propagate(errp, local_err); | |
3392 | } | |
3393 | ||
04d0ffbd GK |
3394 | static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, |
3395 | sPAPRMachineState *spapr) | |
af81cf32 BR |
3396 | { |
3397 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3398 | DeviceClass *dc = DEVICE_GET_CLASS(cs); | |
14bb4486 | 3399 | int id = spapr_get_vcpu_id(cpu); |
af81cf32 BR |
3400 | void *fdt; |
3401 | int offset, fdt_size; | |
3402 | char *nodename; | |
3403 | ||
3404 | fdt = create_device_tree(&fdt_size); | |
3405 | nodename = g_strdup_printf("%s@%x", dc->fw_name, id); | |
3406 | offset = fdt_add_subnode(fdt, 0, nodename); | |
3407 | ||
3408 | spapr_populate_cpu_dt(cs, fdt, offset, spapr); | |
3409 | g_free(nodename); | |
3410 | ||
3411 | *fdt_offset = offset; | |
3412 | return fdt; | |
3413 | } | |
3414 | ||
765d1bdd DG |
3415 | /* Callback to be called during DRC release. */ |
3416 | void spapr_core_release(DeviceState *dev) | |
ff9006dd | 3417 | { |
a4261be1 DH |
3418 | HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); |
3419 | ||
3420 | /* Call the unplug handler chain. This can never fail. */ | |
3421 | hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); | |
3422 | } | |
3423 | ||
3424 | static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) | |
3425 | { | |
3426 | MachineState *ms = MACHINE(hotplug_dev); | |
46f7afa3 | 3427 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); |
ff9006dd | 3428 | CPUCore *cc = CPU_CORE(dev); |
535455fd | 3429 | CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); |
ff9006dd | 3430 | |
46f7afa3 GK |
3431 | if (smc->pre_2_10_has_unused_icps) { |
3432 | sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); | |
46f7afa3 GK |
3433 | int i; |
3434 | ||
3435 | for (i = 0; i < cc->nr_threads; i++) { | |
94ad93bd | 3436 | CPUState *cs = CPU(sc->threads[i]); |
46f7afa3 GK |
3437 | |
3438 | pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); | |
3439 | } | |
3440 | } | |
3441 | ||
07572c06 | 3442 | assert(core_slot); |
535455fd | 3443 | core_slot->cpu = NULL; |
ff9006dd IM |
3444 | object_unparent(OBJECT(dev)); |
3445 | } | |
3446 | ||
115debf2 IM |
3447 | static |
3448 | void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3449 | Error **errp) | |
ff9006dd | 3450 | { |
72194664 | 3451 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
535455fd IM |
3452 | int index; |
3453 | sPAPRDRConnector *drc; | |
535455fd | 3454 | CPUCore *cc = CPU_CORE(dev); |
ff9006dd | 3455 | |
535455fd IM |
3456 | if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { |
3457 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3458 | cc->core_id); | |
3459 | return; | |
3460 | } | |
ff9006dd IM |
3461 | if (index == 0) { |
3462 | error_setg(errp, "Boot CPU core may not be unplugged"); | |
3463 | return; | |
3464 | } | |
3465 | ||
5d0fb150 GK |
3466 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3467 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd IM |
3468 | g_assert(drc); |
3469 | ||
a8dc47fd | 3470 | spapr_drc_detach(drc); |
ff9006dd IM |
3471 | |
3472 | spapr_hotplug_req_remove_by_index(drc); | |
3473 | } | |
3474 | ||
3475 | static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3476 | Error **errp) | |
3477 | { | |
3478 | sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); | |
3479 | MachineClass *mc = MACHINE_GET_CLASS(spapr); | |
46f7afa3 | 3480 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
ff9006dd IM |
3481 | sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); |
3482 | CPUCore *cc = CPU_CORE(dev); | |
94ad93bd | 3483 | CPUState *cs = CPU(core->threads[0]); |
ff9006dd IM |
3484 | sPAPRDRConnector *drc; |
3485 | Error *local_err = NULL; | |
535455fd IM |
3486 | CPUArchId *core_slot; |
3487 | int index; | |
94fd9cba | 3488 | bool hotplugged = spapr_drc_hotplugged(dev); |
ff9006dd | 3489 | |
535455fd IM |
3490 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3491 | if (!core_slot) { | |
3492 | error_setg(errp, "Unable to find CPU core with core-id: %d", | |
3493 | cc->core_id); | |
3494 | return; | |
3495 | } | |
5d0fb150 GK |
3496 | drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, |
3497 | spapr_vcpu_id(spapr, cc->core_id)); | |
ff9006dd | 3498 | |
c5514d0e | 3499 | g_assert(drc || !mc->has_hotpluggable_cpus); |
ff9006dd | 3500 | |
ff9006dd | 3501 | if (drc) { |
e49c63d5 GK |
3502 | void *fdt; |
3503 | int fdt_offset; | |
3504 | ||
3505 | fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); | |
3506 | ||
5c1da812 | 3507 | spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); |
ff9006dd IM |
3508 | if (local_err) { |
3509 | g_free(fdt); | |
ff9006dd IM |
3510 | error_propagate(errp, local_err); |
3511 | return; | |
3512 | } | |
ff9006dd | 3513 | |
94fd9cba LV |
3514 | if (hotplugged) { |
3515 | /* | |
3516 | * Send hotplug notification interrupt to the guest only | |
3517 | * in case of hotplugged CPUs. | |
3518 | */ | |
3519 | spapr_hotplug_req_add_by_index(drc); | |
3520 | } else { | |
3521 | spapr_drc_reset(drc); | |
3522 | } | |
ff9006dd | 3523 | } |
94fd9cba | 3524 | |
535455fd | 3525 | core_slot->cpu = OBJECT(dev); |
46f7afa3 GK |
3526 | |
3527 | if (smc->pre_2_10_has_unused_icps) { | |
46f7afa3 GK |
3528 | int i; |
3529 | ||
3530 | for (i = 0; i < cc->nr_threads; i++) { | |
bc877283 | 3531 | cs = CPU(core->threads[i]); |
46f7afa3 GK |
3532 | pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); |
3533 | } | |
3534 | } | |
ff9006dd IM |
3535 | } |
3536 | ||
3537 | static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, | |
3538 | Error **errp) | |
3539 | { | |
3540 | MachineState *machine = MACHINE(OBJECT(hotplug_dev)); | |
3541 | MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); | |
ff9006dd IM |
3542 | Error *local_err = NULL; |
3543 | CPUCore *cc = CPU_CORE(dev); | |
2e9c10eb | 3544 | const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); |
ff9006dd | 3545 | const char *type = object_get_typename(OBJECT(dev)); |
535455fd IM |
3546 | CPUArchId *core_slot; |
3547 | int index; | |
ff9006dd | 3548 | |
c5514d0e | 3549 | if (dev->hotplugged && !mc->has_hotpluggable_cpus) { |
ff9006dd IM |
3550 | error_setg(&local_err, "CPU hotplug not supported for this machine"); |
3551 | goto out; | |
3552 | } | |
3553 | ||
3554 | if (strcmp(base_core_type, type)) { | |
3555 | error_setg(&local_err, "CPU core type should be %s", base_core_type); | |
3556 | goto out; | |
3557 | } | |
3558 | ||
3559 | if (cc->core_id % smp_threads) { | |
3560 | error_setg(&local_err, "invalid core id %d", cc->core_id); | |
3561 | goto out; | |
3562 | } | |
3563 | ||
459264ef DG |
3564 | /* |
3565 | * In general we should have homogeneous threads-per-core, but old | |
3566 | * (pre hotplug support) machine types allow the last core to have | |
3567 | * reduced threads as a compatibility hack for when we allowed | |
3568 | * total vcpus not a multiple of threads-per-core. | |
3569 | */ | |
3570 | if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { | |
df8658de | 3571 | error_setg(&local_err, "invalid nr-threads %d, must be %d", |
8149e299 | 3572 | cc->nr_threads, smp_threads); |
df8658de | 3573 | goto out; |
8149e299 DG |
3574 | } |
3575 | ||
535455fd IM |
3576 | core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); |
3577 | if (!core_slot) { | |
ff9006dd IM |
3578 | error_setg(&local_err, "core id %d out of range", cc->core_id); |
3579 | goto out; | |
3580 | } | |
3581 | ||
535455fd | 3582 | if (core_slot->cpu) { |
ff9006dd IM |
3583 | error_setg(&local_err, "core %d already populated", cc->core_id); |
3584 | goto out; | |
3585 | } | |
3586 | ||
a0ceb640 | 3587 | numa_cpu_pre_plug(core_slot, dev, &local_err); |
0b8497f0 | 3588 | |
ff9006dd | 3589 | out: |
ff9006dd IM |
3590 | error_propagate(errp, local_err); |
3591 | } | |
3592 | ||
c20d332a BR |
3593 | static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, |
3594 | DeviceState *dev, Error **errp) | |
3595 | { | |
c20d332a | 3596 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
81985f3b | 3597 | spapr_memory_plug(hotplug_dev, dev, errp); |
af81cf32 BR |
3598 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3599 | spapr_core_plug(hotplug_dev, dev, errp); | |
c20d332a BR |
3600 | } |
3601 | } | |
3602 | ||
88432f44 DH |
3603 | static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, |
3604 | DeviceState *dev, Error **errp) | |
3605 | { | |
3ec71474 DH |
3606 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3607 | spapr_memory_unplug(hotplug_dev, dev); | |
a4261be1 DH |
3608 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
3609 | spapr_core_unplug(hotplug_dev, dev); | |
3ec71474 | 3610 | } |
88432f44 DH |
3611 | } |
3612 | ||
cf632463 BR |
3613 | static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, |
3614 | DeviceState *dev, Error **errp) | |
3615 | { | |
c86c1aff DHB |
3616 | sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); |
3617 | MachineClass *mc = MACHINE_GET_CLASS(sms); | |
cf632463 BR |
3618 | |
3619 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
3620 | if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { | |
3621 | spapr_memory_unplug_request(hotplug_dev, dev, errp); | |
3622 | } else { | |
3623 | /* NOTE: this means there is a window after guest reset, prior to | |
3624 | * CAS negotiation, where unplug requests will fail due to the | |
3625 | * capability not being detected yet. This is a bit different than | |
3626 | * the case with PCI unplug, where the events will be queued and | |
3627 | * eventually handled by the guest after boot | |
3628 | */ | |
3629 | error_setg(errp, "Memory hot unplug not supported for this guest"); | |
3630 | } | |
6f4b5c3e | 3631 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { |
c5514d0e | 3632 | if (!mc->has_hotpluggable_cpus) { |
6f4b5c3e BR |
3633 | error_setg(errp, "CPU hot unplug not supported on this machine"); |
3634 | return; | |
3635 | } | |
115debf2 | 3636 | spapr_core_unplug_request(hotplug_dev, dev, errp); |
c20d332a BR |
3637 | } |
3638 | } | |
3639 | ||
94a94e4c BR |
3640 | static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, |
3641 | DeviceState *dev, Error **errp) | |
3642 | { | |
c871bc70 LV |
3643 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
3644 | spapr_memory_pre_plug(hotplug_dev, dev, errp); | |
3645 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
94a94e4c BR |
3646 | spapr_core_pre_plug(hotplug_dev, dev, errp); |
3647 | } | |
3648 | } | |
3649 | ||
7ebaf795 BR |
3650 | static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, |
3651 | DeviceState *dev) | |
c20d332a | 3652 | { |
94a94e4c BR |
3653 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
3654 | object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { | |
c20d332a BR |
3655 | return HOTPLUG_HANDLER(machine); |
3656 | } | |
3657 | return NULL; | |
3658 | } | |
3659 | ||
ea089eeb IM |
3660 | static CpuInstanceProperties |
3661 | spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) | |
20bb648d | 3662 | { |
ea089eeb IM |
3663 | CPUArchId *core_slot; |
3664 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3665 | ||
3666 | /* make sure possible_cpu are intialized */ | |
3667 | mc->possible_cpu_arch_ids(machine); | |
3668 | /* get CPU core slot containing thread that matches cpu_index */ | |
3669 | core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); | |
3670 | assert(core_slot); | |
3671 | return core_slot->props; | |
20bb648d DG |
3672 | } |
3673 | ||
79e07936 IM |
3674 | static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) |
3675 | { | |
3676 | return idx / smp_cores % nb_numa_nodes; | |
3677 | } | |
3678 | ||
535455fd IM |
3679 | static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) |
3680 | { | |
3681 | int i; | |
d342eb76 | 3682 | const char *core_type; |
535455fd IM |
3683 | int spapr_max_cores = max_cpus / smp_threads; |
3684 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
3685 | ||
c5514d0e | 3686 | if (!mc->has_hotpluggable_cpus) { |
535455fd IM |
3687 | spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; |
3688 | } | |
3689 | if (machine->possible_cpus) { | |
3690 | assert(machine->possible_cpus->len == spapr_max_cores); | |
3691 | return machine->possible_cpus; | |
3692 | } | |
3693 | ||
d342eb76 IM |
3694 | core_type = spapr_get_cpu_core_type(machine->cpu_type); |
3695 | if (!core_type) { | |
3696 | error_report("Unable to find sPAPR CPU Core definition"); | |
3697 | exit(1); | |
3698 | } | |
3699 | ||
535455fd IM |
3700 | machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
3701 | sizeof(CPUArchId) * spapr_max_cores); | |
3702 | machine->possible_cpus->len = spapr_max_cores; | |
3703 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
3704 | int core_id = i * smp_threads; | |
3705 | ||
d342eb76 | 3706 | machine->possible_cpus->cpus[i].type = core_type; |
f2d672c2 | 3707 | machine->possible_cpus->cpus[i].vcpus_count = smp_threads; |
535455fd IM |
3708 | machine->possible_cpus->cpus[i].arch_id = core_id; |
3709 | machine->possible_cpus->cpus[i].props.has_core_id = true; | |
3710 | machine->possible_cpus->cpus[i].props.core_id = core_id; | |
535455fd IM |
3711 | } |
3712 | return machine->possible_cpus; | |
3713 | } | |
3714 | ||
6737d9ad | 3715 | static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, |
daa23699 DG |
3716 | uint64_t *buid, hwaddr *pio, |
3717 | hwaddr *mmio32, hwaddr *mmio64, | |
6737d9ad DG |
3718 | unsigned n_dma, uint32_t *liobns, Error **errp) |
3719 | { | |
357d1e3b DG |
3720 | /* |
3721 | * New-style PHB window placement. | |
3722 | * | |
3723 | * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window | |
3724 | * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO | |
3725 | * windows. | |
3726 | * | |
3727 | * Some guest kernels can't work with MMIO windows above 1<<46 | |
3728 | * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB | |
3729 | * | |
3730 | * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each | |
3731 | * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the | |
3732 | * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the | |
3733 | * 1TiB 64-bit MMIO windows for each PHB. | |
3734 | */ | |
6737d9ad | 3735 | const uint64_t base_buid = 0x800000020000000ULL; |
25e6a118 MT |
3736 | #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ |
3737 | SPAPR_PCI_MEM64_WIN_SIZE - 1) | |
6737d9ad DG |
3738 | int i; |
3739 | ||
357d1e3b DG |
3740 | /* Sanity check natural alignments */ |
3741 | QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3742 | QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); | |
3743 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); | |
3744 | QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); | |
3745 | /* Sanity check bounds */ | |
25e6a118 MT |
3746 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > |
3747 | SPAPR_PCI_MEM32_WIN_SIZE); | |
3748 | QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > | |
3749 | SPAPR_PCI_MEM64_WIN_SIZE); | |
3750 | ||
3751 | if (index >= SPAPR_MAX_PHBS) { | |
3752 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", | |
3753 | SPAPR_MAX_PHBS - 1); | |
6737d9ad DG |
3754 | return; |
3755 | } | |
3756 | ||
3757 | *buid = base_buid + index; | |
3758 | for (i = 0; i < n_dma; ++i) { | |
3759 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
3760 | } | |
3761 | ||
357d1e3b DG |
3762 | *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; |
3763 | *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; | |
3764 | *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; | |
6737d9ad DG |
3765 | } |
3766 | ||
7844e12b CLG |
3767 | static ICSState *spapr_ics_get(XICSFabric *dev, int irq) |
3768 | { | |
3769 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3770 | ||
3771 | return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; | |
3772 | } | |
3773 | ||
3774 | static void spapr_ics_resend(XICSFabric *dev) | |
3775 | { | |
3776 | sPAPRMachineState *spapr = SPAPR_MACHINE(dev); | |
3777 | ||
3778 | ics_resend(spapr->ics); | |
3779 | } | |
3780 | ||
81210c20 | 3781 | static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) |
b2fc59aa | 3782 | { |
2e886fb3 | 3783 | PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); |
b2fc59aa | 3784 | |
5bc8d26d | 3785 | return cpu ? ICP(cpu->intc) : NULL; |
b2fc59aa CLG |
3786 | } |
3787 | ||
6449da45 CLG |
3788 | static void spapr_pic_print_info(InterruptStatsProvider *obj, |
3789 | Monitor *mon) | |
3790 | { | |
3791 | sPAPRMachineState *spapr = SPAPR_MACHINE(obj); | |
ef01ed9d | 3792 | sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); |
6449da45 | 3793 | |
ef01ed9d | 3794 | smc->irq->print_info(spapr, mon); |
6449da45 CLG |
3795 | } |
3796 | ||
14bb4486 | 3797 | int spapr_get_vcpu_id(PowerPCCPU *cpu) |
2e886fb3 | 3798 | { |
b1a568c1 | 3799 | return cpu->vcpu_id; |
2e886fb3 SB |
3800 | } |
3801 | ||
648edb64 GK |
3802 | void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) |
3803 | { | |
3804 | sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); | |
3805 | int vcpu_id; | |
3806 | ||
5d0fb150 | 3807 | vcpu_id = spapr_vcpu_id(spapr, cpu_index); |
648edb64 GK |
3808 | |
3809 | if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { | |
3810 | error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); | |
3811 | error_append_hint(errp, "Adjust the number of cpus to %d " | |
3812 | "or try to raise the number of threads per core\n", | |
3813 | vcpu_id * smp_threads / spapr->vsmt); | |
3814 | return; | |
3815 | } | |
3816 | ||
3817 | cpu->vcpu_id = vcpu_id; | |
3818 | } | |
3819 | ||
2e886fb3 SB |
3820 | PowerPCCPU *spapr_find_cpu(int vcpu_id) |
3821 | { | |
3822 | CPUState *cs; | |
3823 | ||
3824 | CPU_FOREACH(cs) { | |
3825 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
3826 | ||
14bb4486 | 3827 | if (spapr_get_vcpu_id(cpu) == vcpu_id) { |
2e886fb3 SB |
3828 | return cpu; |
3829 | } | |
3830 | } | |
3831 | ||
3832 | return NULL; | |
3833 | } | |
3834 | ||
29ee3247 AK |
3835 | static void spapr_machine_class_init(ObjectClass *oc, void *data) |
3836 | { | |
3837 | MachineClass *mc = MACHINE_CLASS(oc); | |
224245bf | 3838 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); |
71461b0f | 3839 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
34316482 | 3840 | NMIClass *nc = NMI_CLASS(oc); |
c20d332a | 3841 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
1d1be34d | 3842 | PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); |
7844e12b | 3843 | XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); |
6449da45 | 3844 | InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); |
958db90c | 3845 | |
0eb9054c | 3846 | mc->desc = "pSeries Logical Partition (PAPR compliant)"; |
907aac2f | 3847 | mc->ignore_boot_device_suffixes = true; |
fc9f38c3 DG |
3848 | |
3849 | /* | |
3850 | * We set up the default / latest behaviour here. The class_init | |
3851 | * functions for the specific versioned machine types can override | |
3852 | * these details for backwards compatibility | |
3853 | */ | |
bcb5ce08 DG |
3854 | mc->init = spapr_machine_init; |
3855 | mc->reset = spapr_machine_reset; | |
958db90c | 3856 | mc->block_default_type = IF_SCSI; |
6244bb7e | 3857 | mc->max_cpus = 1024; |
958db90c | 3858 | mc->no_parallel = 1; |
5b2128d2 | 3859 | mc->default_boot_order = ""; |
d23b6caa | 3860 | mc->default_ram_size = 512 * MiB; |
29f9cef3 | 3861 | mc->default_display = "std"; |
958db90c | 3862 | mc->kvm_type = spapr_kvm_type; |
7da79a16 | 3863 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); |
e4024630 | 3864 | mc->pci_allow_0_address = true; |
debbdc00 | 3865 | assert(!mc->get_hotplug_handler); |
7ebaf795 | 3866 | mc->get_hotplug_handler = spapr_get_hotplug_handler; |
94a94e4c | 3867 | hc->pre_plug = spapr_machine_device_pre_plug; |
c20d332a | 3868 | hc->plug = spapr_machine_device_plug; |
ea089eeb | 3869 | mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; |
79e07936 | 3870 | mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; |
535455fd | 3871 | mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; |
cf632463 | 3872 | hc->unplug_request = spapr_machine_device_unplug_request; |
88432f44 | 3873 | hc->unplug = spapr_machine_device_unplug; |
00b4fbe2 | 3874 | |
fc9f38c3 | 3875 | smc->dr_lmb_enabled = true; |
2e9c10eb | 3876 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); |
c5514d0e | 3877 | mc->has_hotpluggable_cpus = true; |
52b81ab5 | 3878 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; |
71461b0f | 3879 | fwc->get_dev_path = spapr_get_fw_dev_path; |
34316482 | 3880 | nc->nmi_monitor_handler = spapr_nmi; |
6737d9ad | 3881 | smc->phb_placement = spapr_phb_placement; |
1d1be34d | 3882 | vhc->hypercall = emulate_spapr_hypercall; |
e57ca75c DG |
3883 | vhc->hpt_mask = spapr_hpt_mask; |
3884 | vhc->map_hptes = spapr_map_hptes; | |
3885 | vhc->unmap_hptes = spapr_unmap_hptes; | |
3886 | vhc->store_hpte = spapr_store_hpte; | |
9861bb3e | 3887 | vhc->get_patbe = spapr_get_patbe; |
1ec26c75 | 3888 | vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; |
7844e12b CLG |
3889 | xic->ics_get = spapr_ics_get; |
3890 | xic->ics_resend = spapr_ics_resend; | |
b2fc59aa | 3891 | xic->icp_get = spapr_icp_get; |
6449da45 | 3892 | ispc->print_info = spapr_pic_print_info; |
55641213 LV |
3893 | /* Force NUMA node memory size to be a multiple of |
3894 | * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity | |
3895 | * in which LMBs are represented and hot-added | |
3896 | */ | |
3897 | mc->numa_mem_align_shift = 28; | |
33face6b | 3898 | |
4e5fe368 SJS |
3899 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; |
3900 | smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; | |
3901 | smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; | |
8f38eaf8 | 3902 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; |
09114fd8 | 3903 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; |
4be8d4e7 | 3904 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; |
2309832a | 3905 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ |
b9a477b7 | 3906 | smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; |
33face6b | 3907 | spapr_caps_add_properties(smc, &error_abort); |
ef01ed9d | 3908 | smc->irq = &spapr_irq_xics; |
29ee3247 AK |
3909 | } |
3910 | ||
3911 | static const TypeInfo spapr_machine_info = { | |
3912 | .name = TYPE_SPAPR_MACHINE, | |
3913 | .parent = TYPE_MACHINE, | |
4aee7362 | 3914 | .abstract = true, |
6ca1502e | 3915 | .instance_size = sizeof(sPAPRMachineState), |
bcb5ce08 | 3916 | .instance_init = spapr_instance_init, |
87bbdd9c | 3917 | .instance_finalize = spapr_machine_finalizefn, |
183930c0 | 3918 | .class_size = sizeof(sPAPRMachineClass), |
29ee3247 | 3919 | .class_init = spapr_machine_class_init, |
71461b0f AK |
3920 | .interfaces = (InterfaceInfo[]) { |
3921 | { TYPE_FW_PATH_PROVIDER }, | |
34316482 | 3922 | { TYPE_NMI }, |
c20d332a | 3923 | { TYPE_HOTPLUG_HANDLER }, |
1d1be34d | 3924 | { TYPE_PPC_VIRTUAL_HYPERVISOR }, |
7844e12b | 3925 | { TYPE_XICS_FABRIC }, |
6449da45 | 3926 | { TYPE_INTERRUPT_STATS_PROVIDER }, |
71461b0f AK |
3927 | { } |
3928 | }, | |
29ee3247 AK |
3929 | }; |
3930 | ||
fccbc785 | 3931 | #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ |
5013c547 DG |
3932 | static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ |
3933 | void *data) \ | |
3934 | { \ | |
3935 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
3936 | spapr_machine_##suffix##_class_options(mc); \ | |
fccbc785 DG |
3937 | if (latest) { \ |
3938 | mc->alias = "pseries"; \ | |
3939 | mc->is_default = 1; \ | |
3940 | } \ | |
5013c547 | 3941 | } \ |
5013c547 DG |
3942 | static const TypeInfo spapr_machine_##suffix##_info = { \ |
3943 | .name = MACHINE_TYPE_NAME("pseries-" verstr), \ | |
3944 | .parent = TYPE_SPAPR_MACHINE, \ | |
3945 | .class_init = spapr_machine_##suffix##_class_init, \ | |
5013c547 DG |
3946 | }; \ |
3947 | static void spapr_machine_register_##suffix(void) \ | |
3948 | { \ | |
3949 | type_register(&spapr_machine_##suffix##_info); \ | |
3950 | } \ | |
0e6aac87 | 3951 | type_init(spapr_machine_register_##suffix) |
5013c547 | 3952 | |
84e060bf AW |
3953 | /* |
3954 | * pseries-4.0 | |
3955 | */ | |
84e060bf AW |
3956 | static void spapr_machine_4_0_class_options(MachineClass *mc) |
3957 | { | |
3958 | /* Defaults for the latest behaviour inherited from the base class */ | |
3959 | } | |
3960 | ||
3961 | DEFINE_SPAPR_MACHINE(4_0, "4.0", true); | |
3962 | ||
3963 | /* | |
d45360d9 CLG |
3964 | * pseries-3.1 |
3965 | */ | |
84e060bf AW |
3966 | #define SPAPR_COMPAT_3_1 \ |
3967 | HW_COMPAT_3_1 | |
3968 | ||
d45360d9 CLG |
3969 | static void spapr_machine_3_1_class_options(MachineClass *mc) |
3970 | { | |
84e060bf AW |
3971 | spapr_machine_4_0_class_options(mc); |
3972 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_1); | |
d45360d9 CLG |
3973 | } |
3974 | ||
84e060bf | 3975 | DEFINE_SPAPR_MACHINE(3_1, "3.1", false); |
d45360d9 | 3976 | |
8a4fd427 | 3977 | /* |
d8c0c7af | 3978 | * pseries-3.0 |
8a4fd427 | 3979 | */ |
d45360d9 CLG |
3980 | #define SPAPR_COMPAT_3_0 \ |
3981 | HW_COMPAT_3_0 | |
3982 | ||
d8c0c7af | 3983 | static void spapr_machine_3_0_class_options(MachineClass *mc) |
8a4fd427 | 3984 | { |
82cffa2e CLG |
3985 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
3986 | ||
d45360d9 CLG |
3987 | spapr_machine_3_1_class_options(mc); |
3988 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0); | |
82cffa2e CLG |
3989 | |
3990 | smc->legacy_irq_allocation = true; | |
ae837402 | 3991 | smc->irq = &spapr_irq_xics_legacy; |
8a4fd427 DG |
3992 | } |
3993 | ||
d45360d9 | 3994 | DEFINE_SPAPR_MACHINE(3_0, "3.0", false); |
8a4fd427 | 3995 | |
2b615412 DG |
3996 | /* |
3997 | * pseries-2.12 | |
3998 | */ | |
8a4fd427 | 3999 | #define SPAPR_COMPAT_2_12 \ |
67d7d66f DG |
4000 | HW_COMPAT_2_12 \ |
4001 | { \ | |
4002 | .driver = TYPE_POWERPC_CPU, \ | |
b9402026 GK |
4003 | .property = "pre-3.0-migration", \ |
4004 | .value = "on", \ | |
4005 | }, \ | |
4006 | { \ | |
4007 | .driver = TYPE_SPAPR_CPU_CORE, \ | |
4008 | .property = "pre-3.0-migration", \ | |
67d7d66f DG |
4009 | .value = "on", \ |
4010 | }, | |
8a4fd427 | 4011 | |
2b615412 DG |
4012 | static void spapr_machine_2_12_class_options(MachineClass *mc) |
4013 | { | |
2309832a | 4014 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
2309832a | 4015 | |
d8c0c7af | 4016 | spapr_machine_3_0_class_options(mc); |
8a4fd427 | 4017 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); |
2309832a | 4018 | |
e8937295 GK |
4019 | /* We depend on kvm_enabled() to choose a default value for the |
4020 | * hpt-max-page-size capability. Of course we can't do it here | |
4021 | * because this is too early and the HW accelerator isn't initialzed | |
4022 | * yet. Postpone this to machine init (see default_caps_with_cpu()). | |
4023 | */ | |
4024 | smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; | |
2b615412 DG |
4025 | } |
4026 | ||
8a4fd427 | 4027 | DEFINE_SPAPR_MACHINE(2_12, "2.12", false); |
2b615412 | 4028 | |
813f3cf6 SJS |
4029 | static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) |
4030 | { | |
4031 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); | |
4032 | ||
4033 | spapr_machine_2_12_class_options(mc); | |
4034 | smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; | |
4035 | smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; | |
4036 | smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; | |
4037 | } | |
4038 | ||
4039 | DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); | |
4040 | ||
e2676b16 GK |
4041 | /* |
4042 | * pseries-2.11 | |
4043 | */ | |
2b615412 DG |
4044 | #define SPAPR_COMPAT_2_11 \ |
4045 | HW_COMPAT_2_11 | |
4046 | ||
e2676b16 GK |
4047 | static void spapr_machine_2_11_class_options(MachineClass *mc) |
4048 | { | |
ee76a09f DG |
4049 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4050 | ||
2b615412 | 4051 | spapr_machine_2_12_class_options(mc); |
4e5fe368 | 4052 | smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; |
2b615412 | 4053 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); |
e2676b16 GK |
4054 | } |
4055 | ||
2b615412 | 4056 | DEFINE_SPAPR_MACHINE(2_11, "2.11", false); |
e2676b16 | 4057 | |
3fa14fbe DG |
4058 | /* |
4059 | * pseries-2.10 | |
4060 | */ | |
e2676b16 | 4061 | #define SPAPR_COMPAT_2_10 \ |
2b615412 | 4062 | HW_COMPAT_2_10 |
e2676b16 | 4063 | |
3fa14fbe DG |
4064 | static void spapr_machine_2_10_class_options(MachineClass *mc) |
4065 | { | |
e2676b16 GK |
4066 | spapr_machine_2_11_class_options(mc); |
4067 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); | |
3fa14fbe DG |
4068 | } |
4069 | ||
e2676b16 | 4070 | DEFINE_SPAPR_MACHINE(2_10, "2.10", false); |
3fa14fbe | 4071 | |
fa325e6c DG |
4072 | /* |
4073 | * pseries-2.9 | |
4074 | */ | |
3fa14fbe | 4075 | #define SPAPR_COMPAT_2_9 \ |
d5fc133e DG |
4076 | HW_COMPAT_2_9 \ |
4077 | { \ | |
4078 | .driver = TYPE_POWERPC_CPU, \ | |
4079 | .property = "pre-2.10-migration", \ | |
4080 | .value = "on", \ | |
4081 | }, \ | |
3fa14fbe | 4082 | |
fa325e6c DG |
4083 | static void spapr_machine_2_9_class_options(MachineClass *mc) |
4084 | { | |
46f7afa3 GK |
4085 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4086 | ||
3fa14fbe DG |
4087 | spapr_machine_2_10_class_options(mc); |
4088 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); | |
3bfe5716 | 4089 | mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; |
46f7afa3 | 4090 | smc->pre_2_10_has_unused_icps = true; |
52b81ab5 | 4091 | smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; |
fa325e6c DG |
4092 | } |
4093 | ||
3fa14fbe | 4094 | DEFINE_SPAPR_MACHINE(2_9, "2.9", false); |
fa325e6c | 4095 | |
db800b21 DG |
4096 | /* |
4097 | * pseries-2.8 | |
4098 | */ | |
82516263 DG |
4099 | #define SPAPR_COMPAT_2_8 \ |
4100 | HW_COMPAT_2_8 \ | |
4101 | { \ | |
4102 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4103 | .property = "pcie-extended-configuration-space", \ | |
4104 | .value = "off", \ | |
4105 | }, | |
fa325e6c | 4106 | |
db800b21 DG |
4107 | static void spapr_machine_2_8_class_options(MachineClass *mc) |
4108 | { | |
fa325e6c DG |
4109 | spapr_machine_2_9_class_options(mc); |
4110 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); | |
55641213 | 4111 | mc->numa_mem_align_shift = 23; |
db800b21 DG |
4112 | } |
4113 | ||
fa325e6c | 4114 | DEFINE_SPAPR_MACHINE(2_8, "2.8", false); |
db800b21 | 4115 | |
1ea1eefc BR |
4116 | /* |
4117 | * pseries-2.7 | |
4118 | */ | |
357d1e3b DG |
4119 | #define SPAPR_COMPAT_2_7 \ |
4120 | HW_COMPAT_2_7 \ | |
4121 | { \ | |
4122 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4123 | .property = "mem_win_size", \ | |
4124 | .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ | |
4125 | }, \ | |
4126 | { \ | |
4127 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4128 | .property = "mem64_win_size", \ | |
4129 | .value = "0", \ | |
146c11f1 DG |
4130 | }, \ |
4131 | { \ | |
4132 | .driver = TYPE_POWERPC_CPU, \ | |
4133 | .property = "pre-2.8-migration", \ | |
4134 | .value = "on", \ | |
5c4537bd DG |
4135 | }, \ |
4136 | { \ | |
4137 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ | |
4138 | .property = "pre-2.8-migration", \ | |
4139 | .value = "on", \ | |
357d1e3b DG |
4140 | }, |
4141 | ||
4142 | static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, | |
4143 | uint64_t *buid, hwaddr *pio, | |
4144 | hwaddr *mmio32, hwaddr *mmio64, | |
4145 | unsigned n_dma, uint32_t *liobns, Error **errp) | |
4146 | { | |
4147 | /* Legacy PHB placement for pseries-2.7 and earlier machine types */ | |
4148 | const uint64_t base_buid = 0x800000020000000ULL; | |
4149 | const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ | |
4150 | const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ | |
4151 | const hwaddr pio_offset = 0x80000000; /* 2 GiB */ | |
4152 | const uint32_t max_index = 255; | |
4153 | const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ | |
4154 | ||
4155 | uint64_t ram_top = MACHINE(spapr)->ram_size; | |
4156 | hwaddr phb0_base, phb_base; | |
4157 | int i; | |
4158 | ||
0c9269a5 | 4159 | /* Do we have device memory? */ |
357d1e3b DG |
4160 | if (MACHINE(spapr)->maxram_size > ram_top) { |
4161 | /* Can't just use maxram_size, because there may be an | |
0c9269a5 DH |
4162 | * alignment gap between normal and device memory regions |
4163 | */ | |
b0c14ec4 DH |
4164 | ram_top = MACHINE(spapr)->device_memory->base + |
4165 | memory_region_size(&MACHINE(spapr)->device_memory->mr); | |
357d1e3b DG |
4166 | } |
4167 | ||
4168 | phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); | |
4169 | ||
4170 | if (index > max_index) { | |
4171 | error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", | |
4172 | max_index); | |
4173 | return; | |
4174 | } | |
4175 | ||
4176 | *buid = base_buid + index; | |
4177 | for (i = 0; i < n_dma; ++i) { | |
4178 | liobns[i] = SPAPR_PCI_LIOBN(index, i); | |
4179 | } | |
4180 | ||
4181 | phb_base = phb0_base + index * phb_spacing; | |
4182 | *pio = phb_base + pio_offset; | |
4183 | *mmio32 = phb_base + mmio_offset; | |
4184 | /* | |
4185 | * We don't set the 64-bit MMIO window, relying on the PHB's | |
4186 | * fallback behaviour of automatically splitting a large "32-bit" | |
4187 | * window into contiguous 32-bit and 64-bit windows | |
4188 | */ | |
4189 | } | |
db800b21 | 4190 | |
1ea1eefc BR |
4191 | static void spapr_machine_2_7_class_options(MachineClass *mc) |
4192 | { | |
3daa4a9f TH |
4193 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4194 | ||
db800b21 | 4195 | spapr_machine_2_8_class_options(mc); |
2e9c10eb | 4196 | mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); |
a140c199 | 4197 | mc->default_machine_opts = "modern-hotplug-events=off"; |
db800b21 | 4198 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); |
357d1e3b | 4199 | smc->phb_placement = phb_placement_2_7; |
1ea1eefc BR |
4200 | } |
4201 | ||
db800b21 | 4202 | DEFINE_SPAPR_MACHINE(2_7, "2.7", false); |
1ea1eefc | 4203 | |
4b23699c DG |
4204 | /* |
4205 | * pseries-2.6 | |
4206 | */ | |
1ea1eefc | 4207 | #define SPAPR_COMPAT_2_6 \ |
ae4de14c AK |
4208 | HW_COMPAT_2_6 \ |
4209 | { \ | |
4210 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4211 | .property = "ddw",\ | |
4212 | .value = stringify(off),\ | |
4213 | }, | |
1ea1eefc | 4214 | |
4b23699c DG |
4215 | static void spapr_machine_2_6_class_options(MachineClass *mc) |
4216 | { | |
1ea1eefc | 4217 | spapr_machine_2_7_class_options(mc); |
c5514d0e | 4218 | mc->has_hotpluggable_cpus = false; |
1ea1eefc | 4219 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); |
4b23699c DG |
4220 | } |
4221 | ||
1ea1eefc | 4222 | DEFINE_SPAPR_MACHINE(2_6, "2.6", false); |
4b23699c | 4223 | |
1c5f29bb DG |
4224 | /* |
4225 | * pseries-2.5 | |
4226 | */ | |
4b23699c | 4227 | #define SPAPR_COMPAT_2_5 \ |
57c522f4 TH |
4228 | HW_COMPAT_2_5 \ |
4229 | { \ | |
4230 | .driver = "spapr-vlan", \ | |
4231 | .property = "use-rx-buffer-pools", \ | |
4232 | .value = "off", \ | |
4233 | }, | |
4b23699c | 4234 | |
5013c547 DG |
4235 | static void spapr_machine_2_5_class_options(MachineClass *mc) |
4236 | { | |
57040d45 TH |
4237 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4238 | ||
4b23699c | 4239 | spapr_machine_2_6_class_options(mc); |
57040d45 | 4240 | smc->use_ohci_by_default = true; |
4b23699c | 4241 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); |
1c5f29bb DG |
4242 | } |
4243 | ||
4b23699c | 4244 | DEFINE_SPAPR_MACHINE(2_5, "2.5", false); |
1c5f29bb DG |
4245 | |
4246 | /* | |
4247 | * pseries-2.4 | |
4248 | */ | |
80fd50f9 CH |
4249 | #define SPAPR_COMPAT_2_4 \ |
4250 | HW_COMPAT_2_4 | |
4251 | ||
5013c547 DG |
4252 | static void spapr_machine_2_4_class_options(MachineClass *mc) |
4253 | { | |
fc9f38c3 DG |
4254 | sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); |
4255 | ||
4256 | spapr_machine_2_5_class_options(mc); | |
fc9f38c3 | 4257 | smc->dr_lmb_enabled = false; |
f949b4e5 | 4258 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); |
1c5f29bb DG |
4259 | } |
4260 | ||
fccbc785 | 4261 | DEFINE_SPAPR_MACHINE(2_4, "2.4", false); |
1c5f29bb DG |
4262 | |
4263 | /* | |
4264 | * pseries-2.3 | |
4265 | */ | |
38ff32c6 | 4266 | #define SPAPR_COMPAT_2_3 \ |
7619c7b0 MR |
4267 | HW_COMPAT_2_3 \ |
4268 | {\ | |
4269 | .driver = "spapr-pci-host-bridge",\ | |
4270 | .property = "dynamic-reconfiguration",\ | |
4271 | .value = "off",\ | |
4272 | }, | |
38ff32c6 | 4273 | |
5013c547 | 4274 | static void spapr_machine_2_3_class_options(MachineClass *mc) |
6026db45 | 4275 | { |
fc9f38c3 | 4276 | spapr_machine_2_4_class_options(mc); |
f949b4e5 | 4277 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); |
6026db45 | 4278 | } |
fccbc785 | 4279 | DEFINE_SPAPR_MACHINE(2_3, "2.3", false); |
6026db45 | 4280 | |
1c5f29bb DG |
4281 | /* |
4282 | * pseries-2.2 | |
4283 | */ | |
4284 | ||
4285 | #define SPAPR_COMPAT_2_2 \ | |
1c5f29bb DG |
4286 | HW_COMPAT_2_2 \ |
4287 | {\ | |
4288 | .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ | |
4289 | .property = "mem_win_size",\ | |
4290 | .value = "0x20000000",\ | |
4291 | }, | |
4292 | ||
5013c547 | 4293 | static void spapr_machine_2_2_class_options(MachineClass *mc) |
4aee7362 | 4294 | { |
fc9f38c3 | 4295 | spapr_machine_2_3_class_options(mc); |
f949b4e5 | 4296 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); |
f6d0656b | 4297 | mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; |
4aee7362 | 4298 | } |
fccbc785 | 4299 | DEFINE_SPAPR_MACHINE(2_2, "2.2", false); |
4aee7362 | 4300 | |
1c5f29bb DG |
4301 | /* |
4302 | * pseries-2.1 | |
4303 | */ | |
4304 | #define SPAPR_COMPAT_2_1 \ | |
1c5f29bb | 4305 | HW_COMPAT_2_1 |
3dab0244 | 4306 | |
5013c547 | 4307 | static void spapr_machine_2_1_class_options(MachineClass *mc) |
d25228e7 | 4308 | { |
fc9f38c3 | 4309 | spapr_machine_2_2_class_options(mc); |
f949b4e5 | 4310 | SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); |
d25228e7 | 4311 | } |
fccbc785 | 4312 | DEFINE_SPAPR_MACHINE(2_1, "2.1", false); |
fb0fc8f6 | 4313 | |
29ee3247 | 4314 | static void spapr_machine_register_types(void) |
9fdf0c29 | 4315 | { |
29ee3247 | 4316 | type_register_static(&spapr_machine_info); |
9fdf0c29 DG |
4317 | } |
4318 | ||
29ee3247 | 4319 | type_init(spapr_machine_register_types) |