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Commit | Line | Data |
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bbf5c878 MR |
1 | /* |
2 | * QEMU SPAPR Dynamic Reconfiguration Connector Implementation | |
3 | * | |
4 | * Copyright IBM Corp. 2014 | |
5 | * | |
6 | * Authors: | |
7 | * Michael Roth <mdroth@linux.vnet.ibm.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
0d75590d | 13 | #include "qemu/osdep.h" |
da34e65c | 14 | #include "qapi/error.h" |
15280c36 | 15 | #include "qapi/qmp/qnull.h" |
4771d756 | 16 | #include "cpu.h" |
f348b6d1 | 17 | #include "qemu/cutils.h" |
bbf5c878 MR |
18 | #include "hw/ppc/spapr_drc.h" |
19 | #include "qom/object.h" | |
d6454270 | 20 | #include "migration/vmstate.h" |
bbf5c878 MR |
21 | #include "qapi/visitor.h" |
22 | #include "qemu/error-report.h" | |
0cb688d2 | 23 | #include "hw/ppc/spapr.h" /* for RTAS return codes */ |
31834723 | 24 | #include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback */ |
ee3a71e3 | 25 | #include "hw/ppc/spapr_nvdimm.h" |
d9c95c71 | 26 | #include "sysemu/device_tree.h" |
71e8a915 | 27 | #include "sysemu/reset.h" |
24ac7755 | 28 | #include "trace.h" |
bbf5c878 MR |
29 | |
30 | #define DRC_CONTAINER_PATH "/dr-connector" | |
31 | #define DRC_INDEX_TYPE_SHIFT 28 | |
627c2ef7 | 32 | #define DRC_INDEX_ID_MASK ((1ULL << DRC_INDEX_TYPE_SHIFT) - 1) |
bbf5c878 | 33 | |
ce2918cb | 34 | SpaprDrcType spapr_drc_type(SpaprDrc *drc) |
2d335818 | 35 | { |
ce2918cb | 36 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
2d335818 DG |
37 | |
38 | return 1 << drck->typeshift; | |
39 | } | |
40 | ||
ce2918cb | 41 | uint32_t spapr_drc_index(SpaprDrc *drc) |
bbf5c878 | 42 | { |
ce2918cb | 43 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
2d335818 | 44 | |
bbf5c878 MR |
45 | /* no set format for a drc index: it only needs to be globally |
46 | * unique. this is how we encode the DRC type on bare-metal | |
47 | * however, so might as well do that here | |
48 | */ | |
2d335818 DG |
49 | return (drck->typeshift << DRC_INDEX_TYPE_SHIFT) |
50 | | (drc->id & DRC_INDEX_ID_MASK); | |
bbf5c878 MR |
51 | } |
52 | ||
66d10d32 DHB |
53 | static void spapr_drc_release(SpaprDrc *drc) |
54 | { | |
55 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
56 | ||
57 | drck->release(drc->dev); | |
58 | ||
59 | drc->unplug_requested = false; | |
60 | g_free(drc->fdt); | |
61 | drc->fdt = NULL; | |
62 | drc->fdt_start_offset = 0; | |
63 | object_property_del(OBJECT(drc), "device"); | |
64 | drc->dev = NULL; | |
65 | } | |
66 | ||
ce2918cb | 67 | static uint32_t drc_isolate_physical(SpaprDrc *drc) |
bbf5c878 | 68 | { |
9d4c0f4f DG |
69 | switch (drc->state) { |
70 | case SPAPR_DRC_STATE_PHYSICAL_POWERON: | |
71 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
72 | case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED: | |
73 | break; /* see below */ | |
74 | case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE: | |
75 | return RTAS_OUT_PARAM_ERROR; /* not allowed */ | |
76 | default: | |
77 | g_assert_not_reached(); | |
78 | } | |
79 | ||
9d4c0f4f | 80 | drc->state = SPAPR_DRC_STATE_PHYSICAL_POWERON; |
0dfabd39 | 81 | |
f1c52354 | 82 | if (drc->unplug_requested) { |
0dfabd39 | 83 | uint32_t drc_index = spapr_drc_index(drc); |
9d4c0f4f | 84 | trace_spapr_drc_set_isolation_state_finalizing(drc_index); |
66d10d32 | 85 | spapr_drc_release(drc); |
9d1852ce | 86 | } |
0dfabd39 DG |
87 | |
88 | return RTAS_OUT_SUCCESS; | |
89 | } | |
90 | ||
ce2918cb | 91 | static uint32_t drc_unisolate_physical(SpaprDrc *drc) |
0dfabd39 | 92 | { |
9d4c0f4f DG |
93 | switch (drc->state) { |
94 | case SPAPR_DRC_STATE_PHYSICAL_UNISOLATE: | |
95 | case SPAPR_DRC_STATE_PHYSICAL_CONFIGURED: | |
96 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
97 | case SPAPR_DRC_STATE_PHYSICAL_POWERON: | |
98 | break; /* see below */ | |
99 | default: | |
100 | g_assert_not_reached(); | |
101 | } | |
102 | ||
0dfabd39 DG |
103 | /* cannot unisolate a non-existent resource, and, or resources |
104 | * which are in an 'UNUSABLE' allocation state. (PAPR 2.7, | |
105 | * 13.5.3.5) | |
106 | */ | |
107 | if (!drc->dev) { | |
108 | return RTAS_OUT_NO_SUCH_INDICATOR; | |
109 | } | |
110 | ||
9d4c0f4f | 111 | drc->state = SPAPR_DRC_STATE_PHYSICAL_UNISOLATE; |
4445b1d2 DG |
112 | drc->ccs_offset = drc->fdt_start_offset; |
113 | drc->ccs_depth = 0; | |
0dfabd39 DG |
114 | |
115 | return RTAS_OUT_SUCCESS; | |
116 | } | |
117 | ||
ce2918cb | 118 | static uint32_t drc_isolate_logical(SpaprDrc *drc) |
0dfabd39 | 119 | { |
9d4c0f4f DG |
120 | switch (drc->state) { |
121 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: | |
122 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: | |
123 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
124 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: | |
125 | break; /* see below */ | |
126 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: | |
127 | return RTAS_OUT_PARAM_ERROR; /* not allowed */ | |
128 | default: | |
129 | g_assert_not_reached(); | |
130 | } | |
131 | ||
cf632463 BR |
132 | /* |
133 | * Fail any requests to ISOLATE the LMB DRC if this LMB doesn't | |
134 | * belong to a DIMM device that is marked for removal. | |
135 | * | |
136 | * Currently the guest userspace tool drmgr that drives the memory | |
137 | * hotplug/unplug will just try to remove a set of 'removable' LMBs | |
138 | * in response to a hot unplug request that is based on drc-count. | |
139 | * If the LMB being removed doesn't belong to a DIMM device that is | |
140 | * actually being unplugged, fail the isolation request here. | |
141 | */ | |
0dfabd39 | 142 | if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB |
f1c52354 | 143 | && !drc->unplug_requested) { |
0dfabd39 | 144 | return RTAS_OUT_HW_ERROR; |
cf632463 BR |
145 | } |
146 | ||
9d4c0f4f | 147 | drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE; |
bbf5c878 | 148 | |
0dfabd39 DG |
149 | return RTAS_OUT_SUCCESS; |
150 | } | |
151 | ||
ce2918cb | 152 | static uint32_t drc_unisolate_logical(SpaprDrc *drc) |
0dfabd39 | 153 | { |
9d4c0f4f DG |
154 | switch (drc->state) { |
155 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: | |
156 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: | |
157 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
158 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: | |
159 | break; /* see below */ | |
160 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: | |
161 | return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */ | |
162 | default: | |
163 | g_assert_not_reached(); | |
0dfabd39 DG |
164 | } |
165 | ||
9d4c0f4f DG |
166 | /* Move to AVAILABLE state should have ensured device was present */ |
167 | g_assert(drc->dev); | |
bbf5c878 | 168 | |
9d4c0f4f | 169 | drc->state = SPAPR_DRC_STATE_LOGICAL_UNISOLATE; |
4445b1d2 DG |
170 | drc->ccs_offset = drc->fdt_start_offset; |
171 | drc->ccs_depth = 0; | |
172 | ||
0cb688d2 | 173 | return RTAS_OUT_SUCCESS; |
bbf5c878 MR |
174 | } |
175 | ||
ce2918cb | 176 | static uint32_t drc_set_usable(SpaprDrc *drc) |
bbf5c878 | 177 | { |
9d4c0f4f DG |
178 | switch (drc->state) { |
179 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: | |
180 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: | |
181 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: | |
182 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
183 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: | |
184 | break; /* see below */ | |
185 | default: | |
186 | g_assert_not_reached(); | |
187 | } | |
188 | ||
61736732 DG |
189 | /* if there's no resource/device associated with the DRC, there's |
190 | * no way for us to put it in an allocation state consistent with | |
191 | * being 'USABLE'. PAPR 2.7, 13.5.3.4 documents that this should | |
192 | * result in an RTAS return code of -3 / "no such indicator" | |
193 | */ | |
194 | if (!drc->dev) { | |
195 | return RTAS_OUT_NO_SUCH_INDICATOR; | |
196 | } | |
f1c52354 | 197 | if (drc->unplug_requested) { |
82a93a1d DG |
198 | /* Don't allow the guest to move a device away from UNUSABLE |
199 | * state when we want to unplug it */ | |
61736732 | 200 | return RTAS_OUT_NO_SUCH_INDICATOR; |
9d1852ce MR |
201 | } |
202 | ||
9d4c0f4f | 203 | drc->state = SPAPR_DRC_STATE_LOGICAL_AVAILABLE; |
61736732 DG |
204 | |
205 | return RTAS_OUT_SUCCESS; | |
206 | } | |
207 | ||
ce2918cb | 208 | static uint32_t drc_set_unusable(SpaprDrc *drc) |
61736732 | 209 | { |
9d4c0f4f DG |
210 | switch (drc->state) { |
211 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: | |
212 | return RTAS_OUT_SUCCESS; /* Nothing to do */ | |
213 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: | |
214 | break; /* see below */ | |
215 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: | |
216 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: | |
217 | return RTAS_OUT_NO_SUCH_INDICATOR; /* not allowed */ | |
218 | default: | |
219 | g_assert_not_reached(); | |
220 | } | |
221 | ||
222 | drc->state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE; | |
f1c52354 | 223 | if (drc->unplug_requested) { |
61736732 DG |
224 | uint32_t drc_index = spapr_drc_index(drc); |
225 | trace_spapr_drc_set_allocation_state_finalizing(drc_index); | |
66d10d32 | 226 | spapr_drc_release(drc); |
bbf5c878 | 227 | } |
61736732 | 228 | |
0cb688d2 | 229 | return RTAS_OUT_SUCCESS; |
bbf5c878 MR |
230 | } |
231 | ||
dbd26f2f | 232 | static char *spapr_drc_name(SpaprDrc *drc) |
bbf5c878 | 233 | { |
ce2918cb | 234 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
79808336 DG |
235 | |
236 | /* human-readable name for a DRC to encode into the DT | |
237 | * description. this is mainly only used within a guest in place | |
238 | * of the unique DRC index. | |
239 | * | |
240 | * in the case of VIO/PCI devices, it corresponds to a "location | |
241 | * code" that maps a logical device/function (DRC index) to a | |
242 | * physical (or virtual in the case of VIO) location in the system | |
243 | * by chaining together the "location label" for each | |
244 | * encapsulating component. | |
245 | * | |
246 | * since this is more to do with diagnosing physical hardware | |
247 | * issues than guest compatibility, we choose location codes/DRC | |
248 | * names that adhere to the documented format, but avoid encoding | |
249 | * the entire topology information into the label/code, instead | |
250 | * just using the location codes based on the labels for the | |
251 | * endpoints (VIO/PCI adaptor connectors), which is basically just | |
252 | * "C" followed by an integer ID. | |
253 | * | |
254 | * DRC names as documented by PAPR+ v2.7, 13.5.2.4 | |
255 | * location codes as documented by PAPR+ v2.7, 12.3.1.5 | |
256 | */ | |
257 | return g_strdup_printf("%s%d", drck->drc_name_prefix, drc->id); | |
bbf5c878 MR |
258 | } |
259 | ||
bbf5c878 MR |
260 | /* |
261 | * dr-entity-sense sensor value | |
262 | * returned via get-sensor-state RTAS calls | |
263 | * as expected by state diagram in PAPR+ 2.7, 13.4 | |
264 | * based on the current allocation/indicator/power states | |
265 | * for the DR connector. | |
266 | */ | |
ce2918cb | 267 | static SpaprDREntitySense physical_entity_sense(SpaprDrc *drc) |
bbf5c878 | 268 | { |
f224d35b DG |
269 | /* this assumes all PCI devices are assigned to a 'live insertion' |
270 | * power domain, where QEMU manages power state automatically as | |
271 | * opposed to the guest. present, non-PCI resources are unaffected | |
272 | * by power state. | |
273 | */ | |
274 | return drc->dev ? SPAPR_DR_ENTITY_SENSE_PRESENT | |
275 | : SPAPR_DR_ENTITY_SENSE_EMPTY; | |
276 | } | |
277 | ||
ce2918cb | 278 | static SpaprDREntitySense logical_entity_sense(SpaprDrc *drc) |
f224d35b | 279 | { |
9d4c0f4f DG |
280 | switch (drc->state) { |
281 | case SPAPR_DRC_STATE_LOGICAL_UNUSABLE: | |
f224d35b | 282 | return SPAPR_DR_ENTITY_SENSE_UNUSABLE; |
9d4c0f4f DG |
283 | case SPAPR_DRC_STATE_LOGICAL_AVAILABLE: |
284 | case SPAPR_DRC_STATE_LOGICAL_UNISOLATE: | |
285 | case SPAPR_DRC_STATE_LOGICAL_CONFIGURED: | |
286 | g_assert(drc->dev); | |
287 | return SPAPR_DR_ENTITY_SENSE_PRESENT; | |
288 | default: | |
289 | g_assert_not_reached(); | |
bbf5c878 | 290 | } |
bbf5c878 MR |
291 | } |
292 | ||
d7bce999 EB |
293 | static void prop_get_index(Object *obj, Visitor *v, const char *name, |
294 | void *opaque, Error **errp) | |
bbf5c878 | 295 | { |
ce2918cb | 296 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
0b55aa91 | 297 | uint32_t value = spapr_drc_index(drc); |
51e72bc1 | 298 | visit_type_uint32(v, name, &value, errp); |
bbf5c878 MR |
299 | } |
300 | ||
d7bce999 EB |
301 | static void prop_get_fdt(Object *obj, Visitor *v, const char *name, |
302 | void *opaque, Error **errp) | |
bbf5c878 | 303 | { |
ce2918cb | 304 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
d2f95f4d | 305 | QNull *null = NULL; |
bbf5c878 MR |
306 | int fdt_offset_next, fdt_offset, fdt_depth; |
307 | void *fdt; | |
308 | ||
309 | if (!drc->fdt) { | |
d2f95f4d | 310 | visit_type_null(v, NULL, &null, errp); |
cb3e7f08 | 311 | qobject_unref(null); |
bbf5c878 MR |
312 | return; |
313 | } | |
314 | ||
315 | fdt = drc->fdt; | |
316 | fdt_offset = drc->fdt_start_offset; | |
317 | fdt_depth = 0; | |
318 | ||
319 | do { | |
320 | const char *name = NULL; | |
321 | const struct fdt_property *prop = NULL; | |
322 | int prop_len = 0, name_len = 0; | |
323 | uint32_t tag; | |
ebd226d2 | 324 | bool ok; |
bbf5c878 MR |
325 | |
326 | tag = fdt_next_tag(fdt, fdt_offset, &fdt_offset_next); | |
327 | switch (tag) { | |
328 | case FDT_BEGIN_NODE: | |
329 | fdt_depth++; | |
330 | name = fdt_get_name(fdt, fdt_offset, &name_len); | |
668f62ec | 331 | if (!visit_start_struct(v, name, NULL, 0, errp)) { |
c75304a1 MA |
332 | return; |
333 | } | |
bbf5c878 MR |
334 | break; |
335 | case FDT_END_NODE: | |
336 | /* shouldn't ever see an FDT_END_NODE before FDT_BEGIN_NODE */ | |
337 | g_assert(fdt_depth > 0); | |
ebd226d2 | 338 | ok = visit_check_struct(v, errp); |
1158bb2a | 339 | visit_end_struct(v, NULL); |
ebd226d2 | 340 | if (!ok) { |
c75304a1 MA |
341 | return; |
342 | } | |
bbf5c878 MR |
343 | fdt_depth--; |
344 | break; | |
345 | case FDT_PROP: { | |
346 | int i; | |
347 | prop = fdt_get_property_by_offset(fdt, fdt_offset, &prop_len); | |
348 | name = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); | |
668f62ec | 349 | if (!visit_start_list(v, name, NULL, 0, errp)) { |
c75304a1 MA |
350 | return; |
351 | } | |
bbf5c878 | 352 | for (i = 0; i < prop_len; i++) { |
62a35aaa | 353 | if (!visit_type_uint8(v, NULL, (uint8_t *)&prop->data[i], |
668f62ec | 354 | errp)) { |
c75304a1 MA |
355 | return; |
356 | } | |
357 | } | |
ebd226d2 | 358 | ok = visit_check_list(v, errp); |
1158bb2a | 359 | visit_end_list(v, NULL); |
ebd226d2 | 360 | if (!ok) { |
a4a1c70d MA |
361 | return; |
362 | } | |
bbf5c878 MR |
363 | break; |
364 | } | |
365 | default: | |
e20c6314 PMD |
366 | error_report("device FDT in unexpected state: %d", tag); |
367 | abort(); | |
bbf5c878 MR |
368 | } |
369 | fdt_offset = fdt_offset_next; | |
370 | } while (fdt_depth != 0); | |
371 | } | |
372 | ||
bc370a65 | 373 | void spapr_drc_attach(SpaprDrc *drc, DeviceState *d) |
bbf5c878 | 374 | { |
0b55aa91 | 375 | trace_spapr_drc_attach(spapr_drc_index(drc)); |
bbf5c878 | 376 | |
bc370a65 | 377 | g_assert(!drc->dev); |
9d4c0f4f DG |
378 | g_assert((drc->state == SPAPR_DRC_STATE_LOGICAL_UNUSABLE) |
379 | || (drc->state == SPAPR_DRC_STATE_PHYSICAL_POWERON)); | |
bbf5c878 | 380 | |
bbf5c878 | 381 | drc->dev = d; |
d9c95c71 | 382 | |
bbf5c878 MR |
383 | object_property_add_link(OBJECT(drc), "device", |
384 | object_get_typename(OBJECT(drc->dev)), | |
385 | (Object **)(&drc->dev), | |
d2623129 | 386 | NULL, 0); |
bbf5c878 MR |
387 | } |
388 | ||
a03509cd | 389 | void spapr_drc_unplug_request(SpaprDrc *drc) |
9c914e53 | 390 | { |
ce2918cb | 391 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
9d4c0f4f | 392 | |
a03509cd | 393 | trace_spapr_drc_unplug_request(spapr_drc_index(drc)); |
9c914e53 | 394 | |
9d4c0f4f | 395 | g_assert(drc->dev); |
a8dc47fd | 396 | |
9d4c0f4f | 397 | drc->unplug_requested = true; |
9c914e53 | 398 | |
9d4c0f4f DG |
399 | if (drc->state != drck->empty_state) { |
400 | trace_spapr_drc_awaiting_quiesce(spapr_drc_index(drc)); | |
9c914e53 DG |
401 | return; |
402 | } | |
403 | ||
9c914e53 DG |
404 | spapr_drc_release(drc); |
405 | } | |
406 | ||
930ef3b5 | 407 | bool spapr_drc_reset(SpaprDrc *drc) |
bbf5c878 | 408 | { |
ce2918cb | 409 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
930ef3b5 | 410 | bool unplug_completed = false; |
9d4c0f4f | 411 | |
0b55aa91 | 412 | trace_spapr_drc_reset(spapr_drc_index(drc)); |
b8fdd530 | 413 | |
bbf5c878 | 414 | /* immediately upon reset we can safely assume DRCs whose devices |
4f9242fc | 415 | * are pending removal can be safely removed. |
bbf5c878 | 416 | */ |
f1c52354 | 417 | if (drc->unplug_requested) { |
4f9242fc | 418 | spapr_drc_release(drc); |
930ef3b5 | 419 | unplug_completed = true; |
4f9242fc DG |
420 | } |
421 | ||
4f9242fc | 422 | if (drc->dev) { |
9d4c0f4f DG |
423 | /* A device present at reset is ready to go, same as coldplugged */ |
424 | drc->state = drck->ready_state; | |
188bfe1b BR |
425 | /* |
426 | * Ensure that we are able to send the FDT fragment again | |
427 | * via configure-connector call if the guest requests. | |
428 | */ | |
429 | drc->ccs_offset = drc->fdt_start_offset; | |
430 | drc->ccs_depth = 0; | |
4f9242fc | 431 | } else { |
9d4c0f4f | 432 | drc->state = drck->empty_state; |
188bfe1b BR |
433 | drc->ccs_offset = -1; |
434 | drc->ccs_depth = -1; | |
bbf5c878 | 435 | } |
930ef3b5 GK |
436 | |
437 | return unplug_completed; | |
bbf5c878 MR |
438 | } |
439 | ||
ab858434 GK |
440 | static bool spapr_drc_unplug_requested_needed(void *opaque) |
441 | { | |
442 | return spapr_drc_unplug_requested(opaque); | |
443 | } | |
444 | ||
445 | static const VMStateDescription vmstate_spapr_drc_unplug_requested = { | |
446 | .name = "spapr_drc/unplug_requested", | |
447 | .version_id = 1, | |
448 | .minimum_version_id = 1, | |
449 | .needed = spapr_drc_unplug_requested_needed, | |
450 | .fields = (VMStateField []) { | |
451 | VMSTATE_BOOL(unplug_requested, SpaprDrc), | |
452 | VMSTATE_END_OF_LIST() | |
453 | } | |
454 | }; | |
455 | ||
cd725bd7 | 456 | static bool spapr_drc_needed(void *opaque) |
a50919dd | 457 | { |
cd725bd7 | 458 | SpaprDrc *drc = opaque; |
ce2918cb | 459 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
a50919dd | 460 | |
4b63db12 GK |
461 | /* |
462 | * If no dev is plugged in there is no need to migrate the DRC state | |
463 | * nor to reset the DRC at CAS. | |
464 | */ | |
c618e300 | 465 | if (!drc->dev) { |
a50919dd DHB |
466 | return false; |
467 | } | |
468 | ||
469 | /* | |
4b63db12 GK |
470 | * We need to reset the DRC at CAS or to migrate the DRC state if it's |
471 | * not equal to the expected long-term state, which is the same as the | |
ab858434 | 472 | * coldplugged initial state, or if an unplug request is pending. |
4b63db12 | 473 | */ |
ab858434 GK |
474 | return drc->state != drck->ready_state || |
475 | spapr_drc_unplug_requested(drc); | |
a50919dd DHB |
476 | } |
477 | ||
478 | static const VMStateDescription vmstate_spapr_drc = { | |
479 | .name = "spapr_drc", | |
480 | .version_id = 1, | |
481 | .minimum_version_id = 1, | |
482 | .needed = spapr_drc_needed, | |
483 | .fields = (VMStateField []) { | |
ce2918cb | 484 | VMSTATE_UINT32(state, SpaprDrc), |
a50919dd | 485 | VMSTATE_END_OF_LIST() |
ab858434 GK |
486 | }, |
487 | .subsections = (const VMStateDescription * []) { | |
488 | &vmstate_spapr_drc_unplug_requested, | |
489 | NULL | |
a50919dd DHB |
490 | } |
491 | }; | |
492 | ||
00f46c92 | 493 | static void drc_realize(DeviceState *d, Error **errp) |
bbf5c878 | 494 | { |
ce2918cb | 495 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(d); |
bbf5c878 | 496 | Object *root_container; |
f5babeac | 497 | gchar *link_name; |
7a309cc9 | 498 | const char *child_name; |
bbf5c878 | 499 | |
0b55aa91 | 500 | trace_spapr_drc_realize(spapr_drc_index(drc)); |
bbf5c878 MR |
501 | /* NOTE: we do this as part of realize/unrealize due to the fact |
502 | * that the guest will communicate with the DRC via RTAS calls | |
503 | * referencing the global DRC index. By unlinking the DRC | |
504 | * from DRC_CONTAINER_PATH/<drc_index> we effectively make it | |
505 | * inaccessible by the guest, since lookups rely on this path | |
506 | * existing in the composition tree | |
507 | */ | |
508 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); | |
f5babeac | 509 | link_name = g_strdup_printf("%x", spapr_drc_index(drc)); |
bbf5c878 | 510 | child_name = object_get_canonical_path_component(OBJECT(drc)); |
0b55aa91 | 511 | trace_spapr_drc_realize_child(spapr_drc_index(drc), child_name); |
bbf5c878 | 512 | object_property_add_alias(root_container, link_name, |
d2623129 | 513 | drc->owner, child_name); |
f5babeac | 514 | g_free(link_name); |
3cad405b | 515 | vmstate_register(VMSTATE_IF(drc), spapr_drc_index(drc), &vmstate_spapr_drc, |
a50919dd | 516 | drc); |
0b55aa91 | 517 | trace_spapr_drc_realize_complete(spapr_drc_index(drc)); |
bbf5c878 MR |
518 | } |
519 | ||
00f46c92 | 520 | static void drc_unrealize(DeviceState *d) |
bbf5c878 | 521 | { |
ce2918cb | 522 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(d); |
bbf5c878 | 523 | Object *root_container; |
f5babeac | 524 | gchar *name; |
bbf5c878 | 525 | |
0b55aa91 | 526 | trace_spapr_drc_unrealize(spapr_drc_index(drc)); |
3cad405b | 527 | vmstate_unregister(VMSTATE_IF(drc), &vmstate_spapr_drc, drc); |
bbf5c878 | 528 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); |
f5babeac | 529 | name = g_strdup_printf("%x", spapr_drc_index(drc)); |
df4fe0b2 | 530 | object_property_del(root_container, name); |
f5babeac | 531 | g_free(name); |
bbf5c878 MR |
532 | } |
533 | ||
ce2918cb | 534 | SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type, |
bbf5c878 MR |
535 | uint32_t id) |
536 | { | |
ce2918cb | 537 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(object_new(type)); |
94649d42 | 538 | char *prop_name; |
bbf5c878 | 539 | |
bbf5c878 MR |
540 | drc->id = id; |
541 | drc->owner = owner; | |
0b55aa91 DG |
542 | prop_name = g_strdup_printf("dr-connector[%"PRIu32"]", |
543 | spapr_drc_index(drc)); | |
d2623129 | 544 | object_property_add_child(owner, prop_name, OBJECT(drc)); |
f3f41030 | 545 | object_unref(OBJECT(drc)); |
ce189ab2 | 546 | qdev_realize(DEVICE(drc), NULL, NULL); |
94649d42 | 547 | g_free(prop_name); |
bbf5c878 | 548 | |
bbf5c878 MR |
549 | return drc; |
550 | } | |
551 | ||
552 | static void spapr_dr_connector_instance_init(Object *obj) | |
553 | { | |
ce2918cb DG |
554 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj); |
555 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
bbf5c878 | 556 | |
d2623129 | 557 | object_property_add_uint32_ptr(obj, "id", &drc->id, OBJ_PROP_FLAG_READ); |
bbf5c878 | 558 | object_property_add(obj, "index", "uint32", prop_get_index, |
d2623129 | 559 | NULL, NULL, NULL); |
bbf5c878 | 560 | object_property_add(obj, "fdt", "struct", prop_get_fdt, |
d2623129 | 561 | NULL, NULL, NULL); |
9d4c0f4f | 562 | drc->state = drck->empty_state; |
bbf5c878 MR |
563 | } |
564 | ||
565 | static void spapr_dr_connector_class_init(ObjectClass *k, void *data) | |
566 | { | |
567 | DeviceClass *dk = DEVICE_CLASS(k); | |
bbf5c878 | 568 | |
00f46c92 GK |
569 | dk->realize = drc_realize; |
570 | dk->unrealize = drc_unrealize; | |
c401ae8c | 571 | /* |
eaf1ffbe GK |
572 | * Reason: DR connector needs to be wired to either the machine or to a |
573 | * PHB in spapr_dr_connector_new(). | |
c401ae8c | 574 | */ |
e90f2a8c | 575 | dk->user_creatable = false; |
bbf5c878 MR |
576 | } |
577 | ||
67fea71b DG |
578 | static bool drc_physical_needed(void *opaque) |
579 | { | |
ce2918cb DG |
580 | SpaprDrcPhysical *drcp = (SpaprDrcPhysical *)opaque; |
581 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(drcp); | |
67fea71b DG |
582 | |
583 | if ((drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_ACTIVE)) | |
584 | || (!drc->dev && (drcp->dr_indicator == SPAPR_DR_INDICATOR_INACTIVE))) { | |
585 | return false; | |
586 | } | |
587 | return true; | |
588 | } | |
589 | ||
590 | static const VMStateDescription vmstate_spapr_drc_physical = { | |
591 | .name = "spapr_drc/physical", | |
592 | .version_id = 1, | |
593 | .minimum_version_id = 1, | |
594 | .needed = drc_physical_needed, | |
595 | .fields = (VMStateField []) { | |
ce2918cb | 596 | VMSTATE_UINT32(dr_indicator, SpaprDrcPhysical), |
67fea71b DG |
597 | VMSTATE_END_OF_LIST() |
598 | } | |
599 | }; | |
600 | ||
601 | static void drc_physical_reset(void *opaque) | |
602 | { | |
ce2918cb DG |
603 | SpaprDrc *drc = SPAPR_DR_CONNECTOR(opaque); |
604 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(drc); | |
67fea71b DG |
605 | |
606 | if (drc->dev) { | |
607 | drcp->dr_indicator = SPAPR_DR_INDICATOR_ACTIVE; | |
608 | } else { | |
609 | drcp->dr_indicator = SPAPR_DR_INDICATOR_INACTIVE; | |
610 | } | |
611 | } | |
612 | ||
613 | static void realize_physical(DeviceState *d, Error **errp) | |
614 | { | |
ce2918cb | 615 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d); |
67fea71b DG |
616 | Error *local_err = NULL; |
617 | ||
00f46c92 | 618 | drc_realize(d, &local_err); |
67fea71b DG |
619 | if (local_err) { |
620 | error_propagate(errp, local_err); | |
621 | return; | |
622 | } | |
623 | ||
3cad405b MAL |
624 | vmstate_register(VMSTATE_IF(drcp), |
625 | spapr_drc_index(SPAPR_DR_CONNECTOR(drcp)), | |
67fea71b DG |
626 | &vmstate_spapr_drc_physical, drcp); |
627 | qemu_register_reset(drc_physical_reset, drcp); | |
628 | } | |
629 | ||
b69c3c21 | 630 | static void unrealize_physical(DeviceState *d) |
379ae096 | 631 | { |
ce2918cb | 632 | SpaprDrcPhysical *drcp = SPAPR_DRC_PHYSICAL(d); |
379ae096 | 633 | |
00f46c92 | 634 | drc_unrealize(d); |
3cad405b | 635 | vmstate_unregister(VMSTATE_IF(drcp), &vmstate_spapr_drc_physical, drcp); |
379ae096 GK |
636 | qemu_unregister_reset(drc_physical_reset, drcp); |
637 | } | |
638 | ||
f224d35b DG |
639 | static void spapr_drc_physical_class_init(ObjectClass *k, void *data) |
640 | { | |
67fea71b | 641 | DeviceClass *dk = DEVICE_CLASS(k); |
ce2918cb | 642 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
f224d35b | 643 | |
67fea71b | 644 | dk->realize = realize_physical; |
379ae096 | 645 | dk->unrealize = unrealize_physical; |
f224d35b | 646 | drck->dr_entity_sense = physical_entity_sense; |
0dfabd39 DG |
647 | drck->isolate = drc_isolate_physical; |
648 | drck->unisolate = drc_unisolate_physical; | |
9d4c0f4f DG |
649 | drck->ready_state = SPAPR_DRC_STATE_PHYSICAL_CONFIGURED; |
650 | drck->empty_state = SPAPR_DRC_STATE_PHYSICAL_POWERON; | |
f224d35b DG |
651 | } |
652 | ||
653 | static void spapr_drc_logical_class_init(ObjectClass *k, void *data) | |
654 | { | |
ce2918cb | 655 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
f224d35b DG |
656 | |
657 | drck->dr_entity_sense = logical_entity_sense; | |
0dfabd39 DG |
658 | drck->isolate = drc_isolate_logical; |
659 | drck->unisolate = drc_unisolate_logical; | |
9d4c0f4f DG |
660 | drck->ready_state = SPAPR_DRC_STATE_LOGICAL_CONFIGURED; |
661 | drck->empty_state = SPAPR_DRC_STATE_LOGICAL_UNUSABLE; | |
f224d35b DG |
662 | } |
663 | ||
2d335818 DG |
664 | static void spapr_drc_cpu_class_init(ObjectClass *k, void *data) |
665 | { | |
ce2918cb | 666 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
2d335818 DG |
667 | |
668 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_CPU; | |
1693ea16 | 669 | drck->typename = "CPU"; |
79808336 | 670 | drck->drc_name_prefix = "CPU "; |
6b762f29 | 671 | drck->release = spapr_core_release; |
345b12b9 | 672 | drck->dt_populate = spapr_core_dt_populate; |
2d335818 DG |
673 | } |
674 | ||
675 | static void spapr_drc_pci_class_init(ObjectClass *k, void *data) | |
676 | { | |
ce2918cb | 677 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
2d335818 DG |
678 | |
679 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PCI; | |
1693ea16 | 680 | drck->typename = "28"; |
79808336 | 681 | drck->drc_name_prefix = "C"; |
6b762f29 | 682 | drck->release = spapr_phb_remove_pci_device_cb; |
46fd0299 | 683 | drck->dt_populate = spapr_pci_dt_populate; |
2d335818 DG |
684 | } |
685 | ||
686 | static void spapr_drc_lmb_class_init(ObjectClass *k, void *data) | |
687 | { | |
ce2918cb | 688 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
2d335818 DG |
689 | |
690 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_LMB; | |
1693ea16 | 691 | drck->typename = "MEM"; |
79808336 | 692 | drck->drc_name_prefix = "LMB "; |
6b762f29 | 693 | drck->release = spapr_lmb_release; |
62d38c9b | 694 | drck->dt_populate = spapr_lmb_dt_populate; |
2d335818 DG |
695 | } |
696 | ||
962b6c36 MR |
697 | static void spapr_drc_phb_class_init(ObjectClass *k, void *data) |
698 | { | |
ce2918cb | 699 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); |
962b6c36 MR |
700 | |
701 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PHB; | |
702 | drck->typename = "PHB"; | |
703 | drck->drc_name_prefix = "PHB "; | |
bb2bdd81 GK |
704 | drck->release = spapr_phb_release; |
705 | drck->dt_populate = spapr_phb_dt_populate; | |
962b6c36 MR |
706 | } |
707 | ||
ee3a71e3 SB |
708 | static void spapr_drc_pmem_class_init(ObjectClass *k, void *data) |
709 | { | |
710 | SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_CLASS(k); | |
711 | ||
712 | drck->typeshift = SPAPR_DR_CONNECTOR_TYPE_SHIFT_PMEM; | |
713 | drck->typename = "PMEM"; | |
714 | drck->drc_name_prefix = "PMEM "; | |
715 | drck->release = NULL; | |
716 | drck->dt_populate = spapr_pmem_dt_populate; | |
717 | } | |
718 | ||
bbf5c878 MR |
719 | static const TypeInfo spapr_dr_connector_info = { |
720 | .name = TYPE_SPAPR_DR_CONNECTOR, | |
721 | .parent = TYPE_DEVICE, | |
ce2918cb | 722 | .instance_size = sizeof(SpaprDrc), |
bbf5c878 | 723 | .instance_init = spapr_dr_connector_instance_init, |
ce2918cb | 724 | .class_size = sizeof(SpaprDrcClass), |
bbf5c878 | 725 | .class_init = spapr_dr_connector_class_init, |
2d335818 DG |
726 | .abstract = true, |
727 | }; | |
728 | ||
729 | static const TypeInfo spapr_drc_physical_info = { | |
730 | .name = TYPE_SPAPR_DRC_PHYSICAL, | |
731 | .parent = TYPE_SPAPR_DR_CONNECTOR, | |
ce2918cb | 732 | .instance_size = sizeof(SpaprDrcPhysical), |
f224d35b | 733 | .class_init = spapr_drc_physical_class_init, |
2d335818 DG |
734 | .abstract = true, |
735 | }; | |
736 | ||
737 | static const TypeInfo spapr_drc_logical_info = { | |
738 | .name = TYPE_SPAPR_DRC_LOGICAL, | |
739 | .parent = TYPE_SPAPR_DR_CONNECTOR, | |
f224d35b | 740 | .class_init = spapr_drc_logical_class_init, |
2d335818 DG |
741 | .abstract = true, |
742 | }; | |
743 | ||
744 | static const TypeInfo spapr_drc_cpu_info = { | |
745 | .name = TYPE_SPAPR_DRC_CPU, | |
746 | .parent = TYPE_SPAPR_DRC_LOGICAL, | |
2d335818 DG |
747 | .class_init = spapr_drc_cpu_class_init, |
748 | }; | |
749 | ||
750 | static const TypeInfo spapr_drc_pci_info = { | |
751 | .name = TYPE_SPAPR_DRC_PCI, | |
752 | .parent = TYPE_SPAPR_DRC_PHYSICAL, | |
2d335818 DG |
753 | .class_init = spapr_drc_pci_class_init, |
754 | }; | |
755 | ||
756 | static const TypeInfo spapr_drc_lmb_info = { | |
757 | .name = TYPE_SPAPR_DRC_LMB, | |
758 | .parent = TYPE_SPAPR_DRC_LOGICAL, | |
2d335818 | 759 | .class_init = spapr_drc_lmb_class_init, |
bbf5c878 MR |
760 | }; |
761 | ||
962b6c36 MR |
762 | static const TypeInfo spapr_drc_phb_info = { |
763 | .name = TYPE_SPAPR_DRC_PHB, | |
764 | .parent = TYPE_SPAPR_DRC_LOGICAL, | |
ce2918cb | 765 | .instance_size = sizeof(SpaprDrc), |
962b6c36 MR |
766 | .class_init = spapr_drc_phb_class_init, |
767 | }; | |
768 | ||
ee3a71e3 SB |
769 | static const TypeInfo spapr_drc_pmem_info = { |
770 | .name = TYPE_SPAPR_DRC_PMEM, | |
771 | .parent = TYPE_SPAPR_DRC_LOGICAL, | |
772 | .class_init = spapr_drc_pmem_class_init, | |
773 | }; | |
774 | ||
bbf5c878 MR |
775 | /* helper functions for external users */ |
776 | ||
ce2918cb | 777 | SpaprDrc *spapr_drc_by_index(uint32_t index) |
bbf5c878 MR |
778 | { |
779 | Object *obj; | |
f5babeac | 780 | gchar *name; |
bbf5c878 | 781 | |
f5babeac | 782 | name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH, index); |
bbf5c878 | 783 | obj = object_resolve_path(name, NULL); |
f5babeac | 784 | g_free(name); |
bbf5c878 MR |
785 | |
786 | return !obj ? NULL : SPAPR_DR_CONNECTOR(obj); | |
787 | } | |
788 | ||
ce2918cb | 789 | SpaprDrc *spapr_drc_by_id(const char *type, uint32_t id) |
bbf5c878 | 790 | { |
ce2918cb | 791 | SpaprDrcClass *drck |
fbf55397 DG |
792 | = SPAPR_DR_CONNECTOR_CLASS(object_class_by_name(type)); |
793 | ||
794 | return spapr_drc_by_index(drck->typeshift << DRC_INDEX_TYPE_SHIFT | |
795 | | (id & DRC_INDEX_ID_MASK)); | |
bbf5c878 | 796 | } |
e4b798bb | 797 | |
e4b798bb | 798 | /** |
9e7d38e8 | 799 | * spapr_dt_drc |
e4b798bb MR |
800 | * |
801 | * @fdt: libfdt device tree | |
802 | * @path: path in the DT to generate properties | |
803 | * @owner: parent Object/DeviceState for which to generate DRC | |
804 | * descriptions for | |
ce2918cb | 805 | * @drc_type_mask: mask of SpaprDrcType values corresponding |
e4b798bb MR |
806 | * to the types of DRCs to generate entries for |
807 | * | |
808 | * generate OF properties to describe DRC topology/indices to guests | |
809 | * | |
810 | * as documented in PAPR+ v2.1, 13.5.2 | |
811 | */ | |
9e7d38e8 | 812 | int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask) |
e4b798bb MR |
813 | { |
814 | Object *root_container; | |
815 | ObjectProperty *prop; | |
7746abd8 | 816 | ObjectPropertyIterator iter; |
e4b798bb MR |
817 | uint32_t drc_count = 0; |
818 | GArray *drc_indexes, *drc_power_domains; | |
819 | GString *drc_names, *drc_types; | |
820 | int ret; | |
821 | ||
776e887f GK |
822 | /* |
823 | * This should really be only called once per node since it overwrites | |
824 | * the OF properties if they already exist. | |
825 | */ | |
826 | g_assert(!fdt_get_property(fdt, offset, "ibm,drc-indexes", NULL)); | |
827 | ||
e4b798bb MR |
828 | /* the first entry of each properties is a 32-bit integer encoding |
829 | * the number of elements in the array. we won't know this until | |
830 | * we complete the iteration through all the matching DRCs, but | |
831 | * reserve the space now and set the offsets accordingly so we | |
832 | * can fill them in later. | |
833 | */ | |
834 | drc_indexes = g_array_new(false, true, sizeof(uint32_t)); | |
835 | drc_indexes = g_array_set_size(drc_indexes, 1); | |
836 | drc_power_domains = g_array_new(false, true, sizeof(uint32_t)); | |
837 | drc_power_domains = g_array_set_size(drc_power_domains, 1); | |
838 | drc_names = g_string_set_size(g_string_new(NULL), sizeof(uint32_t)); | |
839 | drc_types = g_string_set_size(g_string_new(NULL), sizeof(uint32_t)); | |
840 | ||
841 | /* aliases for all DRConnector objects will be rooted in QOM | |
842 | * composition tree at DRC_CONTAINER_PATH | |
843 | */ | |
844 | root_container = container_get(object_get_root(), DRC_CONTAINER_PATH); | |
845 | ||
7746abd8 DB |
846 | object_property_iter_init(&iter, root_container); |
847 | while ((prop = object_property_iter_next(&iter))) { | |
e4b798bb | 848 | Object *obj; |
ce2918cb DG |
849 | SpaprDrc *drc; |
850 | SpaprDrcClass *drck; | |
dbd26f2f | 851 | char *drc_name = NULL; |
e4b798bb MR |
852 | uint32_t drc_index, drc_power_domain; |
853 | ||
854 | if (!strstart(prop->type, "link<", NULL)) { | |
855 | continue; | |
856 | } | |
857 | ||
552d7f49 MA |
858 | obj = object_property_get_link(root_container, prop->name, |
859 | &error_abort); | |
e4b798bb MR |
860 | drc = SPAPR_DR_CONNECTOR(obj); |
861 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
862 | ||
863 | if (owner && (drc->owner != owner)) { | |
864 | continue; | |
865 | } | |
866 | ||
2d335818 | 867 | if ((spapr_drc_type(drc) & drc_type_mask) == 0) { |
e4b798bb MR |
868 | continue; |
869 | } | |
870 | ||
871 | drc_count++; | |
872 | ||
873 | /* ibm,drc-indexes */ | |
0b55aa91 | 874 | drc_index = cpu_to_be32(spapr_drc_index(drc)); |
e4b798bb MR |
875 | g_array_append_val(drc_indexes, drc_index); |
876 | ||
877 | /* ibm,drc-power-domains */ | |
878 | drc_power_domain = cpu_to_be32(-1); | |
879 | g_array_append_val(drc_power_domains, drc_power_domain); | |
880 | ||
881 | /* ibm,drc-names */ | |
dbd26f2f SB |
882 | drc_name = spapr_drc_name(drc); |
883 | drc_names = g_string_append(drc_names, drc_name); | |
e4b798bb | 884 | drc_names = g_string_insert_len(drc_names, -1, "\0", 1); |
dbd26f2f | 885 | g_free(drc_name); |
e4b798bb MR |
886 | |
887 | /* ibm,drc-types */ | |
1693ea16 | 888 | drc_types = g_string_append(drc_types, drck->typename); |
e4b798bb MR |
889 | drc_types = g_string_insert_len(drc_types, -1, "\0", 1); |
890 | } | |
891 | ||
892 | /* now write the drc count into the space we reserved at the | |
893 | * beginning of the arrays previously | |
894 | */ | |
895 | *(uint32_t *)drc_indexes->data = cpu_to_be32(drc_count); | |
896 | *(uint32_t *)drc_power_domains->data = cpu_to_be32(drc_count); | |
897 | *(uint32_t *)drc_names->str = cpu_to_be32(drc_count); | |
898 | *(uint32_t *)drc_types->str = cpu_to_be32(drc_count); | |
899 | ||
9e7d38e8 | 900 | ret = fdt_setprop(fdt, offset, "ibm,drc-indexes", |
e4b798bb MR |
901 | drc_indexes->data, |
902 | drc_indexes->len * sizeof(uint32_t)); | |
903 | if (ret) { | |
ce9863b7 | 904 | error_report("Couldn't create ibm,drc-indexes property"); |
e4b798bb MR |
905 | goto out; |
906 | } | |
907 | ||
9e7d38e8 | 908 | ret = fdt_setprop(fdt, offset, "ibm,drc-power-domains", |
e4b798bb MR |
909 | drc_power_domains->data, |
910 | drc_power_domains->len * sizeof(uint32_t)); | |
911 | if (ret) { | |
ce9863b7 | 912 | error_report("Couldn't finalize ibm,drc-power-domains property"); |
e4b798bb MR |
913 | goto out; |
914 | } | |
915 | ||
9e7d38e8 | 916 | ret = fdt_setprop(fdt, offset, "ibm,drc-names", |
e4b798bb MR |
917 | drc_names->str, drc_names->len); |
918 | if (ret) { | |
ce9863b7 | 919 | error_report("Couldn't finalize ibm,drc-names property"); |
e4b798bb MR |
920 | goto out; |
921 | } | |
922 | ||
9e7d38e8 | 923 | ret = fdt_setprop(fdt, offset, "ibm,drc-types", |
e4b798bb MR |
924 | drc_types->str, drc_types->len); |
925 | if (ret) { | |
ce9863b7 | 926 | error_report("Couldn't finalize ibm,drc-types property"); |
e4b798bb MR |
927 | goto out; |
928 | } | |
929 | ||
930 | out: | |
931 | g_array_free(drc_indexes, true); | |
932 | g_array_free(drc_power_domains, true); | |
933 | g_string_free(drc_names, true); | |
934 | g_string_free(drc_types, true); | |
935 | ||
936 | return ret; | |
937 | } | |
b89b3d39 | 938 | |
babb819f GK |
939 | void spapr_drc_reset_all(SpaprMachineState *spapr) |
940 | { | |
941 | Object *drc_container; | |
942 | ObjectProperty *prop; | |
943 | ObjectPropertyIterator iter; | |
944 | ||
945 | drc_container = container_get(object_get_root(), DRC_CONTAINER_PATH); | |
946 | restart: | |
947 | object_property_iter_init(&iter, drc_container); | |
948 | while ((prop = object_property_iter_next(&iter))) { | |
949 | SpaprDrc *drc; | |
950 | ||
951 | if (!strstart(prop->type, "link<", NULL)) { | |
952 | continue; | |
953 | } | |
954 | drc = SPAPR_DR_CONNECTOR(object_property_get_link(drc_container, | |
955 | prop->name, | |
956 | &error_abort)); | |
957 | ||
958 | /* | |
959 | * This will complete any pending plug/unplug requests. | |
960 | * In case of a unplugged PHB or PCI bridge, this will | |
961 | * cause some DRCs to be destroyed and thus potentially | |
962 | * invalidate the iterator. | |
963 | */ | |
964 | if (spapr_drc_reset(drc)) { | |
965 | goto restart; | |
966 | } | |
967 | } | |
968 | } | |
969 | ||
b89b3d39 DG |
970 | /* |
971 | * RTAS calls | |
972 | */ | |
973 | ||
7b7258f8 | 974 | static uint32_t rtas_set_isolation_state(uint32_t idx, uint32_t state) |
b89b3d39 | 975 | { |
ce2918cb DG |
976 | SpaprDrc *drc = spapr_drc_by_index(idx); |
977 | SpaprDrcClass *drck; | |
7b7258f8 DG |
978 | |
979 | if (!drc) { | |
0dfabd39 | 980 | return RTAS_OUT_NO_SUCH_INDICATOR; |
b89b3d39 DG |
981 | } |
982 | ||
0dfabd39 DG |
983 | trace_spapr_drc_set_isolation_state(spapr_drc_index(drc), state); |
984 | ||
7b7258f8 | 985 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
0dfabd39 DG |
986 | |
987 | switch (state) { | |
988 | case SPAPR_DR_ISOLATION_STATE_ISOLATED: | |
989 | return drck->isolate(drc); | |
990 | ||
991 | case SPAPR_DR_ISOLATION_STATE_UNISOLATED: | |
992 | return drck->unisolate(drc); | |
993 | ||
994 | default: | |
995 | return RTAS_OUT_PARAM_ERROR; | |
996 | } | |
b89b3d39 DG |
997 | } |
998 | ||
7b7258f8 | 999 | static uint32_t rtas_set_allocation_state(uint32_t idx, uint32_t state) |
b89b3d39 | 1000 | { |
ce2918cb | 1001 | SpaprDrc *drc = spapr_drc_by_index(idx); |
b89b3d39 | 1002 | |
61736732 DG |
1003 | if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_LOGICAL)) { |
1004 | return RTAS_OUT_NO_SUCH_INDICATOR; | |
b89b3d39 DG |
1005 | } |
1006 | ||
61736732 DG |
1007 | trace_spapr_drc_set_allocation_state(spapr_drc_index(drc), state); |
1008 | ||
1009 | switch (state) { | |
1010 | case SPAPR_DR_ALLOCATION_STATE_USABLE: | |
1011 | return drc_set_usable(drc); | |
1012 | ||
1013 | case SPAPR_DR_ALLOCATION_STATE_UNUSABLE: | |
1014 | return drc_set_unusable(drc); | |
1015 | ||
1016 | default: | |
1017 | return RTAS_OUT_PARAM_ERROR; | |
1018 | } | |
7b7258f8 | 1019 | } |
b89b3d39 | 1020 | |
cd74d27e | 1021 | static uint32_t rtas_set_dr_indicator(uint32_t idx, uint32_t state) |
7b7258f8 | 1022 | { |
ce2918cb | 1023 | SpaprDrc *drc = spapr_drc_by_index(idx); |
b89b3d39 | 1024 | |
67fea71b DG |
1025 | if (!drc || !object_dynamic_cast(OBJECT(drc), TYPE_SPAPR_DRC_PHYSICAL)) { |
1026 | return RTAS_OUT_NO_SUCH_INDICATOR; | |
1027 | } | |
1028 | if ((state != SPAPR_DR_INDICATOR_INACTIVE) | |
1029 | && (state != SPAPR_DR_INDICATOR_ACTIVE) | |
1030 | && (state != SPAPR_DR_INDICATOR_IDENTIFY) | |
1031 | && (state != SPAPR_DR_INDICATOR_ACTION)) { | |
1032 | return RTAS_OUT_PARAM_ERROR; /* bad state parameter */ | |
7b7258f8 DG |
1033 | } |
1034 | ||
cd74d27e | 1035 | trace_spapr_drc_set_dr_indicator(idx, state); |
67fea71b | 1036 | SPAPR_DRC_PHYSICAL(drc)->dr_indicator = state; |
cd74d27e | 1037 | return RTAS_OUT_SUCCESS; |
7b7258f8 DG |
1038 | } |
1039 | ||
ce2918cb | 1040 | static void rtas_set_indicator(PowerPCCPU *cpu, SpaprMachineState *spapr, |
7b7258f8 DG |
1041 | uint32_t token, |
1042 | uint32_t nargs, target_ulong args, | |
1043 | uint32_t nret, target_ulong rets) | |
1044 | { | |
1045 | uint32_t type, idx, state; | |
1046 | uint32_t ret = RTAS_OUT_SUCCESS; | |
1047 | ||
1048 | if (nargs != 3 || nret != 1) { | |
b89b3d39 DG |
1049 | ret = RTAS_OUT_PARAM_ERROR; |
1050 | goto out; | |
1051 | } | |
b89b3d39 | 1052 | |
7b7258f8 DG |
1053 | type = rtas_ld(args, 0); |
1054 | idx = rtas_ld(args, 1); | |
1055 | state = rtas_ld(args, 2); | |
1056 | ||
1057 | switch (type) { | |
b89b3d39 | 1058 | case RTAS_SENSOR_TYPE_ISOLATION_STATE: |
7b7258f8 | 1059 | ret = rtas_set_isolation_state(idx, state); |
b89b3d39 DG |
1060 | break; |
1061 | case RTAS_SENSOR_TYPE_DR: | |
cd74d27e | 1062 | ret = rtas_set_dr_indicator(idx, state); |
b89b3d39 DG |
1063 | break; |
1064 | case RTAS_SENSOR_TYPE_ALLOCATION_STATE: | |
7b7258f8 | 1065 | ret = rtas_set_allocation_state(idx, state); |
b89b3d39 DG |
1066 | break; |
1067 | default: | |
7b7258f8 | 1068 | ret = RTAS_OUT_NOT_SUPPORTED; |
b89b3d39 DG |
1069 | } |
1070 | ||
1071 | out: | |
1072 | rtas_st(rets, 0, ret); | |
b89b3d39 DG |
1073 | } |
1074 | ||
ce2918cb | 1075 | static void rtas_get_sensor_state(PowerPCCPU *cpu, SpaprMachineState *spapr, |
b89b3d39 DG |
1076 | uint32_t token, uint32_t nargs, |
1077 | target_ulong args, uint32_t nret, | |
1078 | target_ulong rets) | |
1079 | { | |
1080 | uint32_t sensor_type; | |
1081 | uint32_t sensor_index; | |
1082 | uint32_t sensor_state = 0; | |
ce2918cb DG |
1083 | SpaprDrc *drc; |
1084 | SpaprDrcClass *drck; | |
b89b3d39 DG |
1085 | uint32_t ret = RTAS_OUT_SUCCESS; |
1086 | ||
1087 | if (nargs != 2 || nret != 2) { | |
1088 | ret = RTAS_OUT_PARAM_ERROR; | |
1089 | goto out; | |
1090 | } | |
1091 | ||
1092 | sensor_type = rtas_ld(args, 0); | |
1093 | sensor_index = rtas_ld(args, 1); | |
1094 | ||
1095 | if (sensor_type != RTAS_SENSOR_TYPE_ENTITY_SENSE) { | |
1096 | /* currently only DR-related sensors are implemented */ | |
1097 | trace_spapr_rtas_get_sensor_state_not_supported(sensor_index, | |
1098 | sensor_type); | |
1099 | ret = RTAS_OUT_NOT_SUPPORTED; | |
1100 | goto out; | |
1101 | } | |
1102 | ||
fbf55397 | 1103 | drc = spapr_drc_by_index(sensor_index); |
b89b3d39 DG |
1104 | if (!drc) { |
1105 | trace_spapr_rtas_get_sensor_state_invalid(sensor_index); | |
1106 | ret = RTAS_OUT_PARAM_ERROR; | |
1107 | goto out; | |
1108 | } | |
1109 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); | |
f224d35b | 1110 | sensor_state = drck->dr_entity_sense(drc); |
b89b3d39 DG |
1111 | |
1112 | out: | |
1113 | rtas_st(rets, 0, ret); | |
1114 | rtas_st(rets, 1, sensor_state); | |
1115 | } | |
1116 | ||
1117 | /* configure-connector work area offsets, int32_t units for field | |
1118 | * indexes, bytes for field offset/len values. | |
1119 | * | |
1120 | * as documented by PAPR+ v2.7, 13.5.3.5 | |
1121 | */ | |
1122 | #define CC_IDX_NODE_NAME_OFFSET 2 | |
1123 | #define CC_IDX_PROP_NAME_OFFSET 2 | |
1124 | #define CC_IDX_PROP_LEN 3 | |
1125 | #define CC_IDX_PROP_DATA_OFFSET 4 | |
1126 | #define CC_VAL_DATA_OFFSET ((CC_IDX_PROP_DATA_OFFSET + 1) * 4) | |
1127 | #define CC_WA_LEN 4096 | |
1128 | ||
1129 | static void configure_connector_st(target_ulong addr, target_ulong offset, | |
1130 | const void *buf, size_t len) | |
1131 | { | |
1132 | cpu_physical_memory_write(ppc64_phys_to_real(addr + offset), | |
1133 | buf, MIN(len, CC_WA_LEN - offset)); | |
1134 | } | |
1135 | ||
b89b3d39 | 1136 | static void rtas_ibm_configure_connector(PowerPCCPU *cpu, |
ce2918cb | 1137 | SpaprMachineState *spapr, |
b89b3d39 DG |
1138 | uint32_t token, uint32_t nargs, |
1139 | target_ulong args, uint32_t nret, | |
1140 | target_ulong rets) | |
1141 | { | |
1142 | uint64_t wa_addr; | |
1143 | uint64_t wa_offset; | |
1144 | uint32_t drc_index; | |
ce2918cb DG |
1145 | SpaprDrc *drc; |
1146 | SpaprDrcClass *drck; | |
1147 | SpaprDRCCResponse resp = SPAPR_DR_CC_RESPONSE_CONTINUE; | |
b89b3d39 | 1148 | int rc; |
b89b3d39 DG |
1149 | |
1150 | if (nargs != 2 || nret != 1) { | |
1151 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
1152 | return; | |
1153 | } | |
1154 | ||
1155 | wa_addr = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 0); | |
1156 | ||
1157 | drc_index = rtas_ld(wa_addr, 0); | |
fbf55397 | 1158 | drc = spapr_drc_by_index(drc_index); |
b89b3d39 DG |
1159 | if (!drc) { |
1160 | trace_spapr_rtas_ibm_configure_connector_invalid(drc_index); | |
1161 | rc = RTAS_OUT_PARAM_ERROR; | |
1162 | goto out; | |
1163 | } | |
1164 | ||
9d4c0f4f | 1165 | if ((drc->state != SPAPR_DRC_STATE_LOGICAL_UNISOLATE) |
188bfe1b BR |
1166 | && (drc->state != SPAPR_DRC_STATE_PHYSICAL_UNISOLATE) |
1167 | && (drc->state != SPAPR_DRC_STATE_LOGICAL_CONFIGURED) | |
1168 | && (drc->state != SPAPR_DRC_STATE_PHYSICAL_CONFIGURED)) { | |
1169 | /* | |
1170 | * Need to unisolate the device before configuring | |
1171 | * or it should already be in configured state to | |
1172 | * allow configure-connector be called repeatedly. | |
1173 | */ | |
b89b3d39 DG |
1174 | rc = SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE; |
1175 | goto out; | |
1176 | } | |
1177 | ||
9d4c0f4f DG |
1178 | drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); |
1179 | ||
fe1831ef DHB |
1180 | /* |
1181 | * This indicates that the kernel is reconfiguring a LMB due to | |
eb7f80fd | 1182 | * a failed hotunplug. Rollback the DIMM unplug process. |
fe1831ef DHB |
1183 | */ |
1184 | if (spapr_drc_type(drc) == SPAPR_DR_CONNECTOR_TYPE_LMB && | |
1185 | drc->unplug_requested) { | |
eb7f80fd | 1186 | spapr_memory_unplug_rollback(spapr, drc->dev); |
fe1831ef DHB |
1187 | } |
1188 | ||
d9c95c71 | 1189 | if (!drc->fdt) { |
d9c95c71 GK |
1190 | void *fdt; |
1191 | int fdt_size; | |
1192 | ||
1193 | fdt = create_device_tree(&fdt_size); | |
1194 | ||
1195 | if (drck->dt_populate(drc, spapr, fdt, &drc->fdt_start_offset, | |
9261ef5e | 1196 | NULL)) { |
d9c95c71 | 1197 | g_free(fdt); |
d9c95c71 GK |
1198 | rc = SPAPR_DR_CC_RESPONSE_ERROR; |
1199 | goto out; | |
1200 | } | |
1201 | ||
1202 | drc->fdt = fdt; | |
1203 | drc->ccs_offset = drc->fdt_start_offset; | |
1204 | drc->ccs_depth = 0; | |
1205 | } | |
1206 | ||
b89b3d39 DG |
1207 | do { |
1208 | uint32_t tag; | |
1209 | const char *name; | |
1210 | const struct fdt_property *prop; | |
1211 | int fdt_offset_next, prop_len; | |
1212 | ||
4445b1d2 | 1213 | tag = fdt_next_tag(drc->fdt, drc->ccs_offset, &fdt_offset_next); |
b89b3d39 DG |
1214 | |
1215 | switch (tag) { | |
1216 | case FDT_BEGIN_NODE: | |
4445b1d2 DG |
1217 | drc->ccs_depth++; |
1218 | name = fdt_get_name(drc->fdt, drc->ccs_offset, NULL); | |
b89b3d39 DG |
1219 | |
1220 | /* provide the name of the next OF node */ | |
1221 | wa_offset = CC_VAL_DATA_OFFSET; | |
1222 | rtas_st(wa_addr, CC_IDX_NODE_NAME_OFFSET, wa_offset); | |
1223 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); | |
1224 | resp = SPAPR_DR_CC_RESPONSE_NEXT_CHILD; | |
1225 | break; | |
1226 | case FDT_END_NODE: | |
4445b1d2 DG |
1227 | drc->ccs_depth--; |
1228 | if (drc->ccs_depth == 0) { | |
0b55aa91 | 1229 | uint32_t drc_index = spapr_drc_index(drc); |
9d4c0f4f DG |
1230 | |
1231 | /* done sending the device tree, move to configured state */ | |
0b55aa91 | 1232 | trace_spapr_drc_set_configured(drc_index); |
9d4c0f4f | 1233 | drc->state = drck->ready_state; |
188bfe1b BR |
1234 | /* |
1235 | * Ensure that we are able to send the FDT fragment | |
1236 | * again via configure-connector call if the guest requests. | |
1237 | */ | |
1238 | drc->ccs_offset = drc->fdt_start_offset; | |
1239 | drc->ccs_depth = 0; | |
1240 | fdt_offset_next = drc->fdt_start_offset; | |
b89b3d39 DG |
1241 | resp = SPAPR_DR_CC_RESPONSE_SUCCESS; |
1242 | } else { | |
1243 | resp = SPAPR_DR_CC_RESPONSE_PREV_PARENT; | |
1244 | } | |
1245 | break; | |
1246 | case FDT_PROP: | |
4445b1d2 | 1247 | prop = fdt_get_property_by_offset(drc->fdt, drc->ccs_offset, |
b89b3d39 | 1248 | &prop_len); |
88af6ea5 | 1249 | name = fdt_string(drc->fdt, fdt32_to_cpu(prop->nameoff)); |
b89b3d39 DG |
1250 | |
1251 | /* provide the name of the next OF property */ | |
1252 | wa_offset = CC_VAL_DATA_OFFSET; | |
1253 | rtas_st(wa_addr, CC_IDX_PROP_NAME_OFFSET, wa_offset); | |
1254 | configure_connector_st(wa_addr, wa_offset, name, strlen(name) + 1); | |
1255 | ||
1256 | /* provide the length and value of the OF property. data gets | |
1257 | * placed immediately after NULL terminator of the OF property's | |
1258 | * name string | |
1259 | */ | |
1260 | wa_offset += strlen(name) + 1, | |
1261 | rtas_st(wa_addr, CC_IDX_PROP_LEN, prop_len); | |
1262 | rtas_st(wa_addr, CC_IDX_PROP_DATA_OFFSET, wa_offset); | |
1263 | configure_connector_st(wa_addr, wa_offset, prop->data, prop_len); | |
1264 | resp = SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY; | |
1265 | break; | |
1266 | case FDT_END: | |
1267 | resp = SPAPR_DR_CC_RESPONSE_ERROR; | |
1268 | default: | |
1269 | /* keep seeking for an actionable tag */ | |
1270 | break; | |
1271 | } | |
4445b1d2 DG |
1272 | if (drc->ccs_offset >= 0) { |
1273 | drc->ccs_offset = fdt_offset_next; | |
b89b3d39 DG |
1274 | } |
1275 | } while (resp == SPAPR_DR_CC_RESPONSE_CONTINUE); | |
1276 | ||
1277 | rc = resp; | |
1278 | out: | |
1279 | rtas_st(rets, 0, rc); | |
1280 | } | |
1281 | ||
1282 | static void spapr_drc_register_types(void) | |
1283 | { | |
1284 | type_register_static(&spapr_dr_connector_info); | |
2d335818 DG |
1285 | type_register_static(&spapr_drc_physical_info); |
1286 | type_register_static(&spapr_drc_logical_info); | |
1287 | type_register_static(&spapr_drc_cpu_info); | |
1288 | type_register_static(&spapr_drc_pci_info); | |
1289 | type_register_static(&spapr_drc_lmb_info); | |
962b6c36 | 1290 | type_register_static(&spapr_drc_phb_info); |
ee3a71e3 | 1291 | type_register_static(&spapr_drc_pmem_info); |
b89b3d39 DG |
1292 | |
1293 | spapr_rtas_register(RTAS_SET_INDICATOR, "set-indicator", | |
1294 | rtas_set_indicator); | |
1295 | spapr_rtas_register(RTAS_GET_SENSOR_STATE, "get-sensor-state", | |
1296 | rtas_get_sensor_state); | |
1297 | spapr_rtas_register(RTAS_IBM_CONFIGURE_CONNECTOR, "ibm,configure-connector", | |
1298 | rtas_ibm_configure_connector); | |
1299 | } | |
1300 | type_init(spapr_drc_register_types) |