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Commit | Line | Data |
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9c17d615 | 1 | #include "sysemu/sysemu.h" |
9fdf0c29 | 2 | #include "cpu.h" |
9c17d615 | 3 | #include "sysemu/sysemu.h" |
ed120055 | 4 | #include "helper_regs.h" |
9fdf0c29 | 5 | #include "hw/spapr.h" |
d5aea6f3 | 6 | #include "mmu-hash64.h" |
f43e3525 | 7 | |
f43e3525 DG |
8 | static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, |
9 | target_ulong pte_index) | |
10 | { | |
11 | target_ulong rb, va_low; | |
12 | ||
13 | rb = (v & ~0x7fULL) << 16; /* AVA field */ | |
14 | va_low = pte_index >> 3; | |
d5aea6f3 | 15 | if (v & HPTE64_V_SECONDARY) { |
f43e3525 DG |
16 | va_low = ~va_low; |
17 | } | |
18 | /* xor vsid from AVA */ | |
d5aea6f3 | 19 | if (!(v & HPTE64_V_1TB_SEG)) { |
f43e3525 DG |
20 | va_low ^= v >> 12; |
21 | } else { | |
22 | va_low ^= v >> 24; | |
23 | } | |
24 | va_low &= 0x7ff; | |
d5aea6f3 | 25 | if (v & HPTE64_V_LARGE) { |
f43e3525 DG |
26 | rb |= 1; /* L field */ |
27 | #if 0 /* Disable that P7 specific bit for now */ | |
28 | if (r & 0xff000) { | |
29 | /* non-16MB large page, must be 64k */ | |
30 | /* (masks depend on page size) */ | |
31 | rb |= 0x1000; /* page encoding in LP field */ | |
32 | rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ | |
33 | rb |= (va_low & 0xfe); /* AVAL field */ | |
34 | } | |
35 | #endif | |
36 | } else { | |
37 | /* 4kB page */ | |
38 | rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ | |
39 | } | |
40 | rb |= (v >> 54) & 0x300; /* B field */ | |
41 | return rb; | |
42 | } | |
43 | ||
b13ce26d | 44 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
f43e3525 DG |
45 | target_ulong opcode, target_ulong *args) |
46 | { | |
b13ce26d | 47 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
48 | target_ulong flags = args[0]; |
49 | target_ulong pte_index = args[1]; | |
50 | target_ulong pteh = args[2]; | |
51 | target_ulong ptel = args[3]; | |
f73a2575 DG |
52 | target_ulong page_shift = 12; |
53 | target_ulong raddr; | |
1235a9cf | 54 | target_ulong i; |
dffdaf61 | 55 | hwaddr hpte; |
f43e3525 DG |
56 | |
57 | /* only handle 4k and 16M pages for now */ | |
d5aea6f3 | 58 | if (pteh & HPTE64_V_LARGE) { |
f43e3525 DG |
59 | #if 0 /* We don't support 64k pages yet */ |
60 | if ((ptel & 0xf000) == 0x1000) { | |
61 | /* 64k page */ | |
f43e3525 DG |
62 | } else |
63 | #endif | |
64 | if ((ptel & 0xff000) == 0) { | |
65 | /* 16M page */ | |
f73a2575 | 66 | page_shift = 24; |
f43e3525 DG |
67 | /* lowest AVA bit must be 0 for 16M pages */ |
68 | if (pteh & 0x80) { | |
69 | return H_PARAMETER; | |
70 | } | |
71 | } else { | |
72 | return H_PARAMETER; | |
73 | } | |
74 | } | |
75 | ||
d5aea6f3 | 76 | raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1); |
f43e3525 | 77 | |
f73a2575 DG |
78 | if (raddr < spapr->ram_limit) { |
79 | /* Regular RAM - should have WIMG=0010 */ | |
d5aea6f3 | 80 | if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { |
f73a2575 DG |
81 | return H_PARAMETER; |
82 | } | |
83 | } else { | |
84 | /* Looks like an IO address */ | |
85 | /* FIXME: What WIMG combinations could be sensible for IO? | |
86 | * For now we allow WIMG=010x, but are there others? */ | |
87 | /* FIXME: Should we check against registered IO addresses? */ | |
d5aea6f3 | 88 | if ((ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)) != HPTE64_R_I) { |
f73a2575 DG |
89 | return H_PARAMETER; |
90 | } | |
f43e3525 | 91 | } |
f73a2575 | 92 | |
f43e3525 DG |
93 | pteh &= ~0x60ULL; |
94 | ||
95 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
96 | return H_PARAMETER; | |
97 | } | |
98 | if (likely((flags & H_EXACT) == 0)) { | |
99 | pte_index &= ~7ULL; | |
dffdaf61 | 100 | hpte = pte_index * HASH_PTE_SIZE_64; |
f43e3525 DG |
101 | for (i = 0; ; ++i) { |
102 | if (i == 8) { | |
103 | return H_PTEG_FULL; | |
104 | } | |
dffdaf61 | 105 | if ((ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) == 0) { |
f43e3525 DG |
106 | break; |
107 | } | |
108 | hpte += HASH_PTE_SIZE_64; | |
109 | } | |
110 | } else { | |
111 | i = 0; | |
dffdaf61 DG |
112 | hpte = pte_index * HASH_PTE_SIZE_64; |
113 | if (ppc_hash64_load_hpte0(env, hpte) & HPTE64_V_VALID) { | |
f43e3525 DG |
114 | return H_PTEG_FULL; |
115 | } | |
116 | } | |
dffdaf61 | 117 | ppc_hash64_store_hpte1(env, hpte, ptel); |
f43e3525 | 118 | /* eieio(); FIXME: need some sort of barrier for smp? */ |
dffdaf61 | 119 | ppc_hash64_store_hpte0(env, hpte, pteh); |
f43e3525 | 120 | |
f43e3525 DG |
121 | args[0] = pte_index + i; |
122 | return H_SUCCESS; | |
123 | } | |
124 | ||
a3d0abae DG |
125 | enum { |
126 | REMOVE_SUCCESS = 0, | |
127 | REMOVE_NOT_FOUND = 1, | |
128 | REMOVE_PARM = 2, | |
129 | REMOVE_HW = 3, | |
130 | }; | |
131 | ||
e2684c0b | 132 | static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex, |
a3d0abae DG |
133 | target_ulong avpn, |
134 | target_ulong flags, | |
135 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 136 | { |
dffdaf61 | 137 | hwaddr hpte; |
f43e3525 DG |
138 | target_ulong v, r, rb; |
139 | ||
a3d0abae DG |
140 | if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) { |
141 | return REMOVE_PARM; | |
f43e3525 DG |
142 | } |
143 | ||
dffdaf61 | 144 | hpte = ptex * HASH_PTE_SIZE_64; |
f43e3525 | 145 | |
dffdaf61 DG |
146 | v = ppc_hash64_load_hpte0(env, hpte); |
147 | r = ppc_hash64_load_hpte1(env, hpte); | |
f43e3525 | 148 | |
d5aea6f3 | 149 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 DG |
150 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || |
151 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 152 | return REMOVE_NOT_FOUND; |
f43e3525 | 153 | } |
35f9304d | 154 | *vp = v; |
a3d0abae | 155 | *rp = r; |
dffdaf61 | 156 | ppc_hash64_store_hpte0(env, hpte, 0); |
a3d0abae | 157 | rb = compute_tlbie_rb(v, r, ptex); |
f43e3525 | 158 | ppc_tlb_invalidate_one(env, rb); |
a3d0abae DG |
159 | return REMOVE_SUCCESS; |
160 | } | |
161 | ||
b13ce26d | 162 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
a3d0abae DG |
163 | target_ulong opcode, target_ulong *args) |
164 | { | |
b13ce26d | 165 | CPUPPCState *env = &cpu->env; |
a3d0abae DG |
166 | target_ulong flags = args[0]; |
167 | target_ulong pte_index = args[1]; | |
168 | target_ulong avpn = args[2]; | |
169 | int ret; | |
170 | ||
171 | ret = remove_hpte(env, pte_index, avpn, flags, | |
172 | &args[0], &args[1]); | |
173 | ||
174 | switch (ret) { | |
175 | case REMOVE_SUCCESS: | |
176 | return H_SUCCESS; | |
177 | ||
178 | case REMOVE_NOT_FOUND: | |
179 | return H_NOT_FOUND; | |
180 | ||
181 | case REMOVE_PARM: | |
182 | return H_PARAMETER; | |
183 | ||
184 | case REMOVE_HW: | |
185 | return H_HARDWARE; | |
186 | } | |
187 | ||
188 | assert(0); | |
189 | } | |
190 | ||
191 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
192 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
193 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
194 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
195 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
196 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
197 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
198 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
199 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
200 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
201 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
202 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
203 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
204 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
205 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
206 | ||
207 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
208 | ||
b13ce26d | 209 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
a3d0abae DG |
210 | target_ulong opcode, target_ulong *args) |
211 | { | |
b13ce26d | 212 | CPUPPCState *env = &cpu->env; |
a3d0abae DG |
213 | int i; |
214 | ||
215 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
216 | target_ulong *tsh = &args[i*2]; | |
217 | target_ulong tsl = args[i*2 + 1]; | |
218 | target_ulong v, r, ret; | |
219 | ||
220 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
221 | break; | |
222 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
223 | return H_PARAMETER; | |
224 | } | |
225 | ||
226 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
227 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
228 | ||
229 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
230 | *tsh |= H_BULK_REMOVE_PARM; | |
231 | return H_PARAMETER; | |
232 | } | |
233 | ||
234 | ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, | |
235 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, | |
236 | &v, &r); | |
237 | ||
238 | *tsh |= ret << 60; | |
239 | ||
240 | switch (ret) { | |
241 | case REMOVE_SUCCESS: | |
d5aea6f3 | 242 | *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; |
a3d0abae DG |
243 | break; |
244 | ||
245 | case REMOVE_PARM: | |
246 | return H_PARAMETER; | |
247 | ||
248 | case REMOVE_HW: | |
249 | return H_HARDWARE; | |
250 | } | |
251 | } | |
252 | ||
f43e3525 DG |
253 | return H_SUCCESS; |
254 | } | |
255 | ||
b13ce26d | 256 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
f43e3525 DG |
257 | target_ulong opcode, target_ulong *args) |
258 | { | |
b13ce26d | 259 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
260 | target_ulong flags = args[0]; |
261 | target_ulong pte_index = args[1]; | |
262 | target_ulong avpn = args[2]; | |
dffdaf61 | 263 | hwaddr hpte; |
f43e3525 DG |
264 | target_ulong v, r, rb; |
265 | ||
266 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
267 | return H_PARAMETER; | |
268 | } | |
269 | ||
dffdaf61 | 270 | hpte = pte_index * HASH_PTE_SIZE_64; |
f43e3525 | 271 | |
dffdaf61 DG |
272 | v = ppc_hash64_load_hpte0(env, hpte); |
273 | r = ppc_hash64_load_hpte1(env, hpte); | |
f43e3525 | 274 | |
d5aea6f3 | 275 | if ((v & HPTE64_V_VALID) == 0 || |
f43e3525 | 276 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { |
f43e3525 DG |
277 | return H_NOT_FOUND; |
278 | } | |
279 | ||
d5aea6f3 DG |
280 | r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | |
281 | HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); | |
282 | r |= (flags << 55) & HPTE64_R_PP0; | |
283 | r |= (flags << 48) & HPTE64_R_KEY_HI; | |
284 | r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); | |
f43e3525 | 285 | rb = compute_tlbie_rb(v, r, pte_index); |
dffdaf61 | 286 | ppc_hash64_store_hpte0(env, hpte, v & ~HPTE64_V_VALID); |
f43e3525 | 287 | ppc_tlb_invalidate_one(env, rb); |
dffdaf61 | 288 | ppc_hash64_store_hpte1(env, hpte, r); |
f43e3525 | 289 | /* Don't need a memory barrier, due to qemu's global lock */ |
dffdaf61 | 290 | ppc_hash64_store_hpte0(env, hpte, v); |
f43e3525 DG |
291 | return H_SUCCESS; |
292 | } | |
293 | ||
6bbd5dde EC |
294 | static target_ulong h_read(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
295 | target_ulong opcode, target_ulong *args) | |
296 | { | |
297 | CPUPPCState *env = &cpu->env; | |
298 | target_ulong flags = args[0]; | |
299 | target_ulong pte_index = args[1]; | |
300 | uint8_t *hpte; | |
301 | int i, ridx, n_entries = 1; | |
302 | ||
303 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
304 | return H_PARAMETER; | |
305 | } | |
306 | ||
307 | if (flags & H_READ_4) { | |
308 | /* Clear the two low order bits */ | |
309 | pte_index &= ~(3ULL); | |
310 | n_entries = 4; | |
311 | } | |
312 | ||
313 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
314 | ||
315 | for (i = 0, ridx = 0; i < n_entries; i++) { | |
316 | args[ridx++] = ldq_p(hpte); | |
317 | args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
318 | hpte += HASH_PTE_SIZE_64; | |
319 | } | |
320 | ||
321 | return H_SUCCESS; | |
322 | } | |
323 | ||
b13ce26d | 324 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
821303f5 DG |
325 | target_ulong opcode, target_ulong *args) |
326 | { | |
327 | /* FIXME: actually implement this */ | |
328 | return H_HARDWARE; | |
329 | } | |
330 | ||
ed120055 DG |
331 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
332 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
333 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
334 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
335 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
336 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
337 | ||
338 | #define VPA_MIN_SIZE 640 | |
339 | #define VPA_SIZE_OFFSET 0x4 | |
340 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
341 | #define VPA_SHARED_PROC_VAL 0x2 | |
342 | ||
e2684c0b | 343 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 DG |
344 | { |
345 | uint16_t size; | |
346 | uint8_t tmp; | |
347 | ||
348 | if (vpa == 0) { | |
349 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
350 | return H_HARDWARE; | |
351 | } | |
352 | ||
353 | if (vpa % env->dcache_line_size) { | |
354 | return H_PARAMETER; | |
355 | } | |
356 | /* FIXME: bounds check the address */ | |
357 | ||
06c46bba | 358 | size = lduw_be_phys(vpa + 0x4); |
ed120055 DG |
359 | |
360 | if (size < VPA_MIN_SIZE) { | |
361 | return H_PARAMETER; | |
362 | } | |
363 | ||
364 | /* VPA is not allowed to cross a page boundary */ | |
365 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
366 | return H_PARAMETER; | |
367 | } | |
368 | ||
1bfb37d1 | 369 | env->vpa_addr = vpa; |
ed120055 | 370 | |
1bfb37d1 | 371 | tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 372 | tmp |= VPA_SHARED_PROC_VAL; |
1bfb37d1 | 373 | stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
374 | |
375 | return H_SUCCESS; | |
376 | } | |
377 | ||
e2684c0b | 378 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 379 | { |
1bfb37d1 | 380 | if (env->slb_shadow_addr) { |
ed120055 DG |
381 | return H_RESOURCE; |
382 | } | |
383 | ||
1bfb37d1 | 384 | if (env->dtl_addr) { |
ed120055 DG |
385 | return H_RESOURCE; |
386 | } | |
387 | ||
1bfb37d1 | 388 | env->vpa_addr = 0; |
ed120055 DG |
389 | return H_SUCCESS; |
390 | } | |
391 | ||
e2684c0b | 392 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 DG |
393 | { |
394 | uint32_t size; | |
395 | ||
396 | if (addr == 0) { | |
397 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
398 | return H_HARDWARE; | |
399 | } | |
400 | ||
06c46bba | 401 | size = ldl_be_phys(addr + 0x4); |
ed120055 DG |
402 | if (size < 0x8) { |
403 | return H_PARAMETER; | |
404 | } | |
405 | ||
406 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
407 | return H_PARAMETER; | |
408 | } | |
409 | ||
1bfb37d1 | 410 | if (!env->vpa_addr) { |
ed120055 DG |
411 | return H_RESOURCE; |
412 | } | |
413 | ||
1bfb37d1 DG |
414 | env->slb_shadow_addr = addr; |
415 | env->slb_shadow_size = size; | |
ed120055 DG |
416 | |
417 | return H_SUCCESS; | |
418 | } | |
419 | ||
e2684c0b | 420 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 421 | { |
1bfb37d1 DG |
422 | env->slb_shadow_addr = 0; |
423 | env->slb_shadow_size = 0; | |
ed120055 DG |
424 | return H_SUCCESS; |
425 | } | |
426 | ||
e2684c0b | 427 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 DG |
428 | { |
429 | uint32_t size; | |
430 | ||
431 | if (addr == 0) { | |
432 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
433 | return H_HARDWARE; | |
434 | } | |
435 | ||
06c46bba | 436 | size = ldl_be_phys(addr + 0x4); |
ed120055 DG |
437 | |
438 | if (size < 48) { | |
439 | return H_PARAMETER; | |
440 | } | |
441 | ||
1bfb37d1 | 442 | if (!env->vpa_addr) { |
ed120055 DG |
443 | return H_RESOURCE; |
444 | } | |
445 | ||
1bfb37d1 | 446 | env->dtl_addr = addr; |
ed120055 DG |
447 | env->dtl_size = size; |
448 | ||
449 | return H_SUCCESS; | |
450 | } | |
451 | ||
73f7821b | 452 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 453 | { |
1bfb37d1 | 454 | env->dtl_addr = 0; |
ed120055 DG |
455 | env->dtl_size = 0; |
456 | ||
457 | return H_SUCCESS; | |
458 | } | |
459 | ||
b13ce26d | 460 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
ed120055 DG |
461 | target_ulong opcode, target_ulong *args) |
462 | { | |
463 | target_ulong flags = args[0]; | |
464 | target_ulong procno = args[1]; | |
465 | target_ulong vpa = args[2]; | |
466 | target_ulong ret = H_PARAMETER; | |
e2684c0b | 467 | CPUPPCState *tenv; |
55e5c285 | 468 | CPUState *tcpu; |
ed120055 | 469 | |
5353d03d AF |
470 | tcpu = qemu_get_cpu(procno); |
471 | if (!tcpu) { | |
ed120055 DG |
472 | return H_PARAMETER; |
473 | } | |
5353d03d | 474 | tenv = tcpu->env_ptr; |
ed120055 DG |
475 | |
476 | switch (flags) { | |
477 | case FLAGS_REGISTER_VPA: | |
478 | ret = register_vpa(tenv, vpa); | |
479 | break; | |
480 | ||
481 | case FLAGS_DEREGISTER_VPA: | |
482 | ret = deregister_vpa(tenv, vpa); | |
483 | break; | |
484 | ||
485 | case FLAGS_REGISTER_SLBSHADOW: | |
486 | ret = register_slb_shadow(tenv, vpa); | |
487 | break; | |
488 | ||
489 | case FLAGS_DEREGISTER_SLBSHADOW: | |
490 | ret = deregister_slb_shadow(tenv, vpa); | |
491 | break; | |
492 | ||
493 | case FLAGS_REGISTER_DTL: | |
494 | ret = register_dtl(tenv, vpa); | |
495 | break; | |
496 | ||
497 | case FLAGS_DEREGISTER_DTL: | |
498 | ret = deregister_dtl(tenv, vpa); | |
499 | break; | |
500 | } | |
501 | ||
502 | return ret; | |
503 | } | |
504 | ||
b13ce26d | 505 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
ed120055 DG |
506 | target_ulong opcode, target_ulong *args) |
507 | { | |
b13ce26d | 508 | CPUPPCState *env = &cpu->env; |
fcd7d003 | 509 | CPUState *cs = CPU(cpu); |
b13ce26d | 510 | |
ed120055 DG |
511 | env->msr |= (1ULL << MSR_EE); |
512 | hreg_compute_hflags(env); | |
fcd7d003 | 513 | if (!cpu_has_work(cs)) { |
259186a7 | 514 | cs->halted = 1; |
1dd08894 | 515 | env->exception_index = EXCP_HLT; |
fcd7d003 | 516 | cs->exit_request = 1; |
ed120055 DG |
517 | } |
518 | return H_SUCCESS; | |
519 | } | |
520 | ||
b13ce26d | 521 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
39ac8455 DG |
522 | target_ulong opcode, target_ulong *args) |
523 | { | |
524 | target_ulong rtas_r3 = args[0]; | |
06c46bba AG |
525 | uint32_t token = ldl_be_phys(rtas_r3); |
526 | uint32_t nargs = ldl_be_phys(rtas_r3 + 4); | |
527 | uint32_t nret = ldl_be_phys(rtas_r3 + 8); | |
39ac8455 DG |
528 | |
529 | return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12, | |
530 | nret, rtas_r3 + 12 + 4*nargs); | |
531 | } | |
532 | ||
b13ce26d | 533 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
534 | target_ulong opcode, target_ulong *args) |
535 | { | |
536 | target_ulong size = args[0]; | |
537 | target_ulong addr = args[1]; | |
538 | ||
539 | switch (size) { | |
540 | case 1: | |
541 | args[0] = ldub_phys(addr); | |
542 | return H_SUCCESS; | |
543 | case 2: | |
544 | args[0] = lduw_phys(addr); | |
545 | return H_SUCCESS; | |
546 | case 4: | |
547 | args[0] = ldl_phys(addr); | |
548 | return H_SUCCESS; | |
549 | case 8: | |
550 | args[0] = ldq_phys(addr); | |
551 | return H_SUCCESS; | |
552 | } | |
553 | return H_PARAMETER; | |
554 | } | |
555 | ||
b13ce26d | 556 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
557 | target_ulong opcode, target_ulong *args) |
558 | { | |
559 | target_ulong size = args[0]; | |
560 | target_ulong addr = args[1]; | |
561 | target_ulong val = args[2]; | |
562 | ||
563 | switch (size) { | |
564 | case 1: | |
565 | stb_phys(addr, val); | |
566 | return H_SUCCESS; | |
567 | case 2: | |
568 | stw_phys(addr, val); | |
569 | return H_SUCCESS; | |
570 | case 4: | |
571 | stl_phys(addr, val); | |
572 | return H_SUCCESS; | |
573 | case 8: | |
574 | stq_phys(addr, val); | |
575 | return H_SUCCESS; | |
576 | } | |
577 | return H_PARAMETER; | |
578 | } | |
579 | ||
b13ce26d | 580 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
c73e3771 BH |
581 | target_ulong opcode, target_ulong *args) |
582 | { | |
583 | target_ulong dst = args[0]; /* Destination address */ | |
584 | target_ulong src = args[1]; /* Source address */ | |
585 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
586 | target_ulong count = args[3]; /* Element count */ | |
587 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
588 | uint64_t tmp; | |
589 | unsigned int mask = (1 << esize) - 1; | |
590 | int step = 1 << esize; | |
591 | ||
592 | if (count > 0x80000000) { | |
593 | return H_PARAMETER; | |
594 | } | |
595 | ||
596 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
597 | return H_PARAMETER; | |
598 | } | |
599 | ||
600 | if (dst >= src && dst < (src + (count << esize))) { | |
601 | dst = dst + ((count - 1) << esize); | |
602 | src = src + ((count - 1) << esize); | |
603 | step = -step; | |
604 | } | |
605 | ||
606 | while (count--) { | |
607 | switch (esize) { | |
608 | case 0: | |
609 | tmp = ldub_phys(src); | |
610 | break; | |
611 | case 1: | |
612 | tmp = lduw_phys(src); | |
613 | break; | |
614 | case 2: | |
615 | tmp = ldl_phys(src); | |
616 | break; | |
617 | case 3: | |
618 | tmp = ldq_phys(src); | |
619 | break; | |
620 | default: | |
621 | return H_PARAMETER; | |
622 | } | |
623 | if (op == 1) { | |
624 | tmp = ~tmp; | |
625 | } | |
626 | switch (esize) { | |
627 | case 0: | |
628 | stb_phys(dst, tmp); | |
629 | break; | |
630 | case 1: | |
631 | stw_phys(dst, tmp); | |
632 | break; | |
633 | case 2: | |
634 | stl_phys(dst, tmp); | |
635 | break; | |
636 | case 3: | |
637 | stq_phys(dst, tmp); | |
638 | break; | |
639 | } | |
640 | dst = dst + step; | |
641 | src = src + step; | |
642 | } | |
643 | ||
644 | return H_SUCCESS; | |
645 | } | |
646 | ||
b13ce26d | 647 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
648 | target_ulong opcode, target_ulong *args) |
649 | { | |
650 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
651 | return H_SUCCESS; | |
652 | } | |
653 | ||
b13ce26d | 654 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
655 | target_ulong opcode, target_ulong *args) |
656 | { | |
657 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
658 | return H_SUCCESS; | |
659 | } | |
660 | ||
7d7ba3fe DG |
661 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
662 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
9fdf0c29 DG |
663 | |
664 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
665 | { | |
39ac8455 DG |
666 | spapr_hcall_fn *slot; |
667 | ||
668 | if (opcode <= MAX_HCALL_OPCODE) { | |
669 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 670 | |
39ac8455 DG |
671 | slot = &papr_hypercall_table[opcode / 4]; |
672 | } else { | |
673 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 674 | |
39ac8455 DG |
675 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
676 | } | |
9fdf0c29 | 677 | |
c89d5299 | 678 | assert(!(*slot)); |
39ac8455 | 679 | *slot = fn; |
9fdf0c29 DG |
680 | } |
681 | ||
aa100fa4 | 682 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
683 | target_ulong *args) |
684 | { | |
9fdf0c29 DG |
685 | if ((opcode <= MAX_HCALL_OPCODE) |
686 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
687 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
688 | ||
689 | if (fn) { | |
b13ce26d | 690 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
691 | } |
692 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
693 | (opcode <= KVMPPC_HCALL_MAX)) { | |
694 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
695 | |
696 | if (fn) { | |
b13ce26d | 697 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
698 | } |
699 | } | |
700 | ||
701 | hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); | |
702 | return H_FUNCTION; | |
703 | } | |
f43e3525 | 704 | |
83f7d43a | 705 | static void hypercall_register_types(void) |
f43e3525 DG |
706 | { |
707 | /* hcall-pft */ | |
708 | spapr_register_hypercall(H_ENTER, h_enter); | |
709 | spapr_register_hypercall(H_REMOVE, h_remove); | |
710 | spapr_register_hypercall(H_PROTECT, h_protect); | |
6bbd5dde | 711 | spapr_register_hypercall(H_READ, h_read); |
39ac8455 | 712 | |
a3d0abae DG |
713 | /* hcall-bulk */ |
714 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
715 | ||
821303f5 DG |
716 | /* hcall-dabr */ |
717 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); | |
718 | ||
ed120055 DG |
719 | /* hcall-splpar */ |
720 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
721 | spapr_register_hypercall(H_CEDE, h_cede); | |
722 | ||
827200a2 DG |
723 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
724 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
725 | * mapping attributes qemu is using. When using KVM, the kernel will | |
726 | * enforce the attributes more strongly | |
727 | */ | |
728 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
729 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
730 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
731 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
732 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
733 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 734 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 735 | |
39ac8455 DG |
736 | /* qemu/KVM-PPC specific hcalls */ |
737 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
f43e3525 | 738 | } |
83f7d43a AF |
739 | |
740 | type_init(hypercall_register_types) |