[qemu.git] / hw / ppc / xics.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "hw/hw.h"
#include "trace.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/xics.h"

/*
 * ICP: Presentation layer
 */

struct icp_server_state {
    uint32_t xirr;
    uint8_t pending_priority;
    uint8_t mfrr;
    qemu_irq output;
};

#define XISR_MASK  0x00ffffff
#define CPPR_MASK  0xff000000

#define XISR(ss)   (((ss)->xirr) & XISR_MASK)
#define CPPR(ss)   (((ss)->xirr) >> 24)

struct ics_state;

struct icp_state {
    long nr_servers;
    struct icp_server_state *ss;
    struct ics_state *ics;
};

static void ics_reject(struct ics_state *ics, int nr);
static void ics_resend(struct ics_state *ics);
static void ics_eoi(struct ics_state *ics, int nr);

static void icp_check_ipi(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
        return;
    }

    trace_xics_icp_check_ipi(server, ss->mfrr);

    if (XISR(ss)) {
        ics_reject(icp->ics, XISR(ss));
    }

    ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
    ss->pending_priority = ss->mfrr;
    qemu_irq_raise(ss->output);
}

static void icp_resend(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (ss->mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
    ics_resend(icp->ics);
}

static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
{
    struct icp_server_state *ss = icp->ss + server;
    uint8_t old_cppr;
    uint32_t old_xisr;

    old_cppr = CPPR(ss);
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);

    if (cppr < old_cppr) {
        if (XISR(ss) && (cppr <= ss->pending_priority)) {
            old_xisr = XISR(ss);
            ss->xirr &= ~XISR_MASK; /* Clear XISR */
            ss->pending_priority = 0xff;
            qemu_irq_lower(ss->output);
            ics_reject(icp->ics, old_xisr);
        }
    } else {
        if (!XISR(ss)) {
            icp_resend(icp, server);
        }
    }
}

static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
{
    struct icp_server_state *ss = icp->ss + server;

    ss->mfrr = mfrr;
    if (mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
}

static uint32_t icp_accept(struct icp_server_state *ss)
{
    uint32_t xirr = ss->xirr;

    qemu_irq_lower(ss->output);
    ss->xirr = ss->pending_priority << 24;
    ss->pending_priority = 0xff;

    trace_xics_icp_accept(xirr, ss->xirr);

    return xirr;
}

static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
{
    struct icp_server_state *ss = icp->ss + server;

    /* Send EOI -> ICS */
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
    trace_xics_icp_eoi(server, xirr, ss->xirr);
    ics_eoi(icp->ics, xirr & XISR_MASK);
    if (!XISR(ss)) {
        icp_resend(icp, server);
    }
}

static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
{
    struct icp_server_state *ss = icp->ss + server;

    trace_xics_icp_irq(server, nr, priority);

    if ((priority >= CPPR(ss))
        || (XISR(ss) && (ss->pending_priority <= priority))) {
        ics_reject(icp->ics, nr);
    } else {
        if (XISR(ss)) {
            ics_reject(icp->ics, XISR(ss));
        }
        ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
        ss->pending_priority = priority;
        trace_xics_icp_raise(ss->xirr, ss->pending_priority);
        qemu_irq_raise(ss->output);
    }
}

/*
 * ICS: Source layer
 */

struct ics_irq_state {
    int server;
    uint8_t priority;
    uint8_t saved_priority;
#define XICS_STATUS_ASSERTED           0x1
#define XICS_STATUS_SENT               0x2
#define XICS_STATUS_REJECTED           0x4
#define XICS_STATUS_MASKED_PENDING     0x8
    uint8_t status;
};

struct ics_state {
    int nr_irqs;
    int offset;
    qemu_irq *qirqs;
    bool *islsi;
    struct ics_irq_state *irqs;
    struct icp_state *icp;
};

static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
{
    return (nr >= ics->offset)
        && (nr < (ics->offset + ics->nr_irqs));
}

static void resend_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    /* FIXME: filter by server#? */
    if (irq->status & XICS_STATUS_REJECTED) {
        irq->status &= ~XICS_STATUS_REJECTED;
        if (irq->priority != 0xff) {
            icp_irq(ics->icp, irq->server, srcno + ics->offset,
                    irq->priority);
        }
    }
}

static void resend_lsi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if ((irq->priority != 0xff)
        && (irq->status & XICS_STATUS_ASSERTED)
        && !(irq->status & XICS_STATUS_SENT)) {
        irq->status |= XICS_STATUS_SENT;
        icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
    }
}

static void set_irq_msi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    trace_xics_set_irq_msi(srcno, srcno + ics->offset);

    if (val) {
        if (irq->priority == 0xff) {
            irq->status |= XICS_STATUS_MASKED_PENDING;
            trace_xics_masked_pending();
        } else  {
            icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
        }
    }
}

static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
    if (val) {
        irq->status |= XICS_STATUS_ASSERTED;
    } else {
        irq->status &= ~XICS_STATUS_ASSERTED;
    }
    resend_lsi(ics, srcno);
}

static void ics_set_irq(void *opaque, int srcno, int val)
{
    struct ics_state *ics = (struct ics_state *)opaque;

    if (ics->islsi[srcno]) {
        set_irq_lsi(ics, srcno, val);
    } else {
        set_irq_msi(ics, srcno, val);
    }
}

static void write_xive_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (!(irq->status & XICS_STATUS_MASKED_PENDING)
        || (irq->priority == 0xff)) {
        return;
    }

    irq->status &= ~XICS_STATUS_MASKED_PENDING;
    icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
}

static void write_xive_lsi(struct ics_state *ics, int srcno)
{
    resend_lsi(ics, srcno);
}

static void ics_write_xive(struct ics_state *ics, int nr, int server,
                           uint8_t priority, uint8_t saved_priority)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    irq->server = server;
    irq->priority = priority;
    irq->saved_priority = saved_priority;

    trace_xics_ics_write_xive(nr, srcno, server, priority);

    if (ics->islsi[srcno]) {
        write_xive_lsi(ics, srcno);
    } else {
        write_xive_msi(ics, srcno);
    }
}

static void ics_reject(struct ics_state *ics, int nr)
{
    struct ics_irq_state *irq = ics->irqs + nr - ics->offset;

    trace_xics_ics_reject(nr, nr - ics->offset);
    irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
    irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
}

static void ics_resend(struct ics_state *ics)
{
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        /* FIXME: filter by server#? */
        if (ics->islsi[i]) {
            resend_lsi(ics, i);
        } else {
            resend_msi(ics, i);
        }
    }
}

static void ics_eoi(struct ics_state *ics, int nr)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    trace_xics_ics_eoi(nr);

    if (ics->islsi[srcno]) {
        irq->status &= ~XICS_STATUS_SENT;
    }
}

/*
 * Exported functions
 */

qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
{
    if (!ics_valid_irq(icp->ics, irq)) {
        return NULL;
    }

    return icp->ics->qirqs[irq - icp->ics->offset];
}

void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
{
    assert(ics_valid_irq(icp->ics, irq));

    icp->ics->islsi[irq - icp->ics->offset] = lsi;
}

static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    CPUState *cs = CPU(cpu);
    target_ulong cppr = args[0];

    icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong server = args[0];
    target_ulong mfrr = args[1];

    if (server >= spapr->icp->nr_servers) {
        return H_PARAMETER;
    }

    icp_set_mfrr(spapr->icp, server, mfrr);
    return H_SUCCESS;
}

static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    CPUState *cs = CPU(cpu);
    uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    CPUState *cs = CPU(cpu);
    target_ulong xirr = args[0];

    icp_eoi(spapr->icp, cs->cpu_index, xirr);
    return H_SUCCESS;
}

static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
        || (priority > 0xff)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, server, priority, priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                          uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    rtas_st(rets, 0, 0); /* Success */
    rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
    rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
}

static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                         uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
                   ics->irqs[nr - ics->offset].priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                        uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
                   ics->irqs[nr - ics->offset].saved_priority,
                   ics->irqs[nr - ics->offset].saved_priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void xics_reset(void *opaque)
{
    struct icp_state *icp = (struct icp_state *)opaque;
    struct ics_state *ics = icp->ics;
    int i;

    for (i = 0; i < icp->nr_servers; i++) {
        icp->ss[i].xirr = 0;
        icp->ss[i].pending_priority = 0xff;
        icp->ss[i].mfrr = 0xff;
        /* Make all outputs are deasserted */
        qemu_set_irq(icp->ss[i].output, 0);
    }

    memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs);
    for (i = 0; i < ics->nr_irqs; i++) {
        ics->irqs[i].priority = 0xff;
        ics->irqs[i].saved_priority = 0xff;
    }
}

void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
{
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;
    struct icp_server_state *ss = &icp->ss[cs->cpu_index];

    assert(cs->cpu_index < icp->nr_servers);

    switch (PPC_INPUT(env)) {
    case PPC_FLAGS_INPUT_POWER7:
        ss->output = env->irq_inputs[POWER7_INPUT_INT];
        break;

    case PPC_FLAGS_INPUT_970:
        ss->output = env->irq_inputs[PPC970_INPUT_INT];
        break;

    default:
        fprintf(stderr, "XICS interrupt controller does not support this CPU "
                "bus model\n");
        abort();
    }
}

struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
{
    struct icp_state *icp;
    struct ics_state *ics;

    icp = g_malloc0(sizeof(*icp));
    icp->nr_servers = nr_servers;
    icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));

    ics = g_malloc0(sizeof(*ics));
    ics->nr_irqs = nr_irqs;
    ics->offset = XICS_IRQ_BASE;
    ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
    ics->islsi = g_malloc0(nr_irqs * sizeof(bool));

    icp->ics = ics;
    ics->icp = icp;

    ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_EOI, h_eoi);

    spapr_rtas_register("ibm,set-xive", rtas_set_xive);
    spapr_rtas_register("ibm,get-xive", rtas_get_xive);
    spapr_rtas_register("ibm,int-off", rtas_int_off);
    spapr_rtas_register("ibm,int-on", rtas_int_on);

    qemu_register_reset(xics_reset, icp);

    return icp;
}
Commit	Line	Data
b5cec4c5 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
83c9f4ca	28	#include "hw/hw.h"
500efa23	29	#include "trace.h"
0d09e41a PB	30	#include "hw/ppc/spapr.h"
0d09e41a PB	31	#include "hw/ppc/xics.h"
b5cec4c5	32
b5cec4c5 DG	33	/*
	34	* ICP: Presentation layer
	35	*/
	36
	37	struct icp_server_state {
	38	uint32_t xirr;
	39	uint8_t pending_priority;
	40	uint8_t mfrr;
	41	qemu_irq output;
	42	};
	43
	44	#define XISR_MASK 0x00ffffff
	45	#define CPPR_MASK 0xff000000
	46
	47	#define XISR(ss) (((ss)->xirr) & XISR_MASK)
	48	#define CPPR(ss) (((ss)->xirr) >> 24)
	49
	50	struct ics_state;
	51
	52	struct icp_state {
	53	long nr_servers;
	54	struct icp_server_state *ss;
	55	struct ics_state *ics;
	56	};
	57
	58	static void ics_reject(struct ics_state *ics, int nr);
	59	static void ics_resend(struct ics_state *ics);
	60	static void ics_eoi(struct ics_state *ics, int nr);
	61
	62	static void icp_check_ipi(struct icp_state *icp, int server)
	63	{
	64	struct icp_server_state *ss = icp->ss + server;
	65
	66	if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
	67	return;
	68	}
	69
500efa23 DG	70	trace_xics_icp_check_ipi(server, ss->mfrr);
500efa23 DG	71
b5cec4c5 DG	72	if (XISR(ss)) {
	73	ics_reject(icp->ics, XISR(ss));
	74	}
	75
	76	ss->xirr = (ss->xirr & ~XISR_MASK) \| XICS_IPI;
	77	ss->pending_priority = ss->mfrr;
	78	qemu_irq_raise(ss->output);
	79	}
	80
	81	static void icp_resend(struct icp_state *icp, int server)
	82	{
	83	struct icp_server_state *ss = icp->ss + server;
	84
	85	if (ss->mfrr < CPPR(ss)) {
	86	icp_check_ipi(icp, server);
	87	}
	88	ics_resend(icp->ics);
	89	}
	90
	91	static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
	92	{
	93	struct icp_server_state *ss = icp->ss + server;
	94	uint8_t old_cppr;
	95	uint32_t old_xisr;
	96
	97	old_cppr = CPPR(ss);
	98	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (cppr << 24);
	99
	100	if (cppr < old_cppr) {
	101	if (XISR(ss) && (cppr <= ss->pending_priority)) {
	102	old_xisr = XISR(ss);
	103	ss->xirr &= ~XISR_MASK; /* Clear XISR */
e03c902c	104	ss->pending_priority = 0xff;
b5cec4c5 DG	105	qemu_irq_lower(ss->output);
	106	ics_reject(icp->ics, old_xisr);
	107	}
	108	} else {
	109	if (!XISR(ss)) {
	110	icp_resend(icp, server);
	111	}
	112	}
	113	}
	114
bf0175de	115	static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
b5cec4c5	116	{
bf0175de	117	struct icp_server_state *ss = icp->ss + server;
b5cec4c5 DG	118
	119	ss->mfrr = mfrr;
	120	if (mfrr < CPPR(ss)) {
bf0175de	121	icp_check_ipi(icp, server);
b5cec4c5 DG	122	}
	123	}
	124
	125	static uint32_t icp_accept(struct icp_server_state *ss)
	126	{
500efa23	127	uint32_t xirr = ss->xirr;
b5cec4c5 DG	128
b5cec4c5 DG	129	qemu_irq_lower(ss->output);
b5cec4c5	130	ss->xirr = ss->pending_priority << 24;
e03c902c	131	ss->pending_priority = 0xff;
500efa23 DG	132
	133	trace_xics_icp_accept(xirr, ss->xirr);
	134
b5cec4c5 DG	135	return xirr;
	136	}
	137
	138	static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
	139	{
	140	struct icp_server_state *ss = icp->ss + server;
	141
b5cec4c5 DG	142	/* Send EOI -> ICS */
b5cec4c5 DG	143	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (xirr & CPPR_MASK);
500efa23	144	trace_xics_icp_eoi(server, xirr, ss->xirr);
d07fee7e	145	ics_eoi(icp->ics, xirr & XISR_MASK);
b5cec4c5 DG	146	if (!XISR(ss)) {
	147	icp_resend(icp, server);
	148	}
	149	}
	150
	151	static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
	152	{
	153	struct icp_server_state *ss = icp->ss + server;
	154
500efa23 DG	155	trace_xics_icp_irq(server, nr, priority);
500efa23 DG	156
b5cec4c5 DG	157	if ((priority >= CPPR(ss))
	158	\|\| (XISR(ss) && (ss->pending_priority <= priority))) {
	159	ics_reject(icp->ics, nr);
	160	} else {
	161	if (XISR(ss)) {
	162	ics_reject(icp->ics, XISR(ss));
	163	}
	164	ss->xirr = (ss->xirr & ~XISR_MASK) \| (nr & XISR_MASK);
	165	ss->pending_priority = priority;
500efa23	166	trace_xics_icp_raise(ss->xirr, ss->pending_priority);
b5cec4c5 DG	167	qemu_irq_raise(ss->output);
	168	}
	169	}
	170
	171	/*
	172	* ICS: Source layer
	173	*/
	174
	175	struct ics_irq_state {
	176	int server;
	177	uint8_t priority;
	178	uint8_t saved_priority;
98ca8c02 DG	179	#define XICS_STATUS_ASSERTED 0x1
	180	#define XICS_STATUS_SENT 0x2
	181	#define XICS_STATUS_REJECTED 0x4
	182	#define XICS_STATUS_MASKED_PENDING 0x8
	183	uint8_t status;
b5cec4c5 DG	184	};
	185
	186	struct ics_state {
	187	int nr_irqs;
	188	int offset;
	189	qemu_irq *qirqs;
22a2611c	190	bool *islsi;
b5cec4c5 DG	191	struct ics_irq_state *irqs;
	192	struct icp_state *icp;
	193	};
	194
	195	static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
	196	{
	197	return (nr >= ics->offset)
	198	&& (nr < (ics->offset + ics->nr_irqs));
	199	}
	200
d07fee7e DG	201	static void resend_msi(struct ics_state *ics, int srcno)
	202	{
	203	struct ics_irq_state *irq = ics->irqs + srcno;
	204
	205	/* FIXME: filter by server#? */
98ca8c02 DG	206	if (irq->status & XICS_STATUS_REJECTED) {
98ca8c02 DG	207	irq->status &= ~XICS_STATUS_REJECTED;
d07fee7e DG	208	if (irq->priority != 0xff) {
	209	icp_irq(ics->icp, irq->server, srcno + ics->offset,
	210	irq->priority);
	211	}
	212	}
	213	}
	214
	215	static void resend_lsi(struct ics_state *ics, int srcno)
	216	{
	217	struct ics_irq_state *irq = ics->irqs + srcno;
	218
98ca8c02 DG	219	if ((irq->priority != 0xff)
	220	&& (irq->status & XICS_STATUS_ASSERTED)
	221	&& !(irq->status & XICS_STATUS_SENT)) {
	222	irq->status \|= XICS_STATUS_SENT;
d07fee7e DG	223	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
	224	}
	225	}
	226
	227	static void set_irq_msi(struct ics_state *ics, int srcno, int val)
b5cec4c5	228	{
cc67b9c8	229	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	230
500efa23 DG	231	trace_xics_set_irq_msi(srcno, srcno + ics->offset);
500efa23 DG	232
b5cec4c5 DG	233	if (val) {
b5cec4c5 DG	234	if (irq->priority == 0xff) {
98ca8c02	235	irq->status \|= XICS_STATUS_MASKED_PENDING;
500efa23	236	trace_xics_masked_pending();
b5cec4c5	237	} else {
cc67b9c8	238	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	239	}
	240	}
	241	}
	242
d07fee7e	243	static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
b5cec4c5	244	{
d07fee7e	245	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	246
500efa23	247	trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
98ca8c02 DG	248	if (val) {
	249	irq->status \|= XICS_STATUS_ASSERTED;
	250	} else {
	251	irq->status &= ~XICS_STATUS_ASSERTED;
	252	}
d07fee7e	253	resend_lsi(ics, srcno);
b5cec4c5 DG	254	}
b5cec4c5 DG	255
d07fee7e	256	static void ics_set_irq(void *opaque, int srcno, int val)
b5cec4c5	257	{
d07fee7e	258	struct ics_state ics = (struct ics_state )opaque;
b5cec4c5	259
22a2611c	260	if (ics->islsi[srcno]) {
d07fee7e DG	261	set_irq_lsi(ics, srcno, val);
	262	} else {
	263	set_irq_msi(ics, srcno, val);
	264	}
	265	}
b5cec4c5	266
d07fee7e DG	267	static void write_xive_msi(struct ics_state *ics, int srcno)
	268	{
	269	struct ics_irq_state *irq = ics->irqs + srcno;
	270
98ca8c02 DG	271	if (!(irq->status & XICS_STATUS_MASKED_PENDING)
98ca8c02 DG	272	\|\| (irq->priority == 0xff)) {
d07fee7e	273	return;
b5cec4c5	274	}
d07fee7e	275
98ca8c02	276	irq->status &= ~XICS_STATUS_MASKED_PENDING;
d07fee7e	277	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	278	}
b5cec4c5 DG	279
d07fee7e	280	static void write_xive_lsi(struct ics_state *ics, int srcno)
b5cec4c5	281	{
d07fee7e DG	282	resend_lsi(ics, srcno);
	283	}
	284
	285	static void ics_write_xive(struct ics_state *ics, int nr, int server,
3fe719f4	286	uint8_t priority, uint8_t saved_priority)
d07fee7e DG	287	{
	288	int srcno = nr - ics->offset;
	289	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5 DG	290
	291	irq->server = server;
	292	irq->priority = priority;
3fe719f4	293	irq->saved_priority = saved_priority;
b5cec4c5	294
500efa23 DG	295	trace_xics_ics_write_xive(nr, srcno, server, priority);
500efa23 DG	296
22a2611c	297	if (ics->islsi[srcno]) {
d07fee7e DG	298	write_xive_lsi(ics, srcno);
	299	} else {
	300	write_xive_msi(ics, srcno);
b5cec4c5	301	}
b5cec4c5 DG	302	}
	303
	304	static void ics_reject(struct ics_state *ics, int nr)
	305	{
d07fee7e DG	306	struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
d07fee7e DG	307
500efa23	308	trace_xics_ics_reject(nr, nr - ics->offset);
98ca8c02 DG	309	irq->status \|= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
98ca8c02 DG	310	irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
b5cec4c5 DG	311	}
	312
	313	static void ics_resend(struct ics_state *ics)
	314	{
d07fee7e DG	315	int i;
	316
	317	for (i = 0; i < ics->nr_irqs; i++) {
d07fee7e	318	/* FIXME: filter by server#? */
22a2611c	319	if (ics->islsi[i]) {
d07fee7e DG	320	resend_lsi(ics, i);
	321	} else {
	322	resend_msi(ics, i);
	323	}
	324	}
b5cec4c5 DG	325	}
	326
	327	static void ics_eoi(struct ics_state *ics, int nr)
	328	{
d07fee7e DG	329	int srcno = nr - ics->offset;
	330	struct ics_irq_state *irq = ics->irqs + srcno;
	331
500efa23 DG	332	trace_xics_ics_eoi(nr);
500efa23 DG	333
22a2611c	334	if (ics->islsi[srcno]) {
98ca8c02	335	irq->status &= ~XICS_STATUS_SENT;
d07fee7e	336	}
b5cec4c5 DG	337	}
	338
	339	/*
	340	* Exported functions
	341	*/
	342
a307d594	343	qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
b5cec4c5	344	{
1ecbbab4	345	if (!ics_valid_irq(icp->ics, irq)) {
b5cec4c5 DG	346	return NULL;
	347	}
	348
a307d594 AK	349	return icp->ics->qirqs[irq - icp->ics->offset];
	350	}
	351
ff9d2afa	352	void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
a307d594	353	{
1ecbbab4	354	assert(ics_valid_irq(icp->ics, irq));
d07fee7e	355
22a2611c	356	icp->ics->islsi[irq - icp->ics->offset] = lsi;
b5cec4c5 DG	357	}
b5cec4c5 DG	358
b13ce26d	359	static target_ulong h_cppr(PowerPCCPU cpu, sPAPREnvironment spapr,
b5cec4c5 DG	360	target_ulong opcode, target_ulong *args)
b5cec4c5 DG	361	{
55e5c285	362	CPUState *cs = CPU(cpu);
b5cec4c5 DG	363	target_ulong cppr = args[0];
b5cec4c5 DG	364
55e5c285	365	icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
b5cec4c5 DG	366	return H_SUCCESS;
	367	}
	368
b13ce26d	369	static target_ulong h_ipi(PowerPCCPU cpu, sPAPREnvironment spapr,
b5cec4c5 DG	370	target_ulong opcode, target_ulong *args)
	371	{
	372	target_ulong server = args[0];
	373	target_ulong mfrr = args[1];
	374
	375	if (server >= spapr->icp->nr_servers) {
	376	return H_PARAMETER;
	377	}
	378
	379	icp_set_mfrr(spapr->icp, server, mfrr);
	380	return H_SUCCESS;
b5cec4c5 DG	381	}
b5cec4c5 DG	382
b13ce26d	383	static target_ulong h_xirr(PowerPCCPU cpu, sPAPREnvironment spapr,
b5cec4c5 DG	384	target_ulong opcode, target_ulong *args)
b5cec4c5 DG	385	{
55e5c285 AF	386	CPUState *cs = CPU(cpu);
55e5c285 AF	387	uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
b5cec4c5 DG	388
	389	args[0] = xirr;
	390	return H_SUCCESS;
	391	}
	392
b13ce26d	393	static target_ulong h_eoi(PowerPCCPU cpu, sPAPREnvironment spapr,
b5cec4c5 DG	394	target_ulong opcode, target_ulong *args)
b5cec4c5 DG	395	{
55e5c285	396	CPUState *cs = CPU(cpu);
b5cec4c5 DG	397	target_ulong xirr = args[0];
b5cec4c5 DG	398
55e5c285	399	icp_eoi(spapr->icp, cs->cpu_index, xirr);
b5cec4c5 DG	400	return H_SUCCESS;
	401	}
	402
210b580b AL	403	static void rtas_set_xive(PowerPCCPU cpu, sPAPREnvironment spapr,
210b580b AL	404	uint32_t token,
b5cec4c5 DG	405	uint32_t nargs, target_ulong args,
	406	uint32_t nret, target_ulong rets)
	407	{
	408	struct ics_state *ics = spapr->icp->ics;
	409	uint32_t nr, server, priority;
	410
	411	if ((nargs != 3) \|\| (nret != 1)) {
	412	rtas_st(rets, 0, -3);
	413	return;
	414	}
	415
	416	nr = rtas_ld(args, 0);
	417	server = rtas_ld(args, 1);
	418	priority = rtas_ld(args, 2);
	419
	420	if (!ics_valid_irq(ics, nr) \|\| (server >= ics->icp->nr_servers)
	421	\|\| (priority > 0xff)) {
	422	rtas_st(rets, 0, -3);
	423	return;
	424	}
	425
3fe719f4	426	ics_write_xive(ics, nr, server, priority, priority);
b5cec4c5 DG	427
	428	rtas_st(rets, 0, 0); /* Success */
	429	}
	430
210b580b AL	431	static void rtas_get_xive(PowerPCCPU cpu, sPAPREnvironment spapr,
210b580b AL	432	uint32_t token,
b5cec4c5 DG	433	uint32_t nargs, target_ulong args,
	434	uint32_t nret, target_ulong rets)
	435	{
	436	struct ics_state *ics = spapr->icp->ics;
	437	uint32_t nr;
	438
	439	if ((nargs != 1) \|\| (nret != 3)) {
	440	rtas_st(rets, 0, -3);
	441	return;
	442	}
	443
	444	nr = rtas_ld(args, 0);
	445
	446	if (!ics_valid_irq(ics, nr)) {
	447	rtas_st(rets, 0, -3);
	448	return;
	449	}
	450
	451	rtas_st(rets, 0, 0); /* Success */
	452	rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
	453	rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
	454	}
	455
210b580b AL	456	static void rtas_int_off(PowerPCCPU cpu, sPAPREnvironment spapr,
210b580b AL	457	uint32_t token,
b5cec4c5 DG	458	uint32_t nargs, target_ulong args,
	459	uint32_t nret, target_ulong rets)
	460	{
	461	struct ics_state *ics = spapr->icp->ics;
	462	uint32_t nr;
	463
	464	if ((nargs != 1) \|\| (nret != 1)) {
	465	rtas_st(rets, 0, -3);
	466	return;
	467	}
	468
	469	nr = rtas_ld(args, 0);
	470
	471	if (!ics_valid_irq(ics, nr)) {
	472	rtas_st(rets, 0, -3);
	473	return;
	474	}
	475
3fe719f4 DG	476	ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
3fe719f4 DG	477	ics->irqs[nr - ics->offset].priority);
b5cec4c5 DG	478
	479	rtas_st(rets, 0, 0); /* Success */
	480	}
	481
210b580b AL	482	static void rtas_int_on(PowerPCCPU cpu, sPAPREnvironment spapr,
210b580b AL	483	uint32_t token,
b5cec4c5 DG	484	uint32_t nargs, target_ulong args,
	485	uint32_t nret, target_ulong rets)
	486	{
	487	struct ics_state *ics = spapr->icp->ics;
	488	uint32_t nr;
	489
	490	if ((nargs != 1) \|\| (nret != 1)) {
	491	rtas_st(rets, 0, -3);
	492	return;
	493	}
	494
	495	nr = rtas_ld(args, 0);
	496
	497	if (!ics_valid_irq(ics, nr)) {
	498	rtas_st(rets, 0, -3);
	499	return;
	500	}
	501
3fe719f4 DG	502	ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
	503	ics->irqs[nr - ics->offset].saved_priority,
	504	ics->irqs[nr - ics->offset].saved_priority);
b5cec4c5 DG	505
	506	rtas_st(rets, 0, 0); /* Success */
	507	}
	508
256b408a DG	509	static void xics_reset(void *opaque)
	510	{
	511	struct icp_state icp = (struct icp_state )opaque;
	512	struct ics_state *ics = icp->ics;
	513	int i;
	514
	515	for (i = 0; i < icp->nr_servers; i++) {
	516	icp->ss[i].xirr = 0;
044f4c8b	517	icp->ss[i].pending_priority = 0xff;
256b408a DG	518	icp->ss[i].mfrr = 0xff;
	519	/* Make all outputs are deasserted */
	520	qemu_set_irq(icp->ss[i].output, 0);
	521	}
	522
22a2611c	523	memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs);
256b408a	524	for (i = 0; i < ics->nr_irqs; i++) {
256b408a DG	525	ics->irqs[i].priority = 0xff;
	526	ics->irqs[i].saved_priority = 0xff;
	527	}
	528	}
	529
7b565160	530	void xics_cpu_setup(struct icp_state icp, PowerPCCPU cpu)
b5cec4c5	531	{
7b565160 DG	532	CPUState *cs = CPU(cpu);
	533	CPUPPCState *env = &cpu->env;
	534	struct icp_server_state *ss = &icp->ss[cs->cpu_index];
b5cec4c5	535
7b565160	536	assert(cs->cpu_index < icp->nr_servers);
c7a5c0c9	537
7b565160 DG	538	switch (PPC_INPUT(env)) {
	539	case PPC_FLAGS_INPUT_POWER7:
	540	ss->output = env->irq_inputs[POWER7_INPUT_INT];
	541	break;
c7a5c0c9	542
7b565160 DG	543	case PPC_FLAGS_INPUT_970:
	544	ss->output = env->irq_inputs[PPC970_INPUT_INT];
	545	break;
b5cec4c5	546
7b565160 DG	547	default:
	548	fprintf(stderr, "XICS interrupt controller does not support this CPU "
	549	"bus model\n");
	550	abort();
	551	}
	552	}
b5cec4c5	553
7b565160 DG	554	struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
	555	{
	556	struct icp_state *icp;
	557	struct ics_state *ics;
b5cec4c5	558
7b565160 DG	559	icp = g_malloc0(sizeof(*icp));
	560	icp->nr_servers = nr_servers;
	561	icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
b5cec4c5	562
7267c094	563	ics = g_malloc0(sizeof(*ics));
b5cec4c5	564	ics->nr_irqs = nr_irqs;
bf3bc4c4	565	ics->offset = XICS_IRQ_BASE;
7267c094	566	ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
22a2611c	567	ics->islsi = g_malloc0(nr_irqs * sizeof(bool));
b5cec4c5 DG	568
	569	icp->ics = ics;
	570	ics->icp = icp;
	571
d07fee7e	572	ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
b5cec4c5 DG	573
	574	spapr_register_hypercall(H_CPPR, h_cppr);
	575	spapr_register_hypercall(H_IPI, h_ipi);
	576	spapr_register_hypercall(H_XIRR, h_xirr);
	577	spapr_register_hypercall(H_EOI, h_eoi);
	578
	579	spapr_rtas_register("ibm,set-xive", rtas_set_xive);
	580	spapr_rtas_register("ibm,get-xive", rtas_get_xive);
	581	spapr_rtas_register("ibm,int-off", rtas_int_off);
	582	spapr_rtas_register("ibm,int-on", rtas_int_on);
	583
256b408a DG	584	qemu_register_reset(xics_reset, icp);
256b408a DG	585
b5cec4c5 DG	586	return icp;
b5cec4c5 DG	587	}