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Commit | Line | Data |
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1a6c0886 JM |
1 | /* |
2 | * QEMU PowerPC 405 evaluation boards emulation | |
5fafdf24 | 3 | * |
1a6c0886 | 4 | * Copyright (c) 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
1a6c0886 JM |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "ppc.h" | |
1a6c0886 | 26 | #include "ppc405.h" |
87ecb68b PB |
27 | #include "nvram.h" |
28 | #include "flash.h" | |
29 | #include "sysemu.h" | |
30 | #include "block.h" | |
31 | #include "boards.h" | |
3b3fb322 | 32 | #include "qemu-log.h" |
ca20cf32 | 33 | #include "loader.h" |
2446333c | 34 | #include "blockdev.h" |
1a6c0886 JM |
35 | |
36 | #define BIOS_FILENAME "ppc405_rom.bin" | |
1a6c0886 JM |
37 | #define BIOS_SIZE (2048 * 1024) |
38 | ||
39 | #define KERNEL_LOAD_ADDR 0x00000000 | |
40 | #define INITRD_LOAD_ADDR 0x01800000 | |
41 | ||
42 | #define USE_FLASH_BIOS | |
43 | ||
44 | #define DEBUG_BOARD_INIT | |
45 | ||
46 | /*****************************************************************************/ | |
47 | /* PPC405EP reference board (IBM) */ | |
48 | /* Standalone board with: | |
49 | * - PowerPC 405EP CPU | |
50 | * - SDRAM (0x00000000) | |
51 | * - Flash (0xFFF80000) | |
52 | * - SRAM (0xFFF00000) | |
53 | * - NVRAM (0xF0000000) | |
54 | * - FPGA (0xF0300000) | |
55 | */ | |
c227f099 AL |
56 | typedef struct ref405ep_fpga_t ref405ep_fpga_t; |
57 | struct ref405ep_fpga_t { | |
1a6c0886 JM |
58 | uint8_t reg0; |
59 | uint8_t reg1; | |
60 | }; | |
61 | ||
c227f099 | 62 | static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr) |
1a6c0886 | 63 | { |
c227f099 | 64 | ref405ep_fpga_t *fpga; |
1a6c0886 JM |
65 | uint32_t ret; |
66 | ||
67 | fpga = opaque; | |
1a6c0886 JM |
68 | switch (addr) { |
69 | case 0x0: | |
70 | ret = fpga->reg0; | |
71 | break; | |
72 | case 0x1: | |
73 | ret = fpga->reg1; | |
74 | break; | |
75 | default: | |
76 | ret = 0; | |
77 | break; | |
78 | } | |
79 | ||
80 | return ret; | |
81 | } | |
82 | ||
83 | static void ref405ep_fpga_writeb (void *opaque, | |
c227f099 | 84 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 | 85 | { |
c227f099 | 86 | ref405ep_fpga_t *fpga; |
1a6c0886 JM |
87 | |
88 | fpga = opaque; | |
1a6c0886 JM |
89 | switch (addr) { |
90 | case 0x0: | |
91 | /* Read only */ | |
92 | break; | |
93 | case 0x1: | |
94 | fpga->reg1 = value; | |
95 | break; | |
96 | default: | |
97 | break; | |
98 | } | |
99 | } | |
100 | ||
c227f099 | 101 | static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr) |
1a6c0886 JM |
102 | { |
103 | uint32_t ret; | |
104 | ||
105 | ret = ref405ep_fpga_readb(opaque, addr) << 8; | |
106 | ret |= ref405ep_fpga_readb(opaque, addr + 1); | |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
111 | static void ref405ep_fpga_writew (void *opaque, | |
c227f099 | 112 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 JM |
113 | { |
114 | ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); | |
115 | ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); | |
116 | } | |
117 | ||
c227f099 | 118 | static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr) |
1a6c0886 JM |
119 | { |
120 | uint32_t ret; | |
121 | ||
122 | ret = ref405ep_fpga_readb(opaque, addr) << 24; | |
123 | ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; | |
124 | ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; | |
125 | ret |= ref405ep_fpga_readb(opaque, addr + 3); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
130 | static void ref405ep_fpga_writel (void *opaque, | |
c227f099 | 131 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 | 132 | { |
8de24106 AJ |
133 | ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); |
134 | ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); | |
135 | ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); | |
1a6c0886 JM |
136 | ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); |
137 | } | |
138 | ||
d60efc6b | 139 | static CPUReadMemoryFunc * const ref405ep_fpga_read[] = { |
1a6c0886 JM |
140 | &ref405ep_fpga_readb, |
141 | &ref405ep_fpga_readw, | |
142 | &ref405ep_fpga_readl, | |
143 | }; | |
144 | ||
d60efc6b | 145 | static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = { |
1a6c0886 JM |
146 | &ref405ep_fpga_writeb, |
147 | &ref405ep_fpga_writew, | |
148 | &ref405ep_fpga_writel, | |
149 | }; | |
150 | ||
151 | static void ref405ep_fpga_reset (void *opaque) | |
152 | { | |
c227f099 | 153 | ref405ep_fpga_t *fpga; |
1a6c0886 JM |
154 | |
155 | fpga = opaque; | |
156 | fpga->reg0 = 0x00; | |
157 | fpga->reg1 = 0x0F; | |
158 | } | |
159 | ||
160 | static void ref405ep_fpga_init (uint32_t base) | |
161 | { | |
c227f099 | 162 | ref405ep_fpga_t *fpga; |
1a6c0886 JM |
163 | int fpga_memory; |
164 | ||
7267c094 | 165 | fpga = g_malloc0(sizeof(ref405ep_fpga_t)); |
1eed09cb | 166 | fpga_memory = cpu_register_io_memory(ref405ep_fpga_read, |
2507c12a AG |
167 | ref405ep_fpga_write, fpga, |
168 | DEVICE_NATIVE_ENDIAN); | |
487414f1 | 169 | cpu_register_physical_memory(base, 0x00000100, fpga_memory); |
a08d4367 | 170 | qemu_register_reset(&ref405ep_fpga_reset, fpga); |
1a6c0886 JM |
171 | } |
172 | ||
c227f099 | 173 | static void ref405ep_init (ram_addr_t ram_size, |
3023f332 | 174 | const char *boot_device, |
5fafdf24 | 175 | const char *kernel_filename, |
1a6c0886 JM |
176 | const char *kernel_cmdline, |
177 | const char *initrd_filename, | |
178 | const char *cpu_model) | |
179 | { | |
5cea8590 | 180 | char *filename; |
c227f099 | 181 | ppc4xx_bd_info_t bd; |
1a6c0886 JM |
182 | CPUPPCState *env; |
183 | qemu_irq *pic; | |
01e0451a | 184 | ram_addr_t sram_offset, bios_offset, bdloc; |
b6dcbe08 | 185 | MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
c227f099 | 186 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
093209cd BS |
187 | target_ulong sram_size; |
188 | long bios_size; | |
1a6c0886 JM |
189 | //int phy_addr = 0; |
190 | //static int phy_addr = 1; | |
093209cd BS |
191 | target_ulong kernel_base, initrd_base; |
192 | long kernel_size, initrd_size; | |
1a6c0886 JM |
193 | int linux_boot; |
194 | int fl_idx, fl_sectors, len; | |
751c6a17 | 195 | DriveInfo *dinfo; |
1a6c0886 JM |
196 | |
197 | /* XXX: fix this */ | |
b6dcbe08 AK |
198 | memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000); |
199 | ram_bases[0] = 0; | |
1a6c0886 | 200 | ram_sizes[0] = 0x08000000; |
b6dcbe08 | 201 | memory_region_init(&ram_memories[1], "ef405ep.ram1", 0); |
1a6c0886 JM |
202 | ram_bases[1] = 0x00000000; |
203 | ram_sizes[1] = 0x00000000; | |
204 | ram_size = 128 * 1024 * 1024; | |
205 | #ifdef DEBUG_BOARD_INIT | |
206 | printf("%s: register cpu\n", __func__); | |
207 | #endif | |
b6dcbe08 | 208 | env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, |
1a6c0886 JM |
209 | kernel_filename == NULL ? 0 : 1); |
210 | /* allocate SRAM */ | |
5c130f65 | 211 | sram_size = 512 * 1024; |
1724f049 | 212 | sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); |
1a6c0886 JM |
213 | #ifdef DEBUG_BOARD_INIT |
214 | printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); | |
215 | #endif | |
1a6c0886 JM |
216 | cpu_register_physical_memory(0xFFF00000, sram_size, |
217 | sram_offset | IO_MEM_RAM); | |
218 | /* allocate and load BIOS */ | |
219 | #ifdef DEBUG_BOARD_INIT | |
220 | printf("%s: register BIOS\n", __func__); | |
221 | #endif | |
1a6c0886 JM |
222 | fl_idx = 0; |
223 | #ifdef USE_FLASH_BIOS | |
751c6a17 GH |
224 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
225 | if (dinfo) { | |
226 | bios_size = bdrv_getlength(dinfo->bdrv); | |
01e0451a | 227 | bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size); |
1a6c0886 JM |
228 | fl_sectors = (bios_size + 65535) >> 16; |
229 | #ifdef DEBUG_BOARD_INIT | |
093209cd | 230 | printf("Register parallel flash %d size %lx" |
01e0451a AL |
231 | " at offset %08lx addr %lx '%s' %d\n", |
232 | fl_idx, bios_size, bios_offset, -bios_size, | |
751c6a17 | 233 | bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
1a6c0886 | 234 | #endif |
01e0451a | 235 | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
751c6a17 | 236 | dinfo->bdrv, 65536, fl_sectors, 1, |
01e0451a AL |
237 | 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
238 | 1); | |
1a6c0886 JM |
239 | fl_idx++; |
240 | } else | |
241 | #endif | |
242 | { | |
243 | #ifdef DEBUG_BOARD_INIT | |
244 | printf("Load BIOS from file\n"); | |
245 | #endif | |
01e0451a | 246 | bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE); |
1192dad8 JM |
247 | if (bios_name == NULL) |
248 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
249 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
250 | if (filename) { | |
01e0451a | 251 | bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset)); |
7267c094 | 252 | g_free(filename); |
5cea8590 PB |
253 | } else { |
254 | bios_size = -1; | |
255 | } | |
1a6c0886 | 256 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
257 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", |
258 | bios_name); | |
1a6c0886 JM |
259 | exit(1); |
260 | } | |
261 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
01e0451a AL |
262 | cpu_register_physical_memory((uint32_t)(-bios_size), |
263 | bios_size, bios_offset | IO_MEM_ROM); | |
1a6c0886 | 264 | } |
1a6c0886 JM |
265 | /* Register FPGA */ |
266 | #ifdef DEBUG_BOARD_INIT | |
267 | printf("%s: register FPGA\n", __func__); | |
268 | #endif | |
269 | ref405ep_fpga_init(0xF0300000); | |
270 | /* Register NVRAM */ | |
271 | #ifdef DEBUG_BOARD_INIT | |
272 | printf("%s: register NVRAM\n", __func__); | |
273 | #endif | |
274 | m48t59_init(NULL, 0xF0000000, 0, 8192, 8); | |
275 | /* Load kernel */ | |
276 | linux_boot = (kernel_filename != NULL); | |
277 | if (linux_boot) { | |
278 | #ifdef DEBUG_BOARD_INIT | |
279 | printf("%s: load kernel\n", __func__); | |
280 | #endif | |
281 | memset(&bd, 0, sizeof(bd)); | |
282 | bd.bi_memstart = 0x00000000; | |
283 | bd.bi_memsize = ram_size; | |
217fae2d | 284 | bd.bi_flashstart = -bios_size; |
1a6c0886 JM |
285 | bd.bi_flashsize = -bios_size; |
286 | bd.bi_flashoffset = 0; | |
287 | bd.bi_sramstart = 0xFFF00000; | |
288 | bd.bi_sramsize = sram_size; | |
289 | bd.bi_bootflags = 0; | |
290 | bd.bi_intfreq = 133333333; | |
291 | bd.bi_busfreq = 33333333; | |
292 | bd.bi_baudrate = 115200; | |
293 | bd.bi_s_version[0] = 'Q'; | |
294 | bd.bi_s_version[1] = 'M'; | |
295 | bd.bi_s_version[2] = 'U'; | |
296 | bd.bi_s_version[3] = '\0'; | |
297 | bd.bi_r_version[0] = 'Q'; | |
298 | bd.bi_r_version[1] = 'E'; | |
299 | bd.bi_r_version[2] = 'M'; | |
300 | bd.bi_r_version[3] = 'U'; | |
301 | bd.bi_r_version[4] = '\0'; | |
302 | bd.bi_procfreq = 133333333; | |
303 | bd.bi_plb_busfreq = 33333333; | |
304 | bd.bi_pci_busfreq = 33333333; | |
305 | bd.bi_opbfreq = 33333333; | |
b8d3f5d1 | 306 | bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); |
1a6c0886 JM |
307 | env->gpr[3] = bdloc; |
308 | kernel_base = KERNEL_LOAD_ADDR; | |
309 | /* now we can load the kernel */ | |
5c130f65 PB |
310 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
311 | ram_size - kernel_base); | |
1a6c0886 | 312 | if (kernel_size < 0) { |
5fafdf24 | 313 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
1a6c0886 JM |
314 | kernel_filename); |
315 | exit(1); | |
316 | } | |
093209cd | 317 | printf("Load kernel size %ld at " TARGET_FMT_lx, |
5c130f65 | 318 | kernel_size, kernel_base); |
1a6c0886 JM |
319 | /* load initrd */ |
320 | if (initrd_filename) { | |
321 | initrd_base = INITRD_LOAD_ADDR; | |
5c130f65 PB |
322 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
323 | ram_size - initrd_base); | |
1a6c0886 | 324 | if (initrd_size < 0) { |
5fafdf24 | 325 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
1a6c0886 JM |
326 | initrd_filename); |
327 | exit(1); | |
328 | } | |
329 | } else { | |
330 | initrd_base = 0; | |
331 | initrd_size = 0; | |
332 | } | |
333 | env->gpr[4] = initrd_base; | |
334 | env->gpr[5] = initrd_size; | |
1a6c0886 JM |
335 | if (kernel_cmdline != NULL) { |
336 | len = strlen(kernel_cmdline); | |
337 | bdloc -= ((len + 255) & ~255); | |
5c130f65 | 338 | cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1); |
1a6c0886 JM |
339 | env->gpr[6] = bdloc; |
340 | env->gpr[7] = bdloc + len; | |
341 | } else { | |
342 | env->gpr[6] = 0; | |
343 | env->gpr[7] = 0; | |
344 | } | |
345 | env->nip = KERNEL_LOAD_ADDR; | |
346 | } else { | |
347 | kernel_base = 0; | |
348 | kernel_size = 0; | |
349 | initrd_base = 0; | |
350 | initrd_size = 0; | |
351 | bdloc = 0; | |
352 | } | |
353 | #ifdef DEBUG_BOARD_INIT | |
354 | printf("%s: Done\n", __func__); | |
355 | #endif | |
5c130f65 | 356 | printf("bdloc %016lx\n", (unsigned long)bdloc); |
1a6c0886 JM |
357 | } |
358 | ||
f80f9ec9 | 359 | static QEMUMachine ref405ep_machine = { |
4b32e168 AL |
360 | .name = "ref405ep", |
361 | .desc = "ref405ep", | |
362 | .init = ref405ep_init, | |
1a6c0886 JM |
363 | }; |
364 | ||
365 | /*****************************************************************************/ | |
366 | /* AMCC Taihu evaluation board */ | |
367 | /* - PowerPC 405EP processor | |
368 | * - SDRAM 128 MB at 0x00000000 | |
369 | * - Boot flash 2 MB at 0xFFE00000 | |
370 | * - Application flash 32 MB at 0xFC000000 | |
371 | * - 2 serial ports | |
372 | * - 2 ethernet PHY | |
373 | * - 1 USB 1.1 device 0x50000000 | |
374 | * - 1 LCD display 0x50100000 | |
375 | * - 1 CPLD 0x50100000 | |
376 | * - 1 I2C EEPROM | |
377 | * - 1 I2C thermal sensor | |
378 | * - a set of LEDs | |
379 | * - bit-bang SPI port using GPIOs | |
380 | * - 1 EBC interface connector 0 0x50200000 | |
381 | * - 1 cardbus controller + expansion slot. | |
382 | * - 1 PCI expansion slot. | |
383 | */ | |
384 | typedef struct taihu_cpld_t taihu_cpld_t; | |
385 | struct taihu_cpld_t { | |
1a6c0886 JM |
386 | uint8_t reg0; |
387 | uint8_t reg1; | |
388 | }; | |
389 | ||
c227f099 | 390 | static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr) |
1a6c0886 JM |
391 | { |
392 | taihu_cpld_t *cpld; | |
393 | uint32_t ret; | |
394 | ||
395 | cpld = opaque; | |
1a6c0886 JM |
396 | switch (addr) { |
397 | case 0x0: | |
398 | ret = cpld->reg0; | |
399 | break; | |
400 | case 0x1: | |
401 | ret = cpld->reg1; | |
402 | break; | |
403 | default: | |
404 | ret = 0; | |
405 | break; | |
406 | } | |
407 | ||
408 | return ret; | |
409 | } | |
410 | ||
411 | static void taihu_cpld_writeb (void *opaque, | |
c227f099 | 412 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 JM |
413 | { |
414 | taihu_cpld_t *cpld; | |
415 | ||
416 | cpld = opaque; | |
1a6c0886 JM |
417 | switch (addr) { |
418 | case 0x0: | |
419 | /* Read only */ | |
420 | break; | |
421 | case 0x1: | |
422 | cpld->reg1 = value; | |
423 | break; | |
424 | default: | |
425 | break; | |
426 | } | |
427 | } | |
428 | ||
c227f099 | 429 | static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr) |
1a6c0886 JM |
430 | { |
431 | uint32_t ret; | |
432 | ||
433 | ret = taihu_cpld_readb(opaque, addr) << 8; | |
434 | ret |= taihu_cpld_readb(opaque, addr + 1); | |
435 | ||
436 | return ret; | |
437 | } | |
438 | ||
439 | static void taihu_cpld_writew (void *opaque, | |
c227f099 | 440 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 JM |
441 | { |
442 | taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF); | |
443 | taihu_cpld_writeb(opaque, addr + 1, value & 0xFF); | |
444 | } | |
445 | ||
c227f099 | 446 | static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr) |
1a6c0886 JM |
447 | { |
448 | uint32_t ret; | |
449 | ||
450 | ret = taihu_cpld_readb(opaque, addr) << 24; | |
451 | ret |= taihu_cpld_readb(opaque, addr + 1) << 16; | |
452 | ret |= taihu_cpld_readb(opaque, addr + 2) << 8; | |
453 | ret |= taihu_cpld_readb(opaque, addr + 3); | |
454 | ||
455 | return ret; | |
456 | } | |
457 | ||
458 | static void taihu_cpld_writel (void *opaque, | |
c227f099 | 459 | target_phys_addr_t addr, uint32_t value) |
1a6c0886 JM |
460 | { |
461 | taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF); | |
462 | taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF); | |
463 | taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF); | |
464 | taihu_cpld_writeb(opaque, addr + 3, value & 0xFF); | |
465 | } | |
466 | ||
d60efc6b | 467 | static CPUReadMemoryFunc * const taihu_cpld_read[] = { |
1a6c0886 JM |
468 | &taihu_cpld_readb, |
469 | &taihu_cpld_readw, | |
470 | &taihu_cpld_readl, | |
471 | }; | |
472 | ||
d60efc6b | 473 | static CPUWriteMemoryFunc * const taihu_cpld_write[] = { |
1a6c0886 JM |
474 | &taihu_cpld_writeb, |
475 | &taihu_cpld_writew, | |
476 | &taihu_cpld_writel, | |
477 | }; | |
478 | ||
479 | static void taihu_cpld_reset (void *opaque) | |
480 | { | |
481 | taihu_cpld_t *cpld; | |
482 | ||
483 | cpld = opaque; | |
484 | cpld->reg0 = 0x01; | |
485 | cpld->reg1 = 0x80; | |
486 | } | |
487 | ||
488 | static void taihu_cpld_init (uint32_t base) | |
489 | { | |
490 | taihu_cpld_t *cpld; | |
491 | int cpld_memory; | |
492 | ||
7267c094 | 493 | cpld = g_malloc0(sizeof(taihu_cpld_t)); |
1eed09cb | 494 | cpld_memory = cpu_register_io_memory(taihu_cpld_read, |
2507c12a AG |
495 | taihu_cpld_write, cpld, |
496 | DEVICE_NATIVE_ENDIAN); | |
487414f1 | 497 | cpu_register_physical_memory(base, 0x00000100, cpld_memory); |
a08d4367 | 498 | qemu_register_reset(&taihu_cpld_reset, cpld); |
1a6c0886 JM |
499 | } |
500 | ||
c227f099 | 501 | static void taihu_405ep_init(ram_addr_t ram_size, |
3023f332 | 502 | const char *boot_device, |
5fafdf24 | 503 | const char *kernel_filename, |
1a6c0886 JM |
504 | const char *kernel_cmdline, |
505 | const char *initrd_filename, | |
506 | const char *cpu_model) | |
507 | { | |
5cea8590 | 508 | char *filename; |
1a6c0886 | 509 | qemu_irq *pic; |
01e0451a | 510 | ram_addr_t bios_offset; |
b6dcbe08 | 511 | MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
c227f099 | 512 | target_phys_addr_t ram_bases[2], ram_sizes[2]; |
093209cd BS |
513 | long bios_size; |
514 | target_ulong kernel_base, initrd_base; | |
515 | long kernel_size, initrd_size; | |
1a6c0886 JM |
516 | int linux_boot; |
517 | int fl_idx, fl_sectors; | |
751c6a17 | 518 | DriveInfo *dinfo; |
3b46e624 | 519 | |
1a6c0886 | 520 | /* RAM is soldered to the board so the size cannot be changed */ |
b6dcbe08 AK |
521 | memory_region_init_ram(&ram_memories[0], NULL, |
522 | "taihu_405ep.ram-0", 0x04000000); | |
523 | ram_bases[0] = 0; | |
1a6c0886 | 524 | ram_sizes[0] = 0x04000000; |
b6dcbe08 AK |
525 | memory_region_init_ram(&ram_memories[1], NULL, |
526 | "taihu_405ep.ram-1", 0x04000000); | |
527 | ram_bases[1] = 0x04000000; | |
1a6c0886 | 528 | ram_sizes[1] = 0x04000000; |
a0b753df | 529 | ram_size = 0x08000000; |
1a6c0886 JM |
530 | #ifdef DEBUG_BOARD_INIT |
531 | printf("%s: register cpu\n", __func__); | |
532 | #endif | |
b6dcbe08 | 533 | ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic, |
49a2942d | 534 | kernel_filename == NULL ? 0 : 1); |
1a6c0886 JM |
535 | /* allocate and load BIOS */ |
536 | #ifdef DEBUG_BOARD_INIT | |
537 | printf("%s: register BIOS\n", __func__); | |
538 | #endif | |
539 | fl_idx = 0; | |
540 | #if defined(USE_FLASH_BIOS) | |
751c6a17 GH |
541 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
542 | if (dinfo) { | |
543 | bios_size = bdrv_getlength(dinfo->bdrv); | |
1a6c0886 JM |
544 | /* XXX: should check that size is 2MB */ |
545 | // bios_size = 2 * 1024 * 1024; | |
546 | fl_sectors = (bios_size + 65535) >> 16; | |
01e0451a | 547 | bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size); |
1a6c0886 | 548 | #ifdef DEBUG_BOARD_INIT |
093209cd | 549 | printf("Register parallel flash %d size %lx" |
01e0451a AL |
550 | " at offset %08lx addr %lx '%s' %d\n", |
551 | fl_idx, bios_size, bios_offset, -bios_size, | |
751c6a17 | 552 | bdrv_get_device_name(dinfo->bdrv), fl_sectors); |
1a6c0886 | 553 | #endif |
01e0451a | 554 | pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, |
751c6a17 | 555 | dinfo->bdrv, 65536, fl_sectors, 1, |
01e0451a AL |
556 | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
557 | 1); | |
1a6c0886 JM |
558 | fl_idx++; |
559 | } else | |
560 | #endif | |
561 | { | |
562 | #ifdef DEBUG_BOARD_INIT | |
563 | printf("Load BIOS from file\n"); | |
564 | #endif | |
1192dad8 JM |
565 | if (bios_name == NULL) |
566 | bios_name = BIOS_FILENAME; | |
01e0451a | 567 | bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE); |
5cea8590 PB |
568 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
569 | if (filename) { | |
01e0451a | 570 | bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset)); |
7267c094 | 571 | g_free(filename); |
5cea8590 PB |
572 | } else { |
573 | bios_size = -1; | |
574 | } | |
1a6c0886 | 575 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
576 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", |
577 | bios_name); | |
1a6c0886 JM |
578 | exit(1); |
579 | } | |
580 | bios_size = (bios_size + 0xfff) & ~0xfff; | |
01e0451a AL |
581 | cpu_register_physical_memory((uint32_t)(-bios_size), |
582 | bios_size, bios_offset | IO_MEM_ROM); | |
1a6c0886 | 583 | } |
1a6c0886 | 584 | /* Register Linux flash */ |
751c6a17 GH |
585 | dinfo = drive_get(IF_PFLASH, 0, fl_idx); |
586 | if (dinfo) { | |
587 | bios_size = bdrv_getlength(dinfo->bdrv); | |
1a6c0886 JM |
588 | /* XXX: should check that size is 32MB */ |
589 | bios_size = 32 * 1024 * 1024; | |
590 | fl_sectors = (bios_size + 65535) >> 16; | |
591 | #ifdef DEBUG_BOARD_INIT | |
093209cd | 592 | printf("Register parallel flash %d size %lx" |
01e0451a AL |
593 | " at offset %08lx addr " TARGET_FMT_lx " '%s'\n", |
594 | fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, | |
751c6a17 | 595 | bdrv_get_device_name(dinfo->bdrv)); |
1a6c0886 | 596 | #endif |
01e0451a AL |
597 | bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size); |
598 | pflash_cfi02_register(0xfc000000, bios_offset, | |
751c6a17 | 599 | dinfo->bdrv, 65536, fl_sectors, 1, |
01e0451a AL |
600 | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, |
601 | 1); | |
1a6c0886 JM |
602 | fl_idx++; |
603 | } | |
604 | /* Register CLPD & LCD display */ | |
605 | #ifdef DEBUG_BOARD_INIT | |
606 | printf("%s: register CPLD\n", __func__); | |
607 | #endif | |
608 | taihu_cpld_init(0x50100000); | |
609 | /* Load kernel */ | |
610 | linux_boot = (kernel_filename != NULL); | |
611 | if (linux_boot) { | |
612 | #ifdef DEBUG_BOARD_INIT | |
613 | printf("%s: load kernel\n", __func__); | |
614 | #endif | |
615 | kernel_base = KERNEL_LOAD_ADDR; | |
616 | /* now we can load the kernel */ | |
5c130f65 PB |
617 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
618 | ram_size - kernel_base); | |
1a6c0886 | 619 | if (kernel_size < 0) { |
5fafdf24 | 620 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
1a6c0886 JM |
621 | kernel_filename); |
622 | exit(1); | |
623 | } | |
624 | /* load initrd */ | |
625 | if (initrd_filename) { | |
626 | initrd_base = INITRD_LOAD_ADDR; | |
5c130f65 PB |
627 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
628 | ram_size - initrd_base); | |
1a6c0886 JM |
629 | if (initrd_size < 0) { |
630 | fprintf(stderr, | |
5fafdf24 | 631 | "qemu: could not load initial ram disk '%s'\n", |
1a6c0886 JM |
632 | initrd_filename); |
633 | exit(1); | |
634 | } | |
635 | } else { | |
636 | initrd_base = 0; | |
637 | initrd_size = 0; | |
638 | } | |
1a6c0886 JM |
639 | } else { |
640 | kernel_base = 0; | |
641 | kernel_size = 0; | |
642 | initrd_base = 0; | |
643 | initrd_size = 0; | |
644 | } | |
645 | #ifdef DEBUG_BOARD_INIT | |
646 | printf("%s: Done\n", __func__); | |
647 | #endif | |
648 | } | |
649 | ||
f80f9ec9 | 650 | static QEMUMachine taihu_machine = { |
b2ee0ce2 PB |
651 | .name = "taihu", |
652 | .desc = "taihu", | |
653 | .init = taihu_405ep_init, | |
1a6c0886 | 654 | }; |
f80f9ec9 AL |
655 | |
656 | static void ppc405_machine_init(void) | |
657 | { | |
658 | qemu_register_machine(&ref405ep_machine); | |
659 | qemu_register_machine(&taihu_machine); | |
660 | } | |
661 | ||
662 | machine_init(ppc405_machine_init); |