[qemu.git] / hw / ppc4xx_devs.c

/*
 * QEMU PowerPC 4xx embedded processors shared devices emulation
 *
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
#include "sysemu.h"
#include "qemu-log.h"

//#define DEBUG_MMIO
//#define DEBUG_UNASSIGNED
#define DEBUG_UIC

/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
CPUState *ppc4xx_init (const char *cpu_model,
                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
                       uint32_t sysclk)
{
    CPUState *env;

    /* init CPUs */
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
                cpu_model);
        exit(1);
    }
    cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
    cpu_clk->opaque = env;
    /* Set time-base frequency to sysclk */
    tb_clk->cb = ppc_emb_timers_init(env, sysclk);
    tb_clk->opaque = env;
    ppc_dcr_init(env, NULL, NULL);
    /* Register qemu callbacks */
    qemu_register_reset(&cpu_ppc_reset, env);

    return env;
}

/*****************************************************************************/
/* Fake device used to map multiple devices in a single memory page */
#define MMIO_AREA_BITS 8
#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
struct ppc4xx_mmio_t {
    target_phys_addr_t base;
    CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
    CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
    void *opaque[MMIO_AREA_NB];
};

static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_UNASSIGNED
    ppc4xx_mmio_t *mmio;

    mmio = opaque;
    printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
           addr, mmio->base);
#endif

    return 0;
}

static void unassigned_mmio_writeb (void *opaque,
                                    target_phys_addr_t addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
    ppc4xx_mmio_t *mmio;

    mmio = opaque;
    printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
           addr, val, mmio->base);
#endif
}

static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
    unassigned_mmio_readb,
    unassigned_mmio_readb,
    unassigned_mmio_readb,
};

static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
    unassigned_mmio_writeb,
    unassigned_mmio_writeb,
    unassigned_mmio_writeb,
};

static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
                              target_phys_addr_t addr, int len)
{
    CPUReadMemoryFunc **mem_read;
    uint32_t ret;
    int idx;

    idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
    printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
           mmio, len, addr, idx);
#endif
    mem_read = mmio->mem_read[idx];
    ret = (*mem_read[len])(mmio->opaque[idx], addr);

    return ret;
}

static void mmio_writelen (ppc4xx_mmio_t *mmio,
                           target_phys_addr_t addr, uint32_t value, int len)
{
    CPUWriteMemoryFunc **mem_write;
    int idx;

    idx = MMIO_IDX(addr);
#if defined(DEBUG_MMIO)
    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
           __func__, mmio, len, addr, idx, value);
#endif
    mem_write = mmio->mem_write[idx];
    (*mem_write[len])(mmio->opaque[idx], addr, value);
}

static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX "\n", __func__, addr);
#endif

    return mmio_readlen(opaque, addr, 0);
}

static void mmio_writeb (void *opaque,
                         target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
    mmio_writelen(opaque, addr, value, 0);
}

static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX "\n", __func__, addr);
#endif

    return mmio_readlen(opaque, addr, 1);
}

static void mmio_writew (void *opaque,
                         target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
    mmio_writelen(opaque, addr, value, 1);
}

static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX "\n", __func__, addr);
#endif

    return mmio_readlen(opaque, addr, 2);
}

static void mmio_writel (void *opaque,
                         target_phys_addr_t addr, uint32_t value)
{
#if defined(DEBUG_MMIO)
    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
    mmio_writelen(opaque, addr, value, 2);
}

static CPUReadMemoryFunc *mmio_read[] = {
    &mmio_readb,
    &mmio_readw,
    &mmio_readl,
};

static CPUWriteMemoryFunc *mmio_write[] = {
    &mmio_writeb,
    &mmio_writew,
    &mmio_writel,
};

int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
                          target_phys_addr_t offset, uint32_t len,
                          CPUReadMemoryFunc **mem_read,
                          CPUWriteMemoryFunc **mem_write, void *opaque)
{
    target_phys_addr_t end;
    int idx, eidx;

    if ((offset + len) > TARGET_PAGE_SIZE)
        return -1;
    idx = MMIO_IDX(offset);
    end = offset + len - 1;
    eidx = MMIO_IDX(end);
#if defined(DEBUG_MMIO)
    printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
           __func__, offset, len, end, idx, eidx);
#endif
    for (; idx <= eidx; idx++) {
        mmio->mem_read[idx] = mem_read;
        mmio->mem_write[idx] = mem_write;
        mmio->opaque[idx] = opaque;
    }

    return 0;
}

ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
{
    ppc4xx_mmio_t *mmio;
    int mmio_memory;

    mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
    if (mmio != NULL) {
        mmio->base = base;
        mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
#if defined(DEBUG_MMIO)
        printf("%s: base " PADDRX " len %08x %d\n", __func__,
               base, TARGET_PAGE_SIZE, mmio_memory);
#endif
        cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
        ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
                             unassigned_mmio_read, unassigned_mmio_write,
                             mmio);
    }

    return mmio;
}

/*****************************************************************************/
/* "Universal" Interrupt controller */
enum {
    DCR_UICSR  = 0x000,
    DCR_UICSRS = 0x001,
    DCR_UICER  = 0x002,
    DCR_UICCR  = 0x003,
    DCR_UICPR  = 0x004,
    DCR_UICTR  = 0x005,
    DCR_UICMSR = 0x006,
    DCR_UICVR  = 0x007,
    DCR_UICVCR = 0x008,
    DCR_UICMAX = 0x009,
};

#define UIC_MAX_IRQ 32
typedef struct ppcuic_t ppcuic_t;
struct ppcuic_t {
    uint32_t dcr_base;
    int use_vectors;
    uint32_t level;  /* Remembers the state of level-triggered interrupts. */
    uint32_t uicsr;  /* Status register */
    uint32_t uicer;  /* Enable register */
    uint32_t uiccr;  /* Critical register */
    uint32_t uicpr;  /* Polarity register */
    uint32_t uictr;  /* Triggering register */
    uint32_t uicvcr; /* Vector configuration register */
    uint32_t uicvr;
    qemu_irq *irqs;
};

static void ppcuic_trigger_irq (ppcuic_t *uic)
{
    uint32_t ir, cr;
    int start, end, inc, i;

    /* Trigger interrupt if any is pending */
    ir = uic->uicsr & uic->uicer & (~uic->uiccr);
    cr = uic->uicsr & uic->uicer & uic->uiccr;
#ifdef DEBUG_UIC
    if (loglevel & CPU_LOG_INT) {
        fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
                " uiccr %08" PRIx32 "\n"
                "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
                __func__, uic->uicsr, uic->uicer, uic->uiccr,
                uic->uicsr & uic->uicer, ir, cr);
    }
#endif
    if (ir != 0x0000000) {
#ifdef DEBUG_UIC
        if (loglevel & CPU_LOG_INT) {
            fprintf(logfile, "Raise UIC interrupt\n");
        }
#endif
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
    } else {
#ifdef DEBUG_UIC
        if (loglevel & CPU_LOG_INT) {
            fprintf(logfile, "Lower UIC interrupt\n");
        }
#endif
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
    }
    /* Trigger critical interrupt if any is pending and update vector */
    if (cr != 0x0000000) {
        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
        if (uic->use_vectors) {
            /* Compute critical IRQ vector */
            if (uic->uicvcr & 1) {
                start = 31;
                end = 0;
                inc = -1;
            } else {
                start = 0;
                end = 31;
                inc = 1;
            }
            uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
            for (i = start; i <= end; i += inc) {
                if (cr & (1 << i)) {
                    uic->uicvr += (i - start) * 512 * inc;
                    break;
                }
            }
        }
#ifdef DEBUG_UIC
        if (loglevel & CPU_LOG_INT) {
            fprintf(logfile, "Raise UIC critical interrupt - "
                    "vector %08" PRIx32 "\n", uic->uicvr);
        }
#endif
    } else {
#ifdef DEBUG_UIC
        if (loglevel & CPU_LOG_INT) {
            fprintf(logfile, "Lower UIC critical interrupt\n");
        }
#endif
        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
        uic->uicvr = 0x00000000;
    }
}

static void ppcuic_set_irq (void *opaque, int irq_num, int level)
{
    ppcuic_t *uic;
    uint32_t mask, sr;

    uic = opaque;
    mask = 1 << (31-irq_num);
#ifdef DEBUG_UIC
    if (loglevel & CPU_LOG_INT) {
        fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
                " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
                __func__, irq_num, level,
                uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
    }
#endif
    if (irq_num < 0 || irq_num > 31)
        return;
    sr = uic->uicsr;

    /* Update status register */
    if (uic->uictr & mask) {
        /* Edge sensitive interrupt */
        if (level == 1)
            uic->uicsr |= mask;
    } else {
        /* Level sensitive interrupt */
        if (level == 1) {
            uic->uicsr |= mask;
            uic->level |= mask;
        } else {
            uic->uicsr &= ~mask;
            uic->level &= ~mask;
        }
    }
#ifdef DEBUG_UIC
    if (loglevel & CPU_LOG_INT) {
        fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
                "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
    }
#endif
    if (sr != uic->uicsr)
        ppcuic_trigger_irq(uic);
}

static target_ulong dcr_read_uic (void *opaque, int dcrn)
{
    ppcuic_t *uic;
    target_ulong ret;

    uic = opaque;
    dcrn -= uic->dcr_base;
    switch (dcrn) {
    case DCR_UICSR:
    case DCR_UICSRS:
        ret = uic->uicsr;
        break;
    case DCR_UICER:
        ret = uic->uicer;
        break;
    case DCR_UICCR:
        ret = uic->uiccr;
        break;
    case DCR_UICPR:
        ret = uic->uicpr;
        break;
    case DCR_UICTR:
        ret = uic->uictr;
        break;
    case DCR_UICMSR:
        ret = uic->uicsr & uic->uicer;
        break;
    case DCR_UICVR:
        if (!uic->use_vectors)
            goto no_read;
        ret = uic->uicvr;
        break;
    case DCR_UICVCR:
        if (!uic->use_vectors)
            goto no_read;
        ret = uic->uicvcr;
        break;
    default:
    no_read:
        ret = 0x00000000;
        break;
    }

    return ret;
}

static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
{
    ppcuic_t *uic;

    uic = opaque;
    dcrn -= uic->dcr_base;
#ifdef DEBUG_UIC
    if (loglevel & CPU_LOG_INT) {
        fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
    }
#endif
    switch (dcrn) {
    case DCR_UICSR:
        uic->uicsr &= ~val;
        uic->uicsr |= uic->level;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICSRS:
        uic->uicsr |= val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICER:
        uic->uicer = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICCR:
        uic->uiccr = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICPR:
        uic->uicpr = val;
        break;
    case DCR_UICTR:
        uic->uictr = val;
        ppcuic_trigger_irq(uic);
        break;
    case DCR_UICMSR:
        break;
    case DCR_UICVR:
        break;
    case DCR_UICVCR:
        uic->uicvcr = val & 0xFFFFFFFD;
        ppcuic_trigger_irq(uic);
        break;
    }
}

static void ppcuic_reset (void *opaque)
{
    ppcuic_t *uic;

    uic = opaque;
    uic->uiccr = 0x00000000;
    uic->uicer = 0x00000000;
    uic->uicpr = 0x00000000;
    uic->uicsr = 0x00000000;
    uic->uictr = 0x00000000;
    if (uic->use_vectors) {
        uic->uicvcr = 0x00000000;
        uic->uicvr = 0x0000000;
    }
}

qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
                       uint32_t dcr_base, int has_ssr, int has_vr)
{
    ppcuic_t *uic;
    int i;

    uic = qemu_mallocz(sizeof(ppcuic_t));
    if (uic != NULL) {
        uic->dcr_base = dcr_base;
        uic->irqs = irqs;
        if (has_vr)
            uic->use_vectors = 1;
        for (i = 0; i < DCR_UICMAX; i++) {
            ppc_dcr_register(env, dcr_base + i, uic,
                             &dcr_read_uic, &dcr_write_uic);
        }
        qemu_register_reset(ppcuic_reset, uic);
        ppcuic_reset(uic);
    }

    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
Commit	Line	Data
008ff9d7 JM	1	/*
	2	* QEMU PowerPC 4xx embedded processors shared devices emulation
	3	*
	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "ppc.h"
008ff9d7	26	#include "ppc4xx.h"
87ecb68b	27	#include "sysemu.h"
3b3fb322	28	#include "qemu-log.h"
008ff9d7 JM	29
008ff9d7 JM	30	//#define DEBUG_MMIO
aae9366a	31	//#define DEBUG_UNASSIGNED
008ff9d7 JM	32	#define DEBUG_UIC
	33
	34	/*****************************************************************************/
	35	/* Generic PowerPC 4xx processor instanciation */
b55266b5	36	CPUState ppc4xx_init (const char cpu_model,
008ff9d7 JM	37	clk_setup_t cpu_clk, clk_setup_t tb_clk,
	38	uint32_t sysclk)
	39	{
	40	CPUState *env;
008ff9d7 JM	41
008ff9d7 JM	42	/* init CPUs */
aaed909a FB	43	env = cpu_init(cpu_model);
	44	if (!env) {
	45	fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
	46	cpu_model);
	47	exit(1);
008ff9d7	48	}
008ff9d7 JM	49	cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
	50	cpu_clk->opaque = env;
	51	/* Set time-base frequency to sysclk */
	52	tb_clk->cb = ppc_emb_timers_init(env, sysclk);
	53	tb_clk->opaque = env;
	54	ppc_dcr_init(env, NULL, NULL);
	55	/* Register qemu callbacks */
	56	qemu_register_reset(&cpu_ppc_reset, env);
008ff9d7 JM	57
	58	return env;
	59	}
	60
	61	/*****************************************************************************/
	62	/* Fake device used to map multiple devices in a single memory page */
	63	#define MMIO_AREA_BITS 8
	64	#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
	65	#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
	66	#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
	67	struct ppc4xx_mmio_t {
	68	target_phys_addr_t base;
	69	CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
	70	CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
	71	void *opaque[MMIO_AREA_NB];
	72	};
	73
	74	static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
	75	{
	76	#ifdef DEBUG_UNASSIGNED
	77	ppc4xx_mmio_t *mmio;
	78
	79	mmio = opaque;
	80	printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
	81	addr, mmio->base);
	82	#endif
	83
	84	return 0;
	85	}
	86
	87	static void unassigned_mmio_writeb (void *opaque,
	88	target_phys_addr_t addr, uint32_t val)
	89	{
	90	#ifdef DEBUG_UNASSIGNED
	91	ppc4xx_mmio_t *mmio;
	92
	93	mmio = opaque;
	94	printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
	95	addr, val, mmio->base);
	96	#endif
	97	}
	98
	99	static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
	100	unassigned_mmio_readb,
	101	unassigned_mmio_readb,
	102	unassigned_mmio_readb,
	103	};
	104
	105	static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
	106	unassigned_mmio_writeb,
	107	unassigned_mmio_writeb,
	108	unassigned_mmio_writeb,
	109	};
	110
	111	static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
	112	target_phys_addr_t addr, int len)
	113	{
	114	CPUReadMemoryFunc **mem_read;
	115	uint32_t ret;
	116	int idx;
	117
8da3ff18	118	idx = MMIO_IDX(addr);
008ff9d7 JM	119	#if defined(DEBUG_MMIO)
	120	printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
	121	mmio, len, addr, idx);
	122	#endif
	123	mem_read = mmio->mem_read[idx];
8da3ff18	124	ret = (*mem_read[len])(mmio->opaque[idx], addr);
008ff9d7 JM	125
	126	return ret;
	127	}
	128
	129	static void mmio_writelen (ppc4xx_mmio_t *mmio,
	130	target_phys_addr_t addr, uint32_t value, int len)
	131	{
	132	CPUWriteMemoryFunc **mem_write;
	133	int idx;
	134
8da3ff18	135	idx = MMIO_IDX(addr);
008ff9d7	136	#if defined(DEBUG_MMIO)
aae9366a JM	137	printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
aae9366a JM	138	__func__, mmio, len, addr, idx, value);
008ff9d7 JM	139	#endif
008ff9d7 JM	140	mem_write = mmio->mem_write[idx];
8da3ff18	141	(*mem_write[len])(mmio->opaque[idx], addr, value);
008ff9d7 JM	142	}
	143
	144	static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
	145	{
	146	#if defined(DEBUG_MMIO)
	147	printf("%s: addr " PADDRX "\n", __func__, addr);
	148	#endif
	149
	150	return mmio_readlen(opaque, addr, 0);
	151	}
	152
	153	static void mmio_writeb (void *opaque,
	154	target_phys_addr_t addr, uint32_t value)
	155	{
	156	#if defined(DEBUG_MMIO)
aae9366a	157	printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
008ff9d7 JM	158	#endif
	159	mmio_writelen(opaque, addr, value, 0);
	160	}
	161
	162	static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
	163	{
	164	#if defined(DEBUG_MMIO)
	165	printf("%s: addr " PADDRX "\n", __func__, addr);
	166	#endif
	167
	168	return mmio_readlen(opaque, addr, 1);
	169	}
	170
	171	static void mmio_writew (void *opaque,
	172	target_phys_addr_t addr, uint32_t value)
	173	{
	174	#if defined(DEBUG_MMIO)
aae9366a	175	printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
008ff9d7 JM	176	#endif
	177	mmio_writelen(opaque, addr, value, 1);
	178	}
	179
	180	static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
	181	{
	182	#if defined(DEBUG_MMIO)
	183	printf("%s: addr " PADDRX "\n", __func__, addr);
	184	#endif
	185
	186	return mmio_readlen(opaque, addr, 2);
	187	}
	188
	189	static void mmio_writel (void *opaque,
	190	target_phys_addr_t addr, uint32_t value)
	191	{
	192	#if defined(DEBUG_MMIO)
aae9366a	193	printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
008ff9d7 JM	194	#endif
	195	mmio_writelen(opaque, addr, value, 2);
	196	}
	197
	198	static CPUReadMemoryFunc *mmio_read[] = {
	199	&mmio_readb,
	200	&mmio_readw,
	201	&mmio_readl,
	202	};
	203
	204	static CPUWriteMemoryFunc *mmio_write[] = {
	205	&mmio_writeb,
	206	&mmio_writew,
	207	&mmio_writel,
	208	};
	209
	210	int ppc4xx_mmio_register (CPUState env, ppc4xx_mmio_t mmio,
	211	target_phys_addr_t offset, uint32_t len,
	212	CPUReadMemoryFunc **mem_read,
	213	CPUWriteMemoryFunc *mem_write, void opaque)
	214	{
aae9366a	215	target_phys_addr_t end;
008ff9d7 JM	216	int idx, eidx;
	217
	218	if ((offset + len) > TARGET_PAGE_SIZE)
	219	return -1;
	220	idx = MMIO_IDX(offset);
	221	end = offset + len - 1;
	222	eidx = MMIO_IDX(end);
	223	#if defined(DEBUG_MMIO)
aae9366a JM	224	printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
aae9366a JM	225	__func__, offset, len, end, idx, eidx);
008ff9d7 JM	226	#endif
	227	for (; idx <= eidx; idx++) {
	228	mmio->mem_read[idx] = mem_read;
	229	mmio->mem_write[idx] = mem_write;
	230	mmio->opaque[idx] = opaque;
	231	}
	232
	233	return 0;
	234	}
	235
	236	ppc4xx_mmio_t ppc4xx_mmio_init (CPUState env, target_phys_addr_t base)
	237	{
	238	ppc4xx_mmio_t *mmio;
	239	int mmio_memory;
	240
	241	mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
	242	if (mmio != NULL) {
	243	mmio->base = base;
	244	mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
	245	#if defined(DEBUG_MMIO)
aae9366a JM	246	printf("%s: base " PADDRX " len %08x %d\n", __func__,
aae9366a JM	247	base, TARGET_PAGE_SIZE, mmio_memory);
008ff9d7 JM	248	#endif
	249	cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
	250	ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
	251	unassigned_mmio_read, unassigned_mmio_write,
	252	mmio);
	253	}
	254
	255	return mmio;
	256	}
	257
	258	/*****************************************************************************/
	259	/* "Universal" Interrupt controller */
	260	enum {
	261	DCR_UICSR = 0x000,
	262	DCR_UICSRS = 0x001,
	263	DCR_UICER = 0x002,
	264	DCR_UICCR = 0x003,
	265	DCR_UICPR = 0x004,
	266	DCR_UICTR = 0x005,
	267	DCR_UICMSR = 0x006,
	268	DCR_UICVR = 0x007,
	269	DCR_UICVCR = 0x008,
	270	DCR_UICMAX = 0x009,
	271	};
	272
	273	#define UIC_MAX_IRQ 32
	274	typedef struct ppcuic_t ppcuic_t;
	275	struct ppcuic_t {
	276	uint32_t dcr_base;
	277	int use_vectors;
4c54e875	278	uint32_t level; /* Remembers the state of level-triggered interrupts. */
008ff9d7 JM	279	uint32_t uicsr; /* Status register */
	280	uint32_t uicer; /* Enable register */
	281	uint32_t uiccr; /* Critical register */
	282	uint32_t uicpr; /* Polarity register */
	283	uint32_t uictr; /* Triggering register */
	284	uint32_t uicvcr; /* Vector configuration register */
	285	uint32_t uicvr;
	286	qemu_irq *irqs;
	287	};
	288
	289	static void ppcuic_trigger_irq (ppcuic_t *uic)
	290	{
	291	uint32_t ir, cr;
	292	int start, end, inc, i;
	293
	294	/* Trigger interrupt if any is pending */
	295	ir = uic->uicsr & uic->uicer & (~uic->uiccr);
	296	cr = uic->uicsr & uic->uicer & uic->uiccr;
	297	#ifdef DEBUG_UIC
	298	if (loglevel & CPU_LOG_INT) {
aae9366a JM	299	fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
	300	" uiccr %08" PRIx32 "\n"
	301	" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
	302	__func__, uic->uicsr, uic->uicer, uic->uiccr,
008ff9d7 JM	303	uic->uicsr & uic->uicer, ir, cr);
	304	}
	305	#endif
	306	if (ir != 0x0000000) {
	307	#ifdef DEBUG_UIC
	308	if (loglevel & CPU_LOG_INT) {
	309	fprintf(logfile, "Raise UIC interrupt\n");
	310	}
	311	#endif
	312	qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
	313	} else {
	314	#ifdef DEBUG_UIC
	315	if (loglevel & CPU_LOG_INT) {
	316	fprintf(logfile, "Lower UIC interrupt\n");
	317	}
	318	#endif
	319	qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
	320	}
	321	/* Trigger critical interrupt if any is pending and update vector */
	322	if (cr != 0x0000000) {
	323	qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
	324	if (uic->use_vectors) {
	325	/* Compute critical IRQ vector */
	326	if (uic->uicvcr & 1) {
	327	start = 31;
	328	end = 0;
	329	inc = -1;
	330	} else {
	331	start = 0;
	332	end = 31;
	333	inc = 1;
	334	}
	335	uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
	336	for (i = start; i <= end; i += inc) {
	337	if (cr & (1 << i)) {
	338	uic->uicvr += (i - start) * 512 * inc;
	339	break;
	340	}
	341	}
	342	}
	343	#ifdef DEBUG_UIC
	344	if (loglevel & CPU_LOG_INT) {
aae9366a JM	345	fprintf(logfile, "Raise UIC critical interrupt - "
aae9366a JM	346	"vector %08" PRIx32 "\n", uic->uicvr);
008ff9d7 JM	347	}
	348	#endif
	349	} else {
	350	#ifdef DEBUG_UIC
	351	if (loglevel & CPU_LOG_INT) {
	352	fprintf(logfile, "Lower UIC critical interrupt\n");
	353	}
	354	#endif
	355	qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
	356	uic->uicvr = 0x00000000;
	357	}
	358	}
	359
	360	static void ppcuic_set_irq (void *opaque, int irq_num, int level)
	361	{
	362	ppcuic_t *uic;
	363	uint32_t mask, sr;
	364
	365	uic = opaque;
923e5e33	366	mask = 1 << (31-irq_num);
008ff9d7 JM	367	#ifdef DEBUG_UIC
008ff9d7 JM	368	if (loglevel & CPU_LOG_INT) {
aae9366a JM	369	fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
	370	" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
	371	__func__, irq_num, level,
008ff9d7 JM	372	uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
	373	}
	374	#endif
	375	if (irq_num < 0 \|\| irq_num > 31)
	376	return;
	377	sr = uic->uicsr;
50bf72b3	378
008ff9d7 JM	379	/* Update status register */
	380	if (uic->uictr & mask) {
	381	/* Edge sensitive interrupt */
	382	if (level == 1)
	383	uic->uicsr \|= mask;
	384	} else {
	385	/* Level sensitive interrupt */
4c54e875	386	if (level == 1) {
008ff9d7	387	uic->uicsr \|= mask;
4c54e875 AJ	388	uic->level \|= mask;
4c54e875 AJ	389	} else {
008ff9d7	390	uic->uicsr &= ~mask;
4c54e875 AJ	391	uic->level &= ~mask;
4c54e875 AJ	392	}
008ff9d7 JM	393	}
	394	#ifdef DEBUG_UIC
	395	if (loglevel & CPU_LOG_INT) {
aae9366a JM	396	fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
aae9366a JM	397	"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
008ff9d7 JM	398	}
	399	#endif
	400	if (sr != uic->uicsr)
	401	ppcuic_trigger_irq(uic);
	402	}
	403
	404	static target_ulong dcr_read_uic (void *opaque, int dcrn)
	405	{
	406	ppcuic_t *uic;
	407	target_ulong ret;
	408
	409	uic = opaque;
	410	dcrn -= uic->dcr_base;
	411	switch (dcrn) {
	412	case DCR_UICSR:
	413	case DCR_UICSRS:
	414	ret = uic->uicsr;
	415	break;
	416	case DCR_UICER:
	417	ret = uic->uicer;
	418	break;
	419	case DCR_UICCR:
	420	ret = uic->uiccr;
	421	break;
	422	case DCR_UICPR:
	423	ret = uic->uicpr;
	424	break;
	425	case DCR_UICTR:
	426	ret = uic->uictr;
	427	break;
	428	case DCR_UICMSR:
	429	ret = uic->uicsr & uic->uicer;
	430	break;
	431	case DCR_UICVR:
	432	if (!uic->use_vectors)
	433	goto no_read;
	434	ret = uic->uicvr;
	435	break;
	436	case DCR_UICVCR:
	437	if (!uic->use_vectors)
	438	goto no_read;
	439	ret = uic->uicvcr;
	440	break;
	441	default:
	442	no_read:
	443	ret = 0x00000000;
	444	break;
	445	}
	446
	447	return ret;
	448	}
	449
	450	static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
	451	{
	452	ppcuic_t *uic;
	453
	454	uic = opaque;
	455	dcrn -= uic->dcr_base;
	456	#ifdef DEBUG_UIC
	457	if (loglevel & CPU_LOG_INT) {
	458	fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
	459	}
	460	#endif
	461	switch (dcrn) {
462	case DCR_UICSR:
463	uic->uicsr &= ~val;
4c54e875	464	uic->uicsr \|= uic->level;
008ff9d7 JM	465	ppcuic_trigger_irq(uic);
	466	break;
	467	case DCR_UICSRS:
	468	uic->uicsr \|= val;
	469	ppcuic_trigger_irq(uic);
	470	break;
	471	case DCR_UICER:
	472	uic->uicer = val;
	473	ppcuic_trigger_irq(uic);
	474	break;
	475	case DCR_UICCR:
	476	uic->uiccr = val;
	477	ppcuic_trigger_irq(uic);
	478	break;
	479	case DCR_UICPR:
	480	uic->uicpr = val;
008ff9d7 JM	481	break;
	482	case DCR_UICTR:
	483	uic->uictr = val;
	484	ppcuic_trigger_irq(uic);
	485	break;
	486	case DCR_UICMSR:
	487	break;
	488	case DCR_UICVR:
	489	break;
	490	case DCR_UICVCR:
	491	uic->uicvcr = val & 0xFFFFFFFD;
	492	ppcuic_trigger_irq(uic);
	493	break;
	494	}
	495	}
	496
	497	static void ppcuic_reset (void *opaque)
	498	{
	499	ppcuic_t *uic;
	500
	501	uic = opaque;
	502	uic->uiccr = 0x00000000;
	503	uic->uicer = 0x00000000;
	504	uic->uicpr = 0x00000000;
	505	uic->uicsr = 0x00000000;
	506	uic->uictr = 0x00000000;
	507	if (uic->use_vectors) {
	508	uic->uicvcr = 0x00000000;
	509	uic->uicvr = 0x0000000;
	510	}
	511	}
	512
	513	qemu_irq ppcuic_init (CPUState env, qemu_irq *irqs,
	514	uint32_t dcr_base, int has_ssr, int has_vr)
	515	{
	516	ppcuic_t *uic;
	517	int i;
	518
	519	uic = qemu_mallocz(sizeof(ppcuic_t));
	520	if (uic != NULL) {
	521	uic->dcr_base = dcr_base;
	522	uic->irqs = irqs;
	523	if (has_vr)
	524	uic->use_vectors = 1;
	525	for (i = 0; i < DCR_UICMAX; i++) {
	526	ppc_dcr_register(env, dcr_base + i, uic,
	527	&dcr_read_uic, &dcr_write_uic);
	528	}
	529	qemu_register_reset(ppcuic_reset, uic);
	530	ppcuic_reset(uic);
	531	}
	532
	533	return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
	534	}