[qemu.git] / hw / ppc4xx_pci.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Copyright IBM Corp. 2008
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

/* This file implements emulation of the 32-bit PCI controller found in some
 * 4xx SoCs, such as the 440EP. */

#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"

typedef a_target_phys_addr a_pci_addr;
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"

#undef DEBUG
#ifdef DEBUG
#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif /* DEBUG */

struct PCIMasterMap {
    uint32_t la;
    uint32_t ma;
    uint32_t pcila;
    uint32_t pciha;
};

struct PCITargetMap {
    uint32_t ms;
    uint32_t la;
};

#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2

struct PPC4xxPCIState {
    struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
    struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];

    PCIHostState pci_state;
    PCIDevice *pci_dev;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
 * PCI accesses. */
#define PCIL0_PMM0LA        0x0
#define PCIL0_PMM0MA        0x4
#define PCIL0_PMM0PCILA     0x8
#define PCIL0_PMM0PCIHA     0xc
#define PCIL0_PMM1LA        0x10
#define PCIL0_PMM1MA        0x14
#define PCIL0_PMM1PCILA     0x18
#define PCIL0_PMM1PCIHA     0x1c
#define PCIL0_PMM2LA        0x20
#define PCIL0_PMM2MA        0x24
#define PCIL0_PMM2PCILA     0x28
#define PCIL0_PMM2PCIHA     0x2c

/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
 * PLB accesses. */
#define PCIL0_PTM1MS        0x30
#define PCIL0_PTM1LA        0x34
#define PCIL0_PTM2MS        0x38
#define PCIL0_PTM2LA        0x3c
#define PCI_REG_SIZE        0x40


static uint32_t pci4xx_cfgaddr_readl(void *opaque, a_target_phys_addr addr)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;

    return ppc4xx_pci->pci_state.config_reg;
}

static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
    &pci4xx_cfgaddr_readl,
    &pci4xx_cfgaddr_readl,
    &pci4xx_cfgaddr_readl,
};

static void pci4xx_cfgaddr_writel(void *opaque, a_target_phys_addr addr,
                                  uint32_t value)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;

#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif

    ppc4xx_pci->pci_state.config_reg = value & ~0x3;
}

static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
    &pci4xx_cfgaddr_writel,
    &pci4xx_cfgaddr_writel,
    &pci4xx_cfgaddr_writel,
};

static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset,
                                  uint32_t value)
{
    struct PPC4xxPCIState *pci = opaque;

#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif

    /* We ignore all target attempts at PCI configuration, effectively
     * assuming a bidirectional 1:1 mapping of PLB and PCI space. */

    switch (offset) {
    case PCIL0_PMM0LA:
        pci->pmm[0].la = value;
        break;
    case PCIL0_PMM0MA:
        pci->pmm[0].ma = value;
        break;
    case PCIL0_PMM0PCIHA:
        pci->pmm[0].pciha = value;
        break;
    case PCIL0_PMM0PCILA:
        pci->pmm[0].pcila = value;
        break;

    case PCIL0_PMM1LA:
        pci->pmm[1].la = value;
        break;
    case PCIL0_PMM1MA:
        pci->pmm[1].ma = value;
        break;
    case PCIL0_PMM1PCIHA:
        pci->pmm[1].pciha = value;
        break;
    case PCIL0_PMM1PCILA:
        pci->pmm[1].pcila = value;
        break;

    case PCIL0_PMM2LA:
        pci->pmm[2].la = value;
        break;
    case PCIL0_PMM2MA:
        pci->pmm[2].ma = value;
        break;
    case PCIL0_PMM2PCIHA:
        pci->pmm[2].pciha = value;
        break;
    case PCIL0_PMM2PCILA:
        pci->pmm[2].pcila = value;
        break;

    case PCIL0_PTM1MS:
        pci->ptm[0].ms = value;
        break;
    case PCIL0_PTM1LA:
        pci->ptm[0].la = value;
        break;
    case PCIL0_PTM2MS:
        pci->ptm[1].ms = value;
        break;
    case PCIL0_PTM2LA:
        pci->ptm[1].la = value;
        break;

    default:
        printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        break;
    }
}

static uint32_t ppc4xx_pci_reg_read4(void *opaque, a_target_phys_addr offset)
{
    struct PPC4xxPCIState *pci = opaque;
    uint32_t value;

    switch (offset) {
    case PCIL0_PMM0LA:
        value = pci->pmm[0].la;
        break;
    case PCIL0_PMM0MA:
        value = pci->pmm[0].ma;
        break;
    case PCIL0_PMM0PCIHA:
        value = pci->pmm[0].pciha;
        break;
    case PCIL0_PMM0PCILA:
        value = pci->pmm[0].pcila;
        break;

    case PCIL0_PMM1LA:
        value = pci->pmm[1].la;
        break;
    case PCIL0_PMM1MA:
        value = pci->pmm[1].ma;
        break;
    case PCIL0_PMM1PCIHA:
        value = pci->pmm[1].pciha;
        break;
    case PCIL0_PMM1PCILA:
        value = pci->pmm[1].pcila;
        break;

    case PCIL0_PMM2LA:
        value = pci->pmm[2].la;
        break;
    case PCIL0_PMM2MA:
        value = pci->pmm[2].ma;
        break;
    case PCIL0_PMM2PCIHA:
        value = pci->pmm[2].pciha;
        break;
    case PCIL0_PMM2PCILA:
        value = pci->pmm[2].pcila;
        break;

    case PCIL0_PTM1MS:
        value = pci->ptm[0].ms;
        break;
    case PCIL0_PTM1LA:
        value = pci->ptm[0].la;
        break;
    case PCIL0_PTM2MS:
        value = pci->ptm[1].ms;
        break;
    case PCIL0_PTM2LA:
        value = pci->ptm[1].la;
        break;

    default:
        printf("%s: invalid PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        value = 0;
    }

#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif

    return value;
}

static CPUReadMemoryFunc * const pci_reg_read[] = {
    &ppc4xx_pci_reg_read4,
    &ppc4xx_pci_reg_read4,
    &ppc4xx_pci_reg_read4,
};

static CPUWriteMemoryFunc * const pci_reg_write[] = {
    &ppc4xx_pci_reg_write4,
    &ppc4xx_pci_reg_write4,
    &ppc4xx_pci_reg_write4,
};

static void ppc4xx_pci_reset(void *opaque)
{
    struct PPC4xxPCIState *pci = opaque;

    memset(pci->pmm, 0, sizeof(pci->pmm));
    memset(pci->ptm, 0, sizeof(pci->ptm));
}

/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 * may need further refactoring for other boards. */
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot = pci_dev->devfn >> 3;

    DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
            pci_dev->devfn, irq_num, slot);

    return slot - 1;
}

static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irqs = opaque;

    DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
    qemu_set_irq(pci_irqs[irq_num], level);
}

static void ppc4xx_pci_save(QEMUFile *f, void *opaque)
{
    PPC4xxPCIState *controller = opaque;
    int i;

    pci_device_save(controller->pci_dev, f);

    for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
        qemu_put_be32s(f, &controller->pmm[i].la);
        qemu_put_be32s(f, &controller->pmm[i].ma);
        qemu_put_be32s(f, &controller->pmm[i].pcila);
        qemu_put_be32s(f, &controller->pmm[i].pciha);
    }

    for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
        qemu_put_be32s(f, &controller->ptm[i].ms);
        qemu_put_be32s(f, &controller->ptm[i].la);
    }
}

static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id)
{
    PPC4xxPCIState *controller = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    pci_device_load(controller->pci_dev, f);

    for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
        qemu_get_be32s(f, &controller->pmm[i].la);
        qemu_get_be32s(f, &controller->pmm[i].ma);
        qemu_get_be32s(f, &controller->pmm[i].pcila);
        qemu_get_be32s(f, &controller->pmm[i].pciha);
    }

    for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
        qemu_get_be32s(f, &controller->ptm[i].ms);
        qemu_get_be32s(f, &controller->ptm[i].la);
    }

    return 0;
}

/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
                        a_target_phys_addr config_space,
                        a_target_phys_addr int_ack,
                        a_target_phys_addr special_cycle,
                        a_target_phys_addr registers)
{
    PPC4xxPCIState *controller;
    int index;
    static int ppc4xx_pci_id;
    uint8_t *pci_conf;

    controller = qemu_mallocz(sizeof(PPC4xxPCIState));

    controller->pci_state.bus = pci_register_bus(NULL, "pci",
                                                 ppc4xx_pci_set_irq,
                                                 ppc4xx_pci_map_irq,
                                                 pci_irqs, 0, 4);

    controller->pci_dev = pci_register_device(controller->pci_state.bus,
                                              "host bridge", sizeof(PCIDevice),
                                              0, NULL, NULL);
    pci_conf = controller->pci_dev->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);

    /* CFGADDR */
    index = cpu_register_io_memory(pci4xx_cfgaddr_read,
                                   pci4xx_cfgaddr_write, controller);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);

    /* CFGDATA */
    index = cpu_register_io_memory(pci4xx_cfgdata_read,
                                   pci4xx_cfgdata_write,
                                   &controller->pci_state);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);

    /* Internal registers */
    index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

    qemu_register_reset(ppc4xx_pci_reset, controller);

    /* XXX load/save code not tested. */
    register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
                    ppc4xx_pci_save, ppc4xx_pci_load, controller);

    return controller->pci_state.bus;

free:
    printf("%s error\n", __func__);
    qemu_free(controller);
    return NULL;
}
Commit	Line	Data
825bb581 AJ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
8167ee88	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
825bb581 AJ	13	*
	14	* Copyright IBM Corp. 2008
	15	*
	16	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	17	*/
	18
	19	/* This file implements emulation of the 32-bit PCI controller found in some
	20	* 4xx SoCs, such as the 440EP. */
	21
	22	#include "hw.h"
0c34a5d7 AJ	23	#include "ppc.h"
0c34a5d7 AJ	24	#include "ppc4xx.h"
825bb581	25
99a0949b	26	typedef a_target_phys_addr a_pci_addr;
825bb581 AJ	27	#include "pci.h"
	28	#include "pci_host.h"
	29	#include "bswap.h"
	30
	31	#undef DEBUG
	32	#ifdef DEBUG
	33	#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
	34	#else
001faf32	35	#define DPRINTF(fmt, ...)
825bb581 AJ	36	#endif /* DEBUG */
	37
	38	struct PCIMasterMap {
	39	uint32_t la;
	40	uint32_t ma;
	41	uint32_t pcila;
	42	uint32_t pciha;
	43	};
	44
	45	struct PCITargetMap {
	46	uint32_t ms;
	47	uint32_t la;
	48	};
	49
	50	#define PPC4xx_PCI_NR_PMMS 3
	51	#define PPC4xx_PCI_NR_PTMS 2
	52
	53	struct PPC4xxPCIState {
	54	struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
	55	struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
	56
	57	PCIHostState pci_state;
	58	PCIDevice *pci_dev;
	59	};
	60	typedef struct PPC4xxPCIState PPC4xxPCIState;
	61
	62	#define PCIC0_CFGADDR 0x0
	63	#define PCIC0_CFGDATA 0x4
	64
	65	/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
	66	* PCI accesses. */
	67	#define PCIL0_PMM0LA 0x0
	68	#define PCIL0_PMM0MA 0x4
	69	#define PCIL0_PMM0PCILA 0x8
	70	#define PCIL0_PMM0PCIHA 0xc
	71	#define PCIL0_PMM1LA 0x10
	72	#define PCIL0_PMM1MA 0x14
	73	#define PCIL0_PMM1PCILA 0x18
	74	#define PCIL0_PMM1PCIHA 0x1c
	75	#define PCIL0_PMM2LA 0x20
	76	#define PCIL0_PMM2MA 0x24
	77	#define PCIL0_PMM2PCILA 0x28
	78	#define PCIL0_PMM2PCIHA 0x2c
	79
	80	/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
	81	* PLB accesses. */
	82	#define PCIL0_PTM1MS 0x30
	83	#define PCIL0_PTM1LA 0x34
	84	#define PCIL0_PTM2MS 0x38
	85	#define PCIL0_PTM2LA 0x3c
	86	#define PCI_REG_SIZE 0x40
	87
	88
99a0949b	89	static uint32_t pci4xx_cfgaddr_readl(void *opaque, a_target_phys_addr addr)
825bb581 AJ	90	{
	91	PPC4xxPCIState *ppc4xx_pci = opaque;
	92
	93	return ppc4xx_pci->pci_state.config_reg;
	94	}
	95
d60efc6b	96	static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
825bb581 AJ	97	&pci4xx_cfgaddr_readl,
	98	&pci4xx_cfgaddr_readl,
	99	&pci4xx_cfgaddr_readl,
	100	};
	101
99a0949b	102	static void pci4xx_cfgaddr_writel(void *opaque, a_target_phys_addr addr,
825bb581 AJ	103	uint32_t value)
	104	{
	105	PPC4xxPCIState *ppc4xx_pci = opaque;
	106
	107	#ifdef TARGET_WORDS_BIGENDIAN
	108	value = bswap32(value);
	109	#endif
	110
	111	ppc4xx_pci->pci_state.config_reg = value & ~0x3;
	112	}
	113
d60efc6b	114	static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
825bb581 AJ	115	&pci4xx_cfgaddr_writel,
	116	&pci4xx_cfgaddr_writel,
	117	&pci4xx_cfgaddr_writel,
	118	};
	119
d60efc6b	120	static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = {
825bb581 AJ	121	&pci_host_data_readb,
	122	&pci_host_data_readw,
	123	&pci_host_data_readl,
	124	};
	125
d60efc6b	126	static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
825bb581 AJ	127	&pci_host_data_writeb,
	128	&pci_host_data_writew,
	129	&pci_host_data_writel,
	130	};
	131
99a0949b	132	static void ppc4xx_pci_reg_write4(void *opaque, a_target_phys_addr offset,
825bb581 AJ	133	uint32_t value)
	134	{
	135	struct PPC4xxPCIState *pci = opaque;
	136
	137	#ifdef TARGET_WORDS_BIGENDIAN
	138	value = bswap32(value);
	139	#endif
	140
	141	/* We ignore all target attempts at PCI configuration, effectively
	142	* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
	143
	144	switch (offset) {
	145	case PCIL0_PMM0LA:
	146	pci->pmm[0].la = value;
	147	break;
	148	case PCIL0_PMM0MA:
	149	pci->pmm[0].ma = value;
	150	break;
	151	case PCIL0_PMM0PCIHA:
	152	pci->pmm[0].pciha = value;
	153	break;
	154	case PCIL0_PMM0PCILA:
	155	pci->pmm[0].pcila = value;
	156	break;
	157
	158	case PCIL0_PMM1LA:
	159	pci->pmm[1].la = value;
	160	break;
	161	case PCIL0_PMM1MA:
	162	pci->pmm[1].ma = value;
	163	break;
	164	case PCIL0_PMM1PCIHA:
	165	pci->pmm[1].pciha = value;
	166	break;
	167	case PCIL0_PMM1PCILA:
	168	pci->pmm[1].pcila = value;
	169	break;
	170
	171	case PCIL0_PMM2LA:
	172	pci->pmm[2].la = value;
	173	break;
	174	case PCIL0_PMM2MA:
	175	pci->pmm[2].ma = value;
	176	break;
	177	case PCIL0_PMM2PCIHA:
	178	pci->pmm[2].pciha = value;
	179	break;
	180	case PCIL0_PMM2PCILA:
	181	pci->pmm[2].pcila = value;
	182	break;
	183
	184	case PCIL0_PTM1MS:
	185	pci->ptm[0].ms = value;
	186	break;
	187	case PCIL0_PTM1LA:
	188	pci->ptm[0].la = value;
	189	break;
	190	case PCIL0_PTM2MS:
	191	pci->ptm[1].ms = value;
	192	break;
	193	case PCIL0_PTM2LA:
	194	pci->ptm[1].la = value;
	195	break;
	196
197	default:
198	printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
199	(unsigned long)offset);
200	break;
201	}
202	}
203
99a0949b	204	static uint32_t ppc4xx_pci_reg_read4(void *opaque, a_target_phys_addr offset)
825bb581 AJ	205	{
	206	struct PPC4xxPCIState *pci = opaque;
	207	uint32_t value;
	208
	209	switch (offset) {
	210	case PCIL0_PMM0LA:
	211	value = pci->pmm[0].la;
	212	break;
	213	case PCIL0_PMM0MA:
	214	value = pci->pmm[0].ma;
	215	break;
	216	case PCIL0_PMM0PCIHA:
	217	value = pci->pmm[0].pciha;
	218	break;
	219	case PCIL0_PMM0PCILA:
	220	value = pci->pmm[0].pcila;
	221	break;
	222
	223	case PCIL0_PMM1LA:
	224	value = pci->pmm[1].la;
	225	break;
	226	case PCIL0_PMM1MA:
	227	value = pci->pmm[1].ma;
	228	break;
	229	case PCIL0_PMM1PCIHA:
	230	value = pci->pmm[1].pciha;
	231	break;
	232	case PCIL0_PMM1PCILA:
	233	value = pci->pmm[1].pcila;
	234	break;
	235
	236	case PCIL0_PMM2LA:
	237	value = pci->pmm[2].la;
	238	break;
	239	case PCIL0_PMM2MA:
	240	value = pci->pmm[2].ma;
	241	break;
	242	case PCIL0_PMM2PCIHA:
	243	value = pci->pmm[2].pciha;
	244	break;
	245	case PCIL0_PMM2PCILA:
	246	value = pci->pmm[2].pcila;
	247	break;
	248
	249	case PCIL0_PTM1MS:
	250	value = pci->ptm[0].ms;
	251	break;
	252	case PCIL0_PTM1LA:
	253	value = pci->ptm[0].la;
	254	break;
	255	case PCIL0_PTM2MS:
	256	value = pci->ptm[1].ms;
	257	break;
	258	case PCIL0_PTM2LA:
	259	value = pci->ptm[1].la;
	260	break;
	261
	262	default:
	263	printf("%s: invalid PCI internal register 0x%lx\n", __func__,
	264	(unsigned long)offset);
	265	value = 0;
	266	}
	267
	268	#ifdef TARGET_WORDS_BIGENDIAN
269	value = bswap32(value);
270	#endif
271
272	return value;
273	}
274
d60efc6b	275	static CPUReadMemoryFunc * const pci_reg_read[] = {
825bb581 AJ	276	&ppc4xx_pci_reg_read4,
	277	&ppc4xx_pci_reg_read4,
	278	&ppc4xx_pci_reg_read4,
	279	};
	280
d60efc6b	281	static CPUWriteMemoryFunc * const pci_reg_write[] = {
825bb581 AJ	282	&ppc4xx_pci_reg_write4,
	283	&ppc4xx_pci_reg_write4,
	284	&ppc4xx_pci_reg_write4,
	285	};
	286
	287	static void ppc4xx_pci_reset(void *opaque)
	288	{
	289	struct PPC4xxPCIState *pci = opaque;
	290
	291	memset(pci->pmm, 0, sizeof(pci->pmm));
	292	memset(pci->ptm, 0, sizeof(pci->ptm));
	293	}
	294
	295	/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
	296	* may need further refactoring for other boards. */
	297	static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	298	{
	299	int slot = pci_dev->devfn >> 3;
	300
	301	DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
	302	pci_dev->devfn, irq_num, slot);
	303
	304	return slot - 1;
	305	}
	306
5d4e84c8	307	static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
825bb581	308	{
5d4e84c8 JQ	309	qemu_irq *pci_irqs = opaque;
5d4e84c8 JQ	310
825bb581 AJ	311	DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
	312	qemu_set_irq(pci_irqs[irq_num], level);
	313	}
	314
	315	static void ppc4xx_pci_save(QEMUFile f, void opaque)
	316	{
	317	PPC4xxPCIState *controller = opaque;
	318	int i;
	319
3476f891	320	pci_device_save(controller->pci_dev, f);
825bb581 AJ	321
	322	for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
	323	qemu_put_be32s(f, &controller->pmm[i].la);
	324	qemu_put_be32s(f, &controller->pmm[i].ma);
	325	qemu_put_be32s(f, &controller->pmm[i].pcila);
	326	qemu_put_be32s(f, &controller->pmm[i].pciha);
	327	}
	328
	329	for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
	330	qemu_put_be32s(f, &controller->ptm[i].ms);
	331	qemu_put_be32s(f, &controller->ptm[i].la);
	332	}
	333	}
	334
	335	static int ppc4xx_pci_load(QEMUFile f, void opaque, int version_id)
	336	{
	337	PPC4xxPCIState *controller = opaque;
	338	int i;
	339
	340	if (version_id != 1)
	341	return -EINVAL;
	342
3476f891	343	pci_device_load(controller->pci_dev, f);
825bb581 AJ	344
	345	for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) {
	346	qemu_get_be32s(f, &controller->pmm[i].la);
	347	qemu_get_be32s(f, &controller->pmm[i].ma);
	348	qemu_get_be32s(f, &controller->pmm[i].pcila);
	349	qemu_get_be32s(f, &controller->pmm[i].pciha);
	350	}
	351
	352	for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) {
	353	qemu_get_be32s(f, &controller->ptm[i].ms);
	354	qemu_get_be32s(f, &controller->ptm[i].la);
	355	}
	356
	357	return 0;
	358	}
	359
	360	/* XXX Interrupt acknowledge cycles not supported. */
	361	PCIBus ppc4xx_pci_init(CPUState env, qemu_irq pci_irqs[4],
99a0949b	362	a_target_phys_addr config_space,
	363	a_target_phys_addr int_ack,
	364	a_target_phys_addr special_cycle,
	365	a_target_phys_addr registers)
825bb581 AJ	366	{
	367	PPC4xxPCIState *controller;
	368	int index;
	369	static int ppc4xx_pci_id;
deb54399	370	uint8_t *pci_conf;
825bb581 AJ	371
825bb581 AJ	372	controller = qemu_mallocz(sizeof(PPC4xxPCIState));
825bb581	373
02e2da45 PB	374	controller->pci_state.bus = pci_register_bus(NULL, "pci",
02e2da45 PB	375	ppc4xx_pci_set_irq,
825bb581 AJ	376	ppc4xx_pci_map_irq,
	377	pci_irqs, 0, 4);
	378
	379	controller->pci_dev = pci_register_device(controller->pci_state.bus,
	380	"host bridge", sizeof(PCIDevice),
	381	0, NULL, NULL);
deb54399 AL	382	pci_conf = controller->pci_dev->config;
deb54399 AL	383	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
a770dc7e	384	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
173a543b	385	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
825bb581 AJ	386
825bb581 AJ	387	/* CFGADDR */
1eed09cb	388	index = cpu_register_io_memory(pci4xx_cfgaddr_read,
825bb581 AJ	389	pci4xx_cfgaddr_write, controller);
	390	if (index < 0)
	391	goto free;
	392	cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
	393
	394	/* CFGDATA */
1eed09cb	395	index = cpu_register_io_memory(pci4xx_cfgdata_read,
825bb581 AJ	396	pci4xx_cfgdata_write,
	397	&controller->pci_state);
	398	if (index < 0)
	399	goto free;
	400	cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
	401
	402	/* Internal registers */
1eed09cb	403	index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
825bb581 AJ	404	if (index < 0)
	405	goto free;
	406	cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
	407
a08d4367	408	qemu_register_reset(ppc4xx_pci_reset, controller);
825bb581 AJ	409
	410	/* XXX load/save code not tested. */
	411	register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,
	412	ppc4xx_pci_save, ppc4xx_pci_load, controller);
	413
	414	return controller->pci_state.bus;
	415
	416	free:
	417	printf("%s error\n", __func__);
	418	qemu_free(controller);
	419	return NULL;
	420	}