[qemu.git] / hw / ppc4xx_pci.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Copyright IBM Corp. 2008
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

/* This file implements emulation of the 32-bit PCI controller found in some
 * 4xx SoCs, such as the 440EP. */

#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
#include "pci.h"
#include "pci_host.h"
#include "exec-memory.h"

#undef DEBUG
#ifdef DEBUG
#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif /* DEBUG */

struct PCIMasterMap {
    uint32_t la;
    uint32_t ma;
    uint32_t pcila;
    uint32_t pciha;
};

struct PCITargetMap {
    uint32_t ms;
    uint32_t la;
};

#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2

struct PPC4xxPCIState {
    struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
    struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];

    PCIHostState pci_state;
    PCIDevice *pci_dev;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
 * PCI accesses. */
#define PCIL0_PMM0LA        0x0
#define PCIL0_PMM0MA        0x4
#define PCIL0_PMM0PCILA     0x8
#define PCIL0_PMM0PCIHA     0xc
#define PCIL0_PMM1LA        0x10
#define PCIL0_PMM1MA        0x14
#define PCIL0_PMM1PCILA     0x18
#define PCIL0_PMM1PCIHA     0x1c
#define PCIL0_PMM2LA        0x20
#define PCIL0_PMM2MA        0x24
#define PCIL0_PMM2PCILA     0x28
#define PCIL0_PMM2PCIHA     0x2c

/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
 * PLB accesses. */
#define PCIL0_PTM1MS        0x30
#define PCIL0_PTM1LA        0x34
#define PCIL0_PTM2MS        0x38
#define PCIL0_PTM2LA        0x3c
#define PCI_REG_SIZE        0x40


static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;

    return ppc4xx_pci->pci_state.config_reg;
}

static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
    &pci4xx_cfgaddr_readl,
    &pci4xx_cfgaddr_readl,
    &pci4xx_cfgaddr_readl,
};

static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
                                  uint32_t value)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;

    ppc4xx_pci->pci_state.config_reg = value & ~0x3;
}

static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
    &pci4xx_cfgaddr_writel,
    &pci4xx_cfgaddr_writel,
    &pci4xx_cfgaddr_writel,
};

static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
                                  uint32_t value)
{
    struct PPC4xxPCIState *pci = opaque;

    /* We ignore all target attempts at PCI configuration, effectively
     * assuming a bidirectional 1:1 mapping of PLB and PCI space. */

    switch (offset) {
    case PCIL0_PMM0LA:
        pci->pmm[0].la = value;
        break;
    case PCIL0_PMM0MA:
        pci->pmm[0].ma = value;
        break;
    case PCIL0_PMM0PCIHA:
        pci->pmm[0].pciha = value;
        break;
    case PCIL0_PMM0PCILA:
        pci->pmm[0].pcila = value;
        break;

    case PCIL0_PMM1LA:
        pci->pmm[1].la = value;
        break;
    case PCIL0_PMM1MA:
        pci->pmm[1].ma = value;
        break;
    case PCIL0_PMM1PCIHA:
        pci->pmm[1].pciha = value;
        break;
    case PCIL0_PMM1PCILA:
        pci->pmm[1].pcila = value;
        break;

    case PCIL0_PMM2LA:
        pci->pmm[2].la = value;
        break;
    case PCIL0_PMM2MA:
        pci->pmm[2].ma = value;
        break;
    case PCIL0_PMM2PCIHA:
        pci->pmm[2].pciha = value;
        break;
    case PCIL0_PMM2PCILA:
        pci->pmm[2].pcila = value;
        break;

    case PCIL0_PTM1MS:
        pci->ptm[0].ms = value;
        break;
    case PCIL0_PTM1LA:
        pci->ptm[0].la = value;
        break;
    case PCIL0_PTM2MS:
        pci->ptm[1].ms = value;
        break;
    case PCIL0_PTM2LA:
        pci->ptm[1].la = value;
        break;

    default:
        printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        break;
    }
}

static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
{
    struct PPC4xxPCIState *pci = opaque;
    uint32_t value;

    switch (offset) {
    case PCIL0_PMM0LA:
        value = pci->pmm[0].la;
        break;
    case PCIL0_PMM0MA:
        value = pci->pmm[0].ma;
        break;
    case PCIL0_PMM0PCIHA:
        value = pci->pmm[0].pciha;
        break;
    case PCIL0_PMM0PCILA:
        value = pci->pmm[0].pcila;
        break;

    case PCIL0_PMM1LA:
        value = pci->pmm[1].la;
        break;
    case PCIL0_PMM1MA:
        value = pci->pmm[1].ma;
        break;
    case PCIL0_PMM1PCIHA:
        value = pci->pmm[1].pciha;
        break;
    case PCIL0_PMM1PCILA:
        value = pci->pmm[1].pcila;
        break;

    case PCIL0_PMM2LA:
        value = pci->pmm[2].la;
        break;
    case PCIL0_PMM2MA:
        value = pci->pmm[2].ma;
        break;
    case PCIL0_PMM2PCIHA:
        value = pci->pmm[2].pciha;
        break;
    case PCIL0_PMM2PCILA:
        value = pci->pmm[2].pcila;
        break;

    case PCIL0_PTM1MS:
        value = pci->ptm[0].ms;
        break;
    case PCIL0_PTM1LA:
        value = pci->ptm[0].la;
        break;
    case PCIL0_PTM2MS:
        value = pci->ptm[1].ms;
        break;
    case PCIL0_PTM2LA:
        value = pci->ptm[1].la;
        break;

    default:
        printf("%s: invalid PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        value = 0;
    }

    return value;
}

static CPUReadMemoryFunc * const pci_reg_read[] = {
    &ppc4xx_pci_reg_read4,
    &ppc4xx_pci_reg_read4,
    &ppc4xx_pci_reg_read4,
};

static CPUWriteMemoryFunc * const pci_reg_write[] = {
    &ppc4xx_pci_reg_write4,
    &ppc4xx_pci_reg_write4,
    &ppc4xx_pci_reg_write4,
};

static void ppc4xx_pci_reset(void *opaque)
{
    struct PPC4xxPCIState *pci = opaque;

    memset(pci->pmm, 0, sizeof(pci->pmm));
    memset(pci->ptm, 0, sizeof(pci->ptm));
}

/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 * may need further refactoring for other boards. */
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot = pci_dev->devfn >> 3;

    DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
            pci_dev->devfn, irq_num, slot);

    return slot - 1;
}

static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irqs = opaque;

    DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
    qemu_set_irq(pci_irqs[irq_num], level);
}

static const VMStateDescription vmstate_pci_master_map = {
    .name = "pci_master_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(la, struct PCIMasterMap),
        VMSTATE_UINT32(ma, struct PCIMasterMap),
        VMSTATE_UINT32(pcila, struct PCIMasterMap),
        VMSTATE_UINT32(pciha, struct PCIMasterMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_target_map = {
    .name = "pci_target_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(ms, struct PCITargetMap),
        VMSTATE_UINT32(la, struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppc4xx_pci = {
    .name = "ppc4xx_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState),
        VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
                             vmstate_pci_master_map,
                             struct PCIMasterMap),
        VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
                             vmstate_pci_target_map,
                             struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
                        target_phys_addr_t config_space,
                        target_phys_addr_t int_ack,
                        target_phys_addr_t special_cycle,
                        target_phys_addr_t registers)
{
    PPC4xxPCIState *controller;
    int index;
    static int ppc4xx_pci_id;
    uint8_t *pci_conf;

    controller = g_malloc0(sizeof(PPC4xxPCIState));

    controller->pci_state.bus = pci_register_bus(NULL, "pci",
                                                 ppc4xx_pci_set_irq,
                                                 ppc4xx_pci_map_irq,
                                                 pci_irqs,
                                                 get_system_memory(),
                                                 get_system_io(),
                                                 0, 4);

    controller->pci_dev = pci_register_device(controller->pci_state.bus,
                                              "host bridge", sizeof(PCIDevice),
                                              0, NULL, NULL);
    pci_conf = controller->pci_dev->config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);

    /* CFGADDR */
    index = cpu_register_io_memory(pci4xx_cfgaddr_read,
                                   pci4xx_cfgaddr_write, controller,
                                   DEVICE_LITTLE_ENDIAN);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);

    /* CFGDATA */
    memory_region_init_io(&controller->pci_state.data_mem,
                          &pci_host_data_be_ops,
                          &controller->pci_state, "pci-conf-data", 4);
    memory_region_add_subregion(get_system_memory(),
                                config_space + PCIC0_CFGDATA,
                                &controller->pci_state.data_mem);

    /* Internal registers */
    index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
                                   DEVICE_LITTLE_ENDIAN);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

    qemu_register_reset(ppc4xx_pci_reset, controller);

    /* XXX load/save code not tested. */
    vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++,
                     &vmstate_ppc4xx_pci, controller);

    return controller->pci_state.bus;

free:
    printf("%s error\n", __func__);
    g_free(controller);
    return NULL;
}
Commit	Line	Data
825bb581 AJ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
8167ee88	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
825bb581 AJ	13	*
	14	* Copyright IBM Corp. 2008
	15	*
	16	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	17	*/
	18
	19	/* This file implements emulation of the 32-bit PCI controller found in some
	20	* 4xx SoCs, such as the 440EP. */
	21
	22	#include "hw.h"
0c34a5d7 AJ	23	#include "ppc.h"
0c34a5d7 AJ	24	#include "ppc4xx.h"
825bb581 AJ	25	#include "pci.h"
825bb581 AJ	26	#include "pci_host.h"
1e39101c	27	#include "exec-memory.h"
825bb581 AJ	28
	29	#undef DEBUG
	30	#ifdef DEBUG
	31	#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
	32	#else
001faf32	33	#define DPRINTF(fmt, ...)
825bb581 AJ	34	#endif /* DEBUG */
	35
	36	struct PCIMasterMap {
	37	uint32_t la;
	38	uint32_t ma;
	39	uint32_t pcila;
	40	uint32_t pciha;
	41	};
	42
	43	struct PCITargetMap {
	44	uint32_t ms;
	45	uint32_t la;
	46	};
	47
	48	#define PPC4xx_PCI_NR_PMMS 3
	49	#define PPC4xx_PCI_NR_PTMS 2
	50
	51	struct PPC4xxPCIState {
	52	struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
	53	struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
	54
	55	PCIHostState pci_state;
	56	PCIDevice *pci_dev;
	57	};
	58	typedef struct PPC4xxPCIState PPC4xxPCIState;
	59
	60	#define PCIC0_CFGADDR 0x0
	61	#define PCIC0_CFGDATA 0x4
	62
	63	/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
	64	* PCI accesses. */
	65	#define PCIL0_PMM0LA 0x0
	66	#define PCIL0_PMM0MA 0x4
	67	#define PCIL0_PMM0PCILA 0x8
	68	#define PCIL0_PMM0PCIHA 0xc
	69	#define PCIL0_PMM1LA 0x10
	70	#define PCIL0_PMM1MA 0x14
	71	#define PCIL0_PMM1PCILA 0x18
	72	#define PCIL0_PMM1PCIHA 0x1c
	73	#define PCIL0_PMM2LA 0x20
	74	#define PCIL0_PMM2MA 0x24
	75	#define PCIL0_PMM2PCILA 0x28
	76	#define PCIL0_PMM2PCIHA 0x2c
	77
	78	/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
	79	* PLB accesses. */
	80	#define PCIL0_PTM1MS 0x30
	81	#define PCIL0_PTM1LA 0x34
	82	#define PCIL0_PTM2MS 0x38
	83	#define PCIL0_PTM2LA 0x3c
	84	#define PCI_REG_SIZE 0x40
	85
	86
c227f099	87	static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
825bb581 AJ	88	{
	89	PPC4xxPCIState *ppc4xx_pci = opaque;
	90
	91	return ppc4xx_pci->pci_state.config_reg;
	92	}
	93
d60efc6b	94	static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
825bb581 AJ	95	&pci4xx_cfgaddr_readl,
	96	&pci4xx_cfgaddr_readl,
	97	&pci4xx_cfgaddr_readl,
	98	};
	99
c227f099	100	static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
825bb581 AJ	101	uint32_t value)
	102	{
	103	PPC4xxPCIState *ppc4xx_pci = opaque;
	104
825bb581 AJ	105	ppc4xx_pci->pci_state.config_reg = value & ~0x3;
	106	}
	107
d60efc6b	108	static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
825bb581 AJ	109	&pci4xx_cfgaddr_writel,
	110	&pci4xx_cfgaddr_writel,
	111	&pci4xx_cfgaddr_writel,
	112	};
	113
c227f099	114	static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
825bb581 AJ	115	uint32_t value)
	116	{
	117	struct PPC4xxPCIState *pci = opaque;
	118
825bb581 AJ	119	/* We ignore all target attempts at PCI configuration, effectively
	120	* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
	121
	122	switch (offset) {
	123	case PCIL0_PMM0LA:
	124	pci->pmm[0].la = value;
	125	break;
	126	case PCIL0_PMM0MA:
	127	pci->pmm[0].ma = value;
	128	break;
	129	case PCIL0_PMM0PCIHA:
	130	pci->pmm[0].pciha = value;
	131	break;
	132	case PCIL0_PMM0PCILA:
	133	pci->pmm[0].pcila = value;
	134	break;
	135
	136	case PCIL0_PMM1LA:
	137	pci->pmm[1].la = value;
	138	break;
	139	case PCIL0_PMM1MA:
	140	pci->pmm[1].ma = value;
	141	break;
	142	case PCIL0_PMM1PCIHA:
	143	pci->pmm[1].pciha = value;
	144	break;
	145	case PCIL0_PMM1PCILA:
	146	pci->pmm[1].pcila = value;
	147	break;
	148
	149	case PCIL0_PMM2LA:
	150	pci->pmm[2].la = value;
	151	break;
	152	case PCIL0_PMM2MA:
	153	pci->pmm[2].ma = value;
	154	break;
	155	case PCIL0_PMM2PCIHA:
	156	pci->pmm[2].pciha = value;
	157	break;
	158	case PCIL0_PMM2PCILA:
	159	pci->pmm[2].pcila = value;
	160	break;
	161
	162	case PCIL0_PTM1MS:
	163	pci->ptm[0].ms = value;
	164	break;
	165	case PCIL0_PTM1LA:
	166	pci->ptm[0].la = value;
	167	break;
	168	case PCIL0_PTM2MS:
	169	pci->ptm[1].ms = value;
	170	break;
	171	case PCIL0_PTM2LA:
	172	pci->ptm[1].la = value;
	173	break;
	174
	175	default:
	176	printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
	177	(unsigned long)offset);
	178	break;
	179	}
	180	}
	181
c227f099	182	static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
825bb581 AJ	183	{
	184	struct PPC4xxPCIState *pci = opaque;
	185	uint32_t value;
	186
	187	switch (offset) {
	188	case PCIL0_PMM0LA:
	189	value = pci->pmm[0].la;
	190	break;
	191	case PCIL0_PMM0MA:
	192	value = pci->pmm[0].ma;
	193	break;
	194	case PCIL0_PMM0PCIHA:
	195	value = pci->pmm[0].pciha;
	196	break;
	197	case PCIL0_PMM0PCILA:
	198	value = pci->pmm[0].pcila;
	199	break;
	200
	201	case PCIL0_PMM1LA:
	202	value = pci->pmm[1].la;
	203	break;
	204	case PCIL0_PMM1MA:
	205	value = pci->pmm[1].ma;
	206	break;
	207	case PCIL0_PMM1PCIHA:
	208	value = pci->pmm[1].pciha;
	209	break;
	210	case PCIL0_PMM1PCILA:
	211	value = pci->pmm[1].pcila;
	212	break;
	213
	214	case PCIL0_PMM2LA:
	215	value = pci->pmm[2].la;
	216	break;
	217	case PCIL0_PMM2MA:
	218	value = pci->pmm[2].ma;
	219	break;
	220	case PCIL0_PMM2PCIHA:
	221	value = pci->pmm[2].pciha;
	222	break;
	223	case PCIL0_PMM2PCILA:
	224	value = pci->pmm[2].pcila;
	225	break;
	226
	227	case PCIL0_PTM1MS:
	228	value = pci->ptm[0].ms;
	229	break;
	230	case PCIL0_PTM1LA:
	231	value = pci->ptm[0].la;
	232	break;
	233	case PCIL0_PTM2MS:
	234	value = pci->ptm[1].ms;
	235	break;
	236	case PCIL0_PTM2LA:
	237	value = pci->ptm[1].la;
	238	break;
	239
	240	default:
	241	printf("%s: invalid PCI internal register 0x%lx\n", __func__,
	242	(unsigned long)offset);
	243	value = 0;
	244	}
	245
825bb581 AJ	246	return value;
	247	}
	248
d60efc6b	249	static CPUReadMemoryFunc * const pci_reg_read[] = {
825bb581 AJ	250	&ppc4xx_pci_reg_read4,
	251	&ppc4xx_pci_reg_read4,
	252	&ppc4xx_pci_reg_read4,
	253	};
	254
d60efc6b	255	static CPUWriteMemoryFunc * const pci_reg_write[] = {
825bb581 AJ	256	&ppc4xx_pci_reg_write4,
	257	&ppc4xx_pci_reg_write4,
	258	&ppc4xx_pci_reg_write4,
	259	};
	260
	261	static void ppc4xx_pci_reset(void *opaque)
	262	{
	263	struct PPC4xxPCIState *pci = opaque;
	264
	265	memset(pci->pmm, 0, sizeof(pci->pmm));
	266	memset(pci->ptm, 0, sizeof(pci->ptm));
	267	}
	268
	269	/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
	270	* may need further refactoring for other boards. */
	271	static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	272	{
	273	int slot = pci_dev->devfn >> 3;
	274
	275	DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
	276	pci_dev->devfn, irq_num, slot);
	277
	278	return slot - 1;
	279	}
	280
5d4e84c8	281	static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
825bb581	282	{
5d4e84c8 JQ	283	qemu_irq *pci_irqs = opaque;
5d4e84c8 JQ	284
825bb581 AJ	285	DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
	286	qemu_set_irq(pci_irqs[irq_num], level);
	287	}
	288
b605f222 JQ	289	static const VMStateDescription vmstate_pci_master_map = {
	290	.name = "pci_master_map",
	291	.version_id = 0,
	292	.minimum_version_id = 0,
	293	.minimum_version_id_old = 0,
	294	.fields = (VMStateField[]) {
	295	VMSTATE_UINT32(la, struct PCIMasterMap),
	296	VMSTATE_UINT32(ma, struct PCIMasterMap),
	297	VMSTATE_UINT32(pcila, struct PCIMasterMap),
	298	VMSTATE_UINT32(pciha, struct PCIMasterMap),
	299	VMSTATE_END_OF_LIST()
825bb581	300	}
b605f222	301	};
825bb581	302
b605f222 JQ	303	static const VMStateDescription vmstate_pci_target_map = {
	304	.name = "pci_target_map",
	305	.version_id = 0,
	306	.minimum_version_id = 0,
	307	.minimum_version_id_old = 0,
	308	.fields = (VMStateField[]) {
	309	VMSTATE_UINT32(ms, struct PCITargetMap),
	310	VMSTATE_UINT32(la, struct PCITargetMap),
	311	VMSTATE_END_OF_LIST()
825bb581	312	}
b605f222	313	};
825bb581	314
b605f222 JQ	315	static const VMStateDescription vmstate_ppc4xx_pci = {
	316	.name = "ppc4xx_pci",
	317	.version_id = 1,
	318	.minimum_version_id = 1,
	319	.minimum_version_id_old = 1,
	320	.fields = (VMStateField[]) {
	321	VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPC4xxPCIState),
	322	VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
	323	vmstate_pci_master_map,
	324	struct PCIMasterMap),
	325	VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
	326	vmstate_pci_target_map,
	327	struct PCITargetMap),
	328	VMSTATE_END_OF_LIST()
825bb581	329	}
b605f222	330	};
825bb581 AJ	331
	332	/* XXX Interrupt acknowledge cycles not supported. */
	333	PCIBus ppc4xx_pci_init(CPUState env, qemu_irq pci_irqs[4],
c227f099 AL	334	target_phys_addr_t config_space,
	335	target_phys_addr_t int_ack,
	336	target_phys_addr_t special_cycle,
	337	target_phys_addr_t registers)
825bb581 AJ	338	{
	339	PPC4xxPCIState *controller;
	340	int index;
	341	static int ppc4xx_pci_id;
deb54399	342	uint8_t *pci_conf;
825bb581	343
7267c094	344	controller = g_malloc0(sizeof(PPC4xxPCIState));
825bb581	345
02e2da45 PB	346	controller->pci_state.bus = pci_register_bus(NULL, "pci",
02e2da45 PB	347	ppc4xx_pci_set_irq,
825bb581	348	ppc4xx_pci_map_irq,
1e39101c AK	349	pci_irqs,
1e39101c AK	350	get_system_memory(),
aee97b84	351	get_system_io(),
1e39101c	352	0, 4);
825bb581 AJ	353
	354	controller->pci_dev = pci_register_device(controller->pci_state.bus,
	355	"host bridge", sizeof(PCIDevice),
	356	0, NULL, NULL);
deb54399 AL	357	pci_conf = controller->pci_dev->config;
deb54399 AL	358	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
a770dc7e	359	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
173a543b	360	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
825bb581 AJ	361
825bb581 AJ	362	/* CFGADDR */
1eed09cb	363	index = cpu_register_io_memory(pci4xx_cfgaddr_read,
2507c12a	364	pci4xx_cfgaddr_write, controller,
0d2a73b3	365	DEVICE_LITTLE_ENDIAN);
825bb581 AJ	366	if (index < 0)
	367	goto free;
	368	cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
	369
	370	/* CFGDATA */
d0ed8076 AK	371	memory_region_init_io(&controller->pci_state.data_mem,
	372	&pci_host_data_be_ops,
	373	&controller->pci_state, "pci-conf-data", 4);
	374	memory_region_add_subregion(get_system_memory(),
	375	config_space + PCIC0_CFGDATA,
	376	&controller->pci_state.data_mem);
825bb581 AJ	377
825bb581 AJ	378	/* Internal registers */
2507c12a	379	index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
0d2a73b3	380	DEVICE_LITTLE_ENDIAN);
825bb581 AJ	381	if (index < 0)
	382	goto free;
	383	cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
	384
a08d4367	385	qemu_register_reset(ppc4xx_pci_reset, controller);
825bb581 AJ	386
825bb581 AJ	387	/* XXX load/save code not tested. */
b605f222 JQ	388	vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++,
b605f222 JQ	389	&vmstate_ppc4xx_pci, controller);
825bb581 AJ	390
	391	return controller->pci_state.bus;
	392
	393	free:
	394	printf("%s error\n", __func__);
7267c094	395	g_free(controller);
825bb581 AJ	396	return NULL;
825bb581 AJ	397	}