[qemu.git] / hw / ppc_chrp.c

/*
 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "ppc_mac.h"

/* UniN device */
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *unin_write[] = {
    &unin_writel,
    &unin_writel,
    &unin_writel,
};

static CPUReadMemoryFunc *unin_read[] = {
    &unin_readl,
    &unin_readl,
    &unin_readl,
};

/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
                             DisplayState *ds, const char **fd_filename,
                             int snapshot,
                             const char *kernel_filename,
                             const char *kernel_cmdline,
                             const char *initrd_filename,
                             const char *cpu_model)
{
    CPUState *env, *envs[MAX_CPUS];
    char buf[1024];
    qemu_irq *pic, **openpic_irqs;
    int unin_memory;
    int linux_boot, i;
    unsigned long bios_offset, vga_bios_offset;
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
    ppc_def_t *def;
    PCIBus *pci_bus;
    nvram_t nvram;
#if 0
    MacIONVRAMState *nvr;
    int nvram_mem_index;
#endif
    m48t59_t *m48t59;
    int vga_bios_size, bios_size;
    qemu_irq *dummy_irq;
    int pic_mem_index, dbdma_mem_index, cuda_mem_index;
    int ide_mem_index[2];

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    env = cpu_init();
    if (cpu_model == NULL)
        cpu_model = "default";
    ppc_find_by_name(cpu_model, &def);
    if (def == NULL) {
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
    }
    for (i = 0; i < smp_cpus; i++) {
        cpu_ppc_register(env, def);
        cpu_ppc_reset(env);
        /* Set time-base frequency to 100 Mhz */
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
#if 0
        env->osi_call = vga_osi_call;
#endif
        qemu_register_reset(&cpu_ppc_reset, env);
        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
        envs[i] = env;
    }
    if (env->nip < 0xFFF80000) {
        /* Special test for PowerPC 601:
         * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
         * But the NVRAM is located at 0xFFF04000...
         */
        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
    }

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* allocate and load BIOS */
    bios_offset = ram_size + vga_ram_size;
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    bios_size = load_image(buf, phys_ram_base + bios_offset);
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
        exit(1);
    }
    bios_size = (bios_size + 0xfff) & ~0xfff;
    if (bios_size > 0x00080000) {
        /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
        cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
    }
    cpu_register_physical_memory((uint32_t)(-bios_size),
                                 bios_size, bios_offset | IO_MEM_ROM);

    /* allocate and load VGA BIOS */
    vga_bios_offset = bios_offset + bios_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
    if (vga_bios_size < 0) {
        /* if no bios is present, we can still work */
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
        vga_bios_size = 0;
    } else {
        /* set a specific header (XXX: find real Apple format for NDRV
           drivers) */
        phys_ram_base[vga_bios_offset] = 'N';
        phys_ram_base[vga_bios_offset + 1] = 'D';
        phys_ram_base[vga_bios_offset + 2] = 'R';
        phys_ram_base[vga_bios_offset + 3] = 'V';
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
                     vga_bios_size);
        vga_bios_size += 8;
    }
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;

    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
        if (kernel_size < 0) {
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
                      kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image(initrd_filename,
                                     phys_ram_base + initrd_base);
            if (initrd_size < 0) {
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
                          initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
    }

    isa_mem_base = 0x80000000;

    /* Register 8 MB of ISA IO space */
    isa_mmio_init(0xf2000000, 0x00800000);

    /* UniN init */
    unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
    cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);

    openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
    openpic_irqs[0] =
        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
    for (i = 0; i < smp_cpus; i++) {
        /* Mac99 IRQ connection between OpenPIC outputs pins
         * and PowerPC input pins
         */
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
            openpic_irqs[i][OPENPIC_OUTPUT_INT] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
            /* Not connected ? */
            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
            /* Check this */
            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
            break;
#if defined(TARGET_PPC64)
        case PPC_FLAGS_INPUT_970:
            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
            openpic_irqs[i][OPENPIC_OUTPUT_INT] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
            /* Not connected ? */
            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
            /* Check this */
            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
            break;
#endif /* defined(TARGET_PPC64) */
        default:
            cpu_abort(env, "Bus model not supported on mac99 machine\n");
            exit(1);
        }
    }
    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
    pci_bus = pci_pmac_init(pic);
    /* init basic PC hardware */
    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
                 ram_size, vga_ram_size,
                 vga_bios_offset, vga_bios_size);
    
    /* XXX: suppress that */
    dummy_irq = i8259_init(NULL);

    /* XXX: use Mac Serial port */
    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }
#if 1
    ide_mem_index[0] = pmac_ide_init(&bs_table[0], pic[0x13]);
    ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x14]);
#else
    pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
#endif
    /* cuda also initialize ADB */
    cuda_init(&cuda_mem_index, pic[0x19]);
    
    adb_kbd_init(&adb_bus);
    adb_mouse_init(&adb_bus);

    dbdma_init(&dbdma_mem_index);

    macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,
               cuda_mem_index, -1, 2, ide_mem_index);

    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, 3, -1);
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;
#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */
    /* The NewWorld NVRAM is not located in the MacIO device */
    nvr = macio_nvram_init(&nvram_mem_index);
    pmac_format_nvram_partition(nvr, 0x2000);
    cpu_register_physical_memory(0xFFF04000, 0x20000, nvram_mem_index);
    nvram.opaque = nvr;
    nvram.read_fn = &macio_nvram_read;
    nvram.write_fn = &macio_nvram_write;
#else
    m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
    nvram.opaque = m48t59;
    nvram.read_fn = &m48t59_read;
    nvram.write_fn = &m48t59_write;
#endif
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size, boot_device,
                         kernel_base, kernel_size,
                         kernel_cmdline,
                         initrd_base, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);
    /* No PCI init: the BIOS will do it */

    /* Special port to get debug messages from Open-Firmware */
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 }

QEMUMachine core99_machine = {
    "mac99",
    "Mac99 based PowerMAC",
    ppc_core99_init,
};
Commit	Line	Data
64201201	1	/*
3cbee15b	2	* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
5fafdf24	3	*
47103572	4	* Copyright (c) 2004-2007 Fabrice Bellard
3cbee15b	5	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	6	*
64201201 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "vl.h"
3cbee15b	26	#include "ppc_mac.h"
267002cd	27
0aa6a4a2 FB	28	/* UniN device */
	29	static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	30	{
	31	}
	32
	33	static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
	34	{
	35	return 0;
	36	}
	37
	38	static CPUWriteMemoryFunc *unin_write[] = {
	39	&unin_writel,
	40	&unin_writel,
	41	&unin_writel,
	42	};
	43
	44	static CPUReadMemoryFunc *unin_read[] = {
	45	&unin_readl,
	46	&unin_readl,
	47	&unin_readl,
	48	};
	49
3cbee15b JM	50	/* PowerPC Mac99 hardware initialisation */
	51	static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
	52	DisplayState ds, const char *fd_filename,
	53	int snapshot,
	54	const char *kernel_filename,
	55	const char *kernel_cmdline,
	56	const char *initrd_filename,
	57	const char *cpu_model)
64201201	58	{
e9df014c	59	CPUState env, envs[MAX_CPUS];
64201201	60	char buf[1024];
e9df014c	61	qemu_irq pic, *openpic_irqs;
aef445bd	62	int unin_memory;
d5295253 FB	63	int linux_boot, i;
d5295253 FB	64	unsigned long bios_offset, vga_bios_offset;
b6b8bd18	65	uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
3fc6c082	66	ppc_def_t *def;
46e50e9d	67	PCIBus *pci_bus;
3cbee15b JM	68	nvram_t nvram;
	69	#if 0
	70	MacIONVRAMState *nvr;
	71	int nvram_mem_index;
	72	#endif
	73	m48t59_t *m48t59;
d5295253	74	int vga_bios_size, bios_size;
d537cf6c	75	qemu_irq *dummy_irq;
3cbee15b JM	76	int pic_mem_index, dbdma_mem_index, cuda_mem_index;
3cbee15b JM	77	int ide_mem_index[2];
46e50e9d	78
64201201 FB	79	linux_boot = (kernel_filename != NULL);
64201201 FB	80
c68ea704 FB	81	/* init CPUs */
c68ea704 FB	82	env = cpu_init();
94fc95cd	83	if (cpu_model == NULL)
d12f4c38	84	cpu_model = "default";
94fc95cd	85	ppc_find_by_name(cpu_model, &def);
c68ea704 FB	86	if (def == NULL) {
	87	cpu_abort(env, "Unable to find PowerPC CPU definition\n");
	88	}
e9df014c JM	89	for (i = 0; i < smp_cpus; i++) {
e9df014c JM	90	cpu_ppc_register(env, def);
fe33cc71	91	cpu_ppc_reset(env);
e9df014c JM	92	/* Set time-base frequency to 100 Mhz */
e9df014c JM	93	cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
3cbee15b	94	#if 0
e9df014c	95	env->osi_call = vga_osi_call;
3cbee15b	96	#endif
fe33cc71 JM	97	qemu_register_reset(&cpu_ppc_reset, env);
fe33cc71 JM	98	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
e9df014c JM	99	envs[i] = env;
e9df014c JM	100	}
4c823cff JM	101	if (env->nip < 0xFFF80000) {
	102	/* Special test for PowerPC 601:
	103	* the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
	104	* But the NVRAM is located at 0xFFF04000...
	105	*/
	106	cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
	107	}
c68ea704	108
64201201 FB	109	/* allocate RAM */
	110	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	111
	112	/* allocate and load BIOS */
	113	bios_offset = ram_size + vga_ram_size;
1192dad8 JM	114	if (bios_name == NULL)
	115	bios_name = BIOS_FILENAME;
	116	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
d5295253 FB	117	bios_size = load_image(buf, phys_ram_base + bios_offset);
d5295253 FB	118	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
4a057712	119	cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
64201201 FB	120	exit(1);
64201201 FB	121	}
d5295253	122	bios_size = (bios_size + 0xfff) & ~0xfff;
4c823cff JM	123	if (bios_size > 0x00080000) {
	124	/* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
	125	cpu_abort(env, "Mac99 hardware can not handle 1 MB BIOS\n");
	126	}
4a057712	127	cpu_register_physical_memory((uint32_t)(-bios_size),
d5295253	128	bios_size, bios_offset \| IO_MEM_ROM);
3b46e624	129
d5295253 FB	130	/* allocate and load VGA BIOS */
	131	vga_bios_offset = bios_offset + bios_size;
	132	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
	133	vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
	134	if (vga_bios_size < 0) {
	135	/* if no bios is present, we can still work */
	136	fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
	137	vga_bios_size = 0;
	138	} else {
	139	/* set a specific header (XXX: find real Apple format for NDRV
	140	drivers) */
	141	phys_ram_base[vga_bios_offset] = 'N';
	142	phys_ram_base[vga_bios_offset + 1] = 'D';
	143	phys_ram_base[vga_bios_offset + 2] = 'R';
	144	phys_ram_base[vga_bios_offset + 3] = 'V';
5fafdf24	145	cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
d5295253 FB	146	vga_bios_size);
	147	vga_bios_size += 8;
	148	}
	149	vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
3b46e624	150
b6b8bd18 FB	151	if (linux_boot) {
	152	kernel_base = KERNEL_LOAD_ADDR;
	153	/* now we can load the kernel */
	154	kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
	155	if (kernel_size < 0) {
4a057712 JM	156	cpu_abort(env, "qemu: could not load kernel '%s'\n",
4a057712 JM	157	kernel_filename);
b6b8bd18 FB	158	exit(1);
	159	}
	160	/* load initrd */
	161	if (initrd_filename) {
	162	initrd_base = INITRD_LOAD_ADDR;
	163	initrd_size = load_image(initrd_filename,
	164	phys_ram_base + initrd_base);
	165	if (initrd_size < 0) {
4a057712 JM	166	cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
4a057712 JM	167	initrd_filename);
b6b8bd18 FB	168	exit(1);
	169	}
	170	} else {
	171	initrd_base = 0;
	172	initrd_size = 0;
	173	}
	174	boot_device = 'm';
	175	} else {
	176	kernel_base = 0;
	177	kernel_size = 0;
	178	initrd_base = 0;
	179	initrd_size = 0;
	180	}
0aa6a4a2	181
3cbee15b	182	isa_mem_base = 0x80000000;
aef445bd	183
3cbee15b JM	184	/* Register 8 MB of ISA IO space */
3cbee15b JM	185	isa_mmio_init(0xf2000000, 0x00800000);
3b46e624	186
3cbee15b JM	187	/* UniN init */
	188	unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
	189	cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
47103572	190
3cbee15b JM	191	openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
	192	openpic_irqs[0] =
	193	qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
	194	for (i = 0; i < smp_cpus; i++) {
	195	/* Mac99 IRQ connection between OpenPIC outputs pins
	196	* and PowerPC input pins
	197	*/
	198	switch (PPC_INPUT(env)) {
	199	case PPC_FLAGS_INPUT_6xx:
	200	openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
	201	openpic_irqs[i][OPENPIC_OUTPUT_INT] =
	202	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	203	openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
	204	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	205	openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
	206	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
	207	/* Not connected ? */
	208	openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
	209	/* Check this */
	210	openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
	211	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
	212	break;
00af685f	213	#if defined(TARGET_PPC64)
3cbee15b JM	214	case PPC_FLAGS_INPUT_970:
	215	openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
	216	openpic_irqs[i][OPENPIC_OUTPUT_INT] =
	217	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
	218	openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
	219	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
	220	openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
	221	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
	222	/* Not connected ? */
	223	openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
	224	/* Check this */
	225	openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
	226	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
	227	break;
00af685f	228	#endif /* defined(TARGET_PPC64) */
3cbee15b JM	229	default:
	230	cpu_abort(env, "Bus model not supported on mac99 machine\n");
	231	exit(1);
0aa6a4a2	232	}
3cbee15b JM	233	}
	234	pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
	235	pci_bus = pci_pmac_init(pic);
	236	/* init basic PC hardware */
	237	pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
	238	ram_size, vga_ram_size,
	239	vga_bios_offset, vga_bios_size);
	240
	241	/* XXX: suppress that */
	242	dummy_irq = i8259_init(NULL);
	243
	244	/* XXX: use Mac Serial port */
	245	serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
	246	for(i = 0; i < nb_nics; i++) {
	247	if (!nd_table[i].model)
	248	nd_table[i].model = "ne2k_pci";
	249	pci_nic_init(pci_bus, &nd_table[i], -1);
	250	}
0aa6a4a2	251	#if 1
3cbee15b JM	252	ide_mem_index[0] = pmac_ide_init(&bs_table[0], pic[0x13]);
3cbee15b JM	253	ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x14]);
0aa6a4a2	254	#else
3cbee15b	255	pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
0aa6a4a2	256	#endif
3cbee15b JM	257	/* cuda also initialize ADB */
	258	cuda_init(&cuda_mem_index, pic[0x19]);
	259
	260	adb_kbd_init(&adb_bus);
	261	adb_mouse_init(&adb_bus);
3b46e624	262
3cbee15b	263	dbdma_init(&dbdma_mem_index);
3b46e624	264
3cbee15b JM	265	macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,
3cbee15b JM	266	cuda_mem_index, -1, 2, ide_mem_index);
0d92ed30 PB	267
0d92ed30 PB	268	if (usb_enabled) {
e24ad6f1	269	usb_ohci_init_pci(pci_bus, 3, -1);
0d92ed30 PB	270	}
0d92ed30 PB	271
b6b8bd18 FB	272	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
b6b8bd18 FB	273	graphic_depth = 15;
3cbee15b JM	274	#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */
	275	/* The NewWorld NVRAM is not located in the MacIO device */
	276	nvr = macio_nvram_init(&nvram_mem_index);
	277	pmac_format_nvram_partition(nvr, 0x2000);
	278	cpu_register_physical_memory(0xFFF04000, 0x20000, nvram_mem_index);
	279	nvram.opaque = nvr;
	280	nvram.read_fn = &macio_nvram_read;
	281	nvram.write_fn = &macio_nvram_write;
	282	#else
	283	m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
	284	nvram.opaque = m48t59;
	285	nvram.read_fn = &m48t59_read;
	286	nvram.write_fn = &m48t59_write;
	287	#endif
	288	PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "MAC99", ram_size, boot_device,
b6b8bd18 FB	289	kernel_base, kernel_size,
	290	kernel_cmdline,
	291	initrd_base, initrd_size,
64201201	292	/* XXX: need an option to load a NVRAM image */
b6b8bd18 FB	293	0,
	294	graphic_width, graphic_height, graphic_depth);
	295	/* No PCI init: the BIOS will do it */
0aa6a4a2 FB	296
	297	/* Special port to get debug messages from Open-Firmware */
	298	register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
3cbee15b	299	}
0aa6a4a2 FB	300
0aa6a4a2 FB	301	QEMUMachine core99_machine = {
0289b2c1 FB	302	"mac99",
0289b2c1 FB	303	"Mac99 based PowerMAC",
0aa6a4a2 FB	304	ppc_core99_init,
0aa6a4a2 FB	305	};