[qemu.git] / hw / ppc_newworld.c

/*
 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 * PCI bus layout on a real G5 (U3 based):
 *
 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
 *
 */
#include "hw.h"
#include "ppc.h"
#include "ppc_mac.h"
#include "mac_dbdma.h"
#include "nvram.h"
#include "pc.h"
#include "pci.h"
#include "usb-ohci.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
#include "fw_cfg.h"
#include "escc.h"
#include "openpic.h"
#include "ide.h"
#include "loader.h"
#include "elf.h"
#include "kvm.h"
#include "kvm_ppc.h"
#include "hw/usb.h"
#include "blockdev.h"

#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

/* UniN device */
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
}

static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
{
    uint32_t value;

    value = 0;
    UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);

    return value;
}

static CPUWriteMemoryFunc * const unin_write[] = {
    &unin_writel,
    &unin_writel,
    &unin_writel,
};

static CPUReadMemoryFunc * const unin_read[] = {
    &unin_readl,
    &unin_readl,
    &unin_readl,
};

static int fw_cfg_boot_set(void *opaque, const char *boot_device)
{
    fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
    return 0;
}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static target_phys_addr_t round_page(target_phys_addr_t addr)
{
    return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}

/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size,
                             const char *boot_device,
                             const char *kernel_filename,
                             const char *kernel_cmdline,
                             const char *initrd_filename,
                             const char *cpu_model)
{
    CPUState *env = NULL;
    char *filename;
    qemu_irq *pic, **openpic_irqs;
    int unin_memory;
    int linux_boot, i;
    ram_addr_t ram_offset, bios_offset;
    target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
    long kernel_size, initrd_size;
    PCIBus *pci_bus;
    MacIONVRAMState *nvr;
    int nvram_mem_index;
    int bios_size;
    int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index;
    int ide_mem_index[3];
    int ppc_boot_device;
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    void *fw_cfg;
    void *dbdma;
    int machine_arch;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
#ifdef TARGET_PPC64
        cpu_model = "970fx";
#else
        cpu_model = "G4";
#endif
    for (i = 0; i < smp_cpus; i++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        /* Set time-base frequency to 100 Mhz */
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
        qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
    }

    /* allocate RAM */
    ram_offset = qemu_ram_alloc(NULL, "ppc_core99.ram", ram_size);
    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate and load BIOS */
    bios_offset = qemu_ram_alloc(NULL, "ppc_core99.bios", BIOS_SIZE);
    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);

    /* Load OpenBIOS (ELF) */
    if (filename) {
        bios_size = load_elf(filename, NULL, NULL, NULL,
                             NULL, NULL, 1, ELF_MACHINE, 0);

        qemu_free(filename);
    } else {
        bios_size = -1;
    }
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
        exit(1);
    }

    if (linux_boot) {
        uint64_t lowaddr = 0;
        int bswap_needed;

#ifdef BSWAP_NEEDED
        bswap_needed = 1;
#else
        bswap_needed = 0;
#endif
        kernel_base = KERNEL_LOAD_ADDR;

        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, kernel_base,
                                    ram_size - kernel_base, bswap_needed,
                                    TARGET_PAGE_SIZE);
        if (kernel_size < 0)
            kernel_size = load_image_targphys(kernel_filename,
                                              kernel_base,
                                              ram_size - kernel_base);
        if (kernel_size < 0) {
            hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                hw_error("qemu: could not load initial ram disk '%s'\n",
                         initrd_filename);
                exit(1);
            }
            cmdline_base = round_page(initrd_base + initrd_size);
        } else {
            initrd_base = 0;
            initrd_size = 0;
            cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
        }
        ppc_boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
        ppc_boot_device = '\0';
        /* We consider that NewWorld PowerMac never have any floppy drive
         * For now, OHW cannot boot from the network.
         */
        for (i = 0; boot_device[i] != '\0'; i++) {
            if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
                ppc_boot_device = boot_device[i];
                break;
            }
        }
        if (ppc_boot_device == '\0') {
            fprintf(stderr, "No valid boot device for Mac99 machine\n");
            exit(1);
        }
    }

    isa_mem_base = 0x80000000;

    /* Register 8 MB of ISA IO space */
    isa_mmio_init(0xf2000000, 0x00800000);

    /* UniN init */
    unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL,
                                         DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);

    openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
    openpic_irqs[0] =
        qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
    for (i = 0; i < smp_cpus; i++) {
        /* Mac99 IRQ connection between OpenPIC outputs pins
         * and PowerPC input pins
         */
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
            openpic_irqs[i][OPENPIC_OUTPUT_INT] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
            /* Not connected ? */
            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
            /* Check this */
            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
            break;
#if defined(TARGET_PPC64)
        case PPC_FLAGS_INPUT_970:
            openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
            openpic_irqs[i][OPENPIC_OUTPUT_INT] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
            openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
            /* Not connected ? */
            openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
            /* Check this */
            openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
                ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
            break;
#endif /* defined(TARGET_PPC64) */
        default:
            hw_error("Bus model not supported on mac99 machine\n");
            exit(1);
        }
    }
    pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
    if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
        /* 970 gets a U3 bus */
        pci_bus = pci_pmac_u3_init(pic);
        machine_arch = ARCH_MAC99_U3;
    } else {
        pci_bus = pci_pmac_init(pic);
        machine_arch = ARCH_MAC99;
    }
    /* init basic PC hardware */
    pci_vga_init(pci_bus);

    escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24],
                               serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);

    for(i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);

    ide_drive_get(hd, MAX_IDE_BUS);
    dbdma = DBDMA_init(&dbdma_mem_index);

    /* We only emulate 2 out of 3 IDE controllers for now */
    ide_mem_index[0] = -1;
    ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
    ide_mem_index[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);

    /* cuda also initialize ADB */
    if (machine_arch == ARCH_MAC99_U3) {
        usb_enabled = 1;
    }
    cuda_init(&cuda_mem_index, pic[0x19]);

    adb_kbd_init(&adb_bus);
    adb_mouse_init(&adb_bus);

    macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index,
               dbdma_mem_index, cuda_mem_index, NULL, 3, ide_mem_index,
               escc_mem_index);

    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, -1);
    }

    /* U3 needs to use USB for input because Linux doesn't support via-cuda
       on PPC64 */
    if (machine_arch == ARCH_MAC99_U3) {
        usbdevice_create("keyboard");
        usbdevice_create("mouse");
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    /* The NewWorld NVRAM is not located in the MacIO device */
    nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1);
    pmac_format_nvram_partition(nvr, 0x2000);
    macio_nvram_map(nvr, 0xFFF04000);
    /* No PCI init: the BIOS will do it */

    fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
    if (kernel_cmdline) {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
    } else {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
    }
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);

    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);

    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        uint8_t *hypercall;

        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
        hypercall = qemu_malloc(16);
        kvmppc_get_hypercall(env, hypercall, 16);
        fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
    } else {
        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
    }

    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}

static QEMUMachine core99_machine = {
    .name = "mac99",
    .desc = "Mac99 based PowerMAC",
    .init = ppc_core99_init,
    .max_cpus = MAX_CPUS,
#ifdef TARGET_PPC64
    .is_default = 1,
#endif
};

static void core99_machine_init(void)
{
    qemu_register_machine(&core99_machine);
}

machine_init(core99_machine_init);
Commit	Line	Data
64201201	1	/*
3cbee15b	2	* QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
5fafdf24	3	*
47103572	4	* Copyright (c) 2004-2007 Fabrice Bellard
3cbee15b	5	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	6	*
64201201 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
915cd3a9 AG	24	*
	25	* PCI bus layout on a real G5 (U3 based):
	26	*
	27	* 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
	28	* 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
	29	* 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
	30	* 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
	31	* 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
	32	* 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
	33	* 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
	34	* 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
	35	* 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
	36	* 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
	37	* 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
	38	* 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
	39	* 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
	40	* 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
	41	* 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
	42	* 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
	43	* 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
	44	* 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
	45	* 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
	46	* 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
	47	*
64201201	48	*/
87ecb68b PB	49	#include "hw.h"
87ecb68b PB	50	#include "ppc.h"
3cbee15b	51	#include "ppc_mac.h"
28ce5ce6	52	#include "mac_dbdma.h"
87ecb68b PB	53	#include "nvram.h"
	54	#include "pc.h"
	55	#include "pci.h"
18e08a55	56	#include "usb-ohci.h"
87ecb68b PB	57	#include "net.h"
	58	#include "sysemu.h"
	59	#include "boards.h"
006f3a48	60	#include "fw_cfg.h"
7fa9ae1a	61	#include "escc.h"
b7169916	62	#include "openpic.h"
977e1244	63	#include "ide.h"
ca20cf32 BS	64	#include "loader.h"
ca20cf32 BS	65	#include "elf.h"
dc702288	66	#include "kvm.h"
dc333cd6	67	#include "kvm_ppc.h"
a2236d48	68	#include "hw/usb.h"
2446333c	69	#include "blockdev.h"
267002cd	70
e4bcb14c	71	#define MAX_IDE_BUS 2
006f3a48	72	#define CFG_ADDR 0xf0000510
e4bcb14c	73
f3902383 BS	74	/* debug UniNorth */
	75	//#define DEBUG_UNIN
	76
	77	#ifdef DEBUG_UNIN
001faf32 BS	78	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	79	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	80	#else
001faf32	81	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	82	#endif
f3902383 BS	83
0aa6a4a2	84	/* UniN device */
c227f099	85	static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
0aa6a4a2	86	{
f3902383	87	UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
0aa6a4a2 FB	88	}
0aa6a4a2 FB	89
c227f099	90	static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
0aa6a4a2	91	{
f3902383 BS	92	uint32_t value;
	93
	94	value = 0;
	95	UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
	96
	97	return value;
0aa6a4a2 FB	98	}
0aa6a4a2 FB	99
d60efc6b	100	static CPUWriteMemoryFunc * const unin_write[] = {
0aa6a4a2 FB	101	&unin_writel,
	102	&unin_writel,
	103	&unin_writel,
	104	};
	105
d60efc6b	106	static CPUReadMemoryFunc * const unin_read[] = {
0aa6a4a2 FB	107	&unin_readl,
	108	&unin_readl,
	109	&unin_readl,
	110	};
	111
513f789f BS	112	static int fw_cfg_boot_set(void opaque, const char boot_device)
	113	{
	114	fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
	115	return 0;
	116	}
	117
409dbce5 AJ	118	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	119	{
	120	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	121	}
	122
b9e17a34 AG	123	static target_phys_addr_t round_page(target_phys_addr_t addr)
	124	{
	125	return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
	126	}
	127
3cbee15b	128	/* PowerPC Mac99 hardware initialisation */
c227f099	129	static void ppc_core99_init (ram_addr_t ram_size,
3023f332	130	const char *boot_device,
3cbee15b JM	131	const char *kernel_filename,
	132	const char *kernel_cmdline,
	133	const char *initrd_filename,
	134	const char *cpu_model)
64201201	135	{
49a2942d	136	CPUState *env = NULL;
5cea8590	137	char *filename;
e9df014c	138	qemu_irq pic, *openpic_irqs;
aef445bd	139	int unin_memory;
d5295253	140	int linux_boot, i;
ae0bfb79	141	ram_addr_t ram_offset, bios_offset;
b9e17a34	142	target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
093209cd	143	long kernel_size, initrd_size;
46e50e9d	144	PCIBus *pci_bus;
3cbee15b JM	145	MacIONVRAMState *nvr;
3cbee15b JM	146	int nvram_mem_index;
ae0bfb79	147	int bios_size;
7fa9ae1a	148	int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index;
dffc07ca	149	int ide_mem_index[3];
28c5af54	150	int ppc_boot_device;
f455e98c	151	DriveInfo hd[MAX_IDE_BUS MAX_IDE_DEVS];
006f3a48	152	void *fw_cfg;
28ce5ce6	153	void *dbdma;
0f921197	154	int machine_arch;
46e50e9d	155
64201201 FB	156	linux_boot = (kernel_filename != NULL);
64201201 FB	157
c68ea704	158	/* init CPUs */
94fc95cd	159	if (cpu_model == NULL)
46214a27 AF	160	#ifdef TARGET_PPC64
	161	cpu_model = "970fx";
	162	#else
e6bd862b	163	cpu_model = "G4";
46214a27	164	#endif
e9df014c	165	for (i = 0; i < smp_cpus; i++) {
aaed909a FB	166	env = cpu_init(cpu_model);
	167	if (!env) {
	168	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	169	exit(1);
	170	}
e9df014c JM	171	/* Set time-base frequency to 100 Mhz */
e9df014c JM	172	cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
d84bda46	173	qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
e9df014c	174	}
c68ea704	175
64201201	176	/* allocate RAM */
1724f049	177	ram_offset = qemu_ram_alloc(NULL, "ppc_core99.ram", ram_size);
864c136a BS	178	cpu_register_physical_memory(0, ram_size, ram_offset);
864c136a BS	179
64201201	180	/* allocate and load BIOS */
1724f049	181	bios_offset = qemu_ram_alloc(NULL, "ppc_core99.bios", BIOS_SIZE);
1192dad8	182	if (bios_name == NULL)
006f3a48	183	bios_name = PROM_FILENAME;
5cea8590	184	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
006f3a48 BS	185	cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset \| IO_MEM_ROM);
	186
	187	/* Load OpenBIOS (ELF) */
5cea8590	188	if (filename) {
409dbce5 AJ	189	bios_size = load_elf(filename, NULL, NULL, NULL,
409dbce5 AJ	190	NULL, NULL, 1, ELF_MACHINE, 0);
ca20cf32	191
5cea8590 PB	192	qemu_free(filename);
	193	} else {
	194	bios_size = -1;
	195	}
d5295253	196	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
5cea8590	197	hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
64201201 FB	198	exit(1);
64201201 FB	199	}
3b46e624	200
b6b8bd18	201	if (linux_boot) {
513f789f	202	uint64_t lowaddr = 0;
ca20cf32 BS	203	int bswap_needed;
	204
	205	#ifdef BSWAP_NEEDED
	206	bswap_needed = 1;
	207	#else
	208	bswap_needed = 0;
	209	#endif
b6b8bd18	210	kernel_base = KERNEL_LOAD_ADDR;
513f789f	211
409dbce5 AJ	212	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
409dbce5 AJ	213	NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
513f789f BS	214	if (kernel_size < 0)
513f789f BS	215	kernel_size = load_aout(kernel_filename, kernel_base,
ca20cf32 BS	216	ram_size - kernel_base, bswap_needed,
ca20cf32 BS	217	TARGET_PAGE_SIZE);
513f789f BS	218	if (kernel_size < 0)
	219	kernel_size = load_image_targphys(kernel_filename,
	220	kernel_base,
	221	ram_size - kernel_base);
b6b8bd18	222	if (kernel_size < 0) {
2ac71179	223	hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
b6b8bd18 FB	224	exit(1);
	225	}
	226	/* load initrd */
	227	if (initrd_filename) {
b9e17a34	228	initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
44654490 PB	229	initrd_size = load_image_targphys(initrd_filename, initrd_base,
44654490 PB	230	ram_size - initrd_base);
b6b8bd18	231	if (initrd_size < 0) {
2ac71179 PB	232	hw_error("qemu: could not load initial ram disk '%s'\n",
2ac71179 PB	233	initrd_filename);
b6b8bd18 FB	234	exit(1);
b6b8bd18 FB	235	}
b9e17a34	236	cmdline_base = round_page(initrd_base + initrd_size);
b6b8bd18 FB	237	} else {
	238	initrd_base = 0;
	239	initrd_size = 0;
b9e17a34	240	cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
b6b8bd18	241	}
6ac0e82d	242	ppc_boot_device = 'm';
b6b8bd18 FB	243	} else {
	244	kernel_base = 0;
	245	kernel_size = 0;
	246	initrd_base = 0;
	247	initrd_size = 0;
28c5af54 JM	248	ppc_boot_device = '\0';
	249	/* We consider that NewWorld PowerMac never have any floppy drive
	250	* For now, OHW cannot boot from the network.
	251	*/
0d913fdb JM	252	for (i = 0; boot_device[i] != '\0'; i++) {
	253	if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
	254	ppc_boot_device = boot_device[i];
28c5af54	255	break;
0d913fdb	256	}
28c5af54 JM	257	}
	258	if (ppc_boot_device == '\0') {
	259	fprintf(stderr, "No valid boot device for Mac99 machine\n");
	260	exit(1);
	261	}
b6b8bd18	262	}
0aa6a4a2	263
3cbee15b	264	isa_mem_base = 0x80000000;
aef445bd	265
3cbee15b	266	/* Register 8 MB of ISA IO space */
968d683c	267	isa_mmio_init(0xf2000000, 0x00800000);
3b46e624	268
3cbee15b	269	/* UniN init */
2507c12a AG	270	unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL,
2507c12a AG	271	DEVICE_NATIVE_ENDIAN);
3cbee15b	272	cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
47103572	273
3cbee15b JM	274	openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
	275	openpic_irqs[0] =
	276	qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
	277	for (i = 0; i < smp_cpus; i++) {
	278	/* Mac99 IRQ connection between OpenPIC outputs pins
	279	* and PowerPC input pins
	280	*/
	281	switch (PPC_INPUT(env)) {
	282	case PPC_FLAGS_INPUT_6xx:
	283	openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
	284	openpic_irqs[i][OPENPIC_OUTPUT_INT] =
	285	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	286	openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
	287	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	288	openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
	289	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
	290	/* Not connected ? */
	291	openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
	292	/* Check this */
	293	openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
	294	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
	295	break;
00af685f	296	#if defined(TARGET_PPC64)
3cbee15b JM	297	case PPC_FLAGS_INPUT_970:
	298	openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
	299	openpic_irqs[i][OPENPIC_OUTPUT_INT] =
	300	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
	301	openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
	302	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
	303	openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
	304	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
	305	/* Not connected ? */
	306	openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
	307	/* Check this */
	308	openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
	309	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
	310	break;
00af685f	311	#endif /* defined(TARGET_PPC64) */
3cbee15b	312	default:
2ac71179	313	hw_error("Bus model not supported on mac99 machine\n");
3cbee15b	314	exit(1);
0aa6a4a2	315	}
3cbee15b JM	316	}
3cbee15b JM	317	pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
0f921197 AG	318	if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
	319	/* 970 gets a U3 bus */
	320	pci_bus = pci_pmac_u3_init(pic);
	321	machine_arch = ARCH_MAC99_U3;
	322	} else {
	323	pci_bus = pci_pmac_init(pic);
	324	machine_arch = ARCH_MAC99;
	325	}
3cbee15b	326	/* init basic PC hardware */
78895427	327	pci_vga_init(pci_bus);
aae9366a	328
b4b784fe	329	escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24],
aeeb69c7	330	serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
cb457d76 AL	331
cb457d76 AL	332	for(i = 0; i < nb_nics; i++)
07caea31	333	pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
cb457d76	334
75717903	335	ide_drive_get(hd, MAX_IDE_BUS);
28ce5ce6	336	dbdma = DBDMA_init(&dbdma_mem_index);
dffc07ca AG	337
	338	/* We only emulate 2 out of 3 IDE controllers for now */
	339	ide_mem_index[0] = -1;
dffc07ca	340	ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
75717903	341	ide_mem_index[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
77f0435e	342
3cbee15b	343	/* cuda also initialize ADB */
a2236d48 AG	344	if (machine_arch == ARCH_MAC99_U3) {
	345	usb_enabled = 1;
	346	}
3cbee15b	347	cuda_init(&cuda_mem_index, pic[0x19]);
aae9366a	348
3cbee15b JM	349	adb_kbd_init(&adb_bus);
3cbee15b JM	350	adb_mouse_init(&adb_bus);
3b46e624	351
4ebcf884	352	macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index,
dffc07ca	353	dbdma_mem_index, cuda_mem_index, NULL, 3, ide_mem_index,
4ebcf884	354	escc_mem_index);
0d92ed30 PB	355
0d92ed30 PB	356	if (usb_enabled) {
a67ba3b6	357	usb_ohci_init_pci(pci_bus, -1);
0d92ed30 PB	358	}
0d92ed30 PB	359
a2236d48 AG	360	/* U3 needs to use USB for input because Linux doesn't support via-cuda
	361	on PPC64 */
	362	if (machine_arch == ARCH_MAC99_U3) {
	363	usbdevice_create("keyboard");
	364	usbdevice_create("mouse");
	365	}
	366
b6b8bd18 FB	367	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
b6b8bd18 FB	368	graphic_depth = 15;
4f3f238b	369
3cbee15b	370	/* The NewWorld NVRAM is not located in the MacIO device */
68af3f24	371	nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1);
3cbee15b	372	pmac_format_nvram_partition(nvr, 0x2000);
74e91155	373	macio_nvram_map(nvr, 0xFFF04000);
b6b8bd18	374	/* No PCI init: the BIOS will do it */
0aa6a4a2	375
006f3a48 BS	376	fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
	377	fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
	378	fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
0f921197	379	fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
513f789f BS	380	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
	381	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
	382	if (kernel_cmdline) {
b9e17a34 AG	383	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
b9e17a34 AG	384	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
513f789f BS	385	} else {
	386	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
	387	}
	388	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
	389	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
	390	fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
10696b4f BS	391
	392	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
	393	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
	394	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
	395
45024f09	396	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
dc333cd6 AG	397	if (kvm_enabled()) {
dc333cd6 AG	398	#ifdef CONFIG_KVM
45024f09 AG	399	uint8_t *hypercall;
45024f09 AG	400
dc333cd6	401	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
45024f09 AG	402	hypercall = qemu_malloc(16);
	403	kvmppc_get_hypercall(env, hypercall, 16);
	404	fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
	405	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
dc333cd6 AG	406	#endif
	407	} else {
	408	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
	409	}
	410
513f789f	411	qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
aae9366a	412	}
0aa6a4a2	413
f80f9ec9	414	static QEMUMachine core99_machine = {
4b32e168 AL	415	.name = "mac99",
	416	.desc = "Mac99 based PowerMAC",
	417	.init = ppc_core99_init,
3d878caa	418	.max_cpus = MAX_CPUS,
46214a27 AF	419	#ifdef TARGET_PPC64
	420	.is_default = 1,
	421	#endif
0aa6a4a2	422	};
f80f9ec9 AL	423
	424	static void core99_machine_init(void)
	425	{
	426	qemu_register_machine(&core99_machine);
	427	}
	428
	429	machine_init(core99_machine_init);