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Fix pci_add nic not to exit on bad model
[qemu.git] / hw / ppc_oldworld.c
CommitLineData
3cbee15b 1/*
4d7ca41e 2 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
3cbee15b
JM
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
87ecb68b
PB
25#include "hw.h"
26#include "ppc.h"
3cbee15b 27#include "ppc_mac.h"
28ce5ce6 28#include "mac_dbdma.h"
87ecb68b
PB
29#include "nvram.h"
30#include "pc.h"
31#include "sysemu.h"
32#include "net.h"
33#include "isa.h"
34#include "pci.h"
35#include "boards.h"
271dd5e0 36#include "fw_cfg.h"
7fa9ae1a 37#include "escc.h"
977e1244 38#include "ide.h"
ca20cf32
BS
39#include "loader.h"
40#include "elf.h"
3cbee15b 41
e4bcb14c 42#define MAX_IDE_BUS 2
a748ab6d 43#define VGA_BIOS_SIZE 65536
271dd5e0
BS
44#define CFG_ADDR 0xf0000510
45
3cbee15b
JM
46/* temporary frame buffer OSI calls for the video.x driver. The right
47 solution is to modify the driver to use VGA PCI I/Os */
48/* XXX: to be removed. This is no way related to emulation */
49static int vga_osi_call (CPUState *env)
50{
51 static int vga_vbl_enabled;
52 int linesize;
53
b11ebf64
BS
54#if 0
55 printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
56#endif
3cbee15b
JM
57
58 /* same handler as PearPC, coming from the original MOL video
59 driver. */
60 switch(env->gpr[5]) {
61 case 4:
62 break;
63 case 28: /* set_vmode */
64 if (env->gpr[6] != 1 || env->gpr[7] != 0)
65 env->gpr[3] = 1;
66 else
67 env->gpr[3] = 0;
68 break;
69 case 29: /* get_vmode_info */
70 if (env->gpr[6] != 0) {
71 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
72 env->gpr[3] = 1;
73 break;
74 }
75 }
76 env->gpr[3] = 0;
77 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
78 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
79 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
80 env->gpr[7] = 85 << 16; /* refresh rate */
81 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
82 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
83 linesize = (linesize + 3) & ~3;
84 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
85 break;
86 case 31: /* set_video power */
87 env->gpr[3] = 0;
88 break;
89 case 39: /* video_ctrl */
90 if (env->gpr[6] == 0 || env->gpr[6] == 1)
91 vga_vbl_enabled = env->gpr[6];
92 env->gpr[3] = 0;
93 break;
94 case 47:
95 break;
96 case 59: /* set_color */
97 /* R6 = index, R7 = RGB */
98 env->gpr[3] = 0;
99 break;
100 case 64: /* get color */
101 /* R6 = index */
102 env->gpr[3] = 0;
103 break;
104 case 116: /* set hwcursor */
105 /* R6 = x, R7 = y, R8 = visible, R9 = data */
106 break;
107 default:
b11ebf64 108 fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
aae9366a 109 ppc_dump_gpr(env, 5));
3cbee15b
JM
110 break;
111 }
112
113 return 1; /* osi_call handled */
114}
115
513f789f
BS
116static int fw_cfg_boot_set(void *opaque, const char *boot_device)
117{
118 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
119 return 0;
120}
121
c227f099 122static void ppc_heathrow_init (ram_addr_t ram_size,
3023f332 123 const char *boot_device,
3cbee15b
JM
124 const char *kernel_filename,
125 const char *kernel_cmdline,
126 const char *initrd_filename,
127 const char *cpu_model)
128{
aaed909a 129 CPUState *env = NULL, *envs[MAX_CPUS];
5cea8590 130 char *filename;
3cbee15b 131 qemu_irq *pic, **heathrow_irqs;
3cbee15b 132 int linux_boot, i;
c227f099 133 ram_addr_t ram_offset, bios_offset, vga_bios_offset;
7373048c
BS
134 uint32_t kernel_base, initrd_base;
135 int32_t kernel_size, initrd_size;
3cbee15b
JM
136 PCIBus *pci_bus;
137 MacIONVRAMState *nvr;
138 int vga_bios_size, bios_size;
3cbee15b 139 int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
7fa9ae1a 140 int escc_mem_index, ide_mem_index[2];
513f789f 141 uint16_t ppc_boot_device;
f455e98c 142 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
271dd5e0 143 void *fw_cfg;
28ce5ce6 144 void *dbdma;
44654490 145 uint8_t *vga_bios_ptr;
3cbee15b
JM
146
147 linux_boot = (kernel_filename != NULL);
148
149 /* init CPUs */
3cbee15b 150 if (cpu_model == NULL)
f2fde45a 151 cpu_model = "G3";
3cbee15b 152 for (i = 0; i < smp_cpus; i++) {
aaed909a
FB
153 env = cpu_init(cpu_model);
154 if (!env) {
155 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
156 exit(1);
157 }
b0fb43d8
AJ
158 /* Set time-base frequency to 16.6 Mhz */
159 cpu_ppc_tb_init(env, 16600000UL);
3cbee15b 160 env->osi_call = vga_osi_call;
a08d4367 161 qemu_register_reset(&cpu_ppc_reset, env);
3cbee15b
JM
162 envs[i] = env;
163 }
164
165 /* allocate RAM */
6b4079f8
AJ
166 if (ram_size > (2047 << 20)) {
167 fprintf(stderr,
168 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
169 ((unsigned int)ram_size / (1 << 20)));
170 exit(1);
171 }
172
a748ab6d
AJ
173 ram_offset = qemu_ram_alloc(ram_size);
174 cpu_register_physical_memory(0, ram_size, ram_offset);
175
3cbee15b 176 /* allocate and load BIOS */
a748ab6d 177 bios_offset = qemu_ram_alloc(BIOS_SIZE);
3cbee15b 178 if (bios_name == NULL)
992e5acd 179 bios_name = PROM_FILENAME;
5cea8590 180 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
992e5acd
BS
181 cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
182
183 /* Load OpenBIOS (ELF) */
5cea8590 184 if (filename) {
ca20cf32
BS
185 bios_size = load_elf(filename, 0, NULL, NULL, NULL,
186 1, ELF_MACHINE, 0);
5cea8590
PB
187 qemu_free(filename);
188 } else {
189 bios_size = -1;
190 }
3cbee15b 191 if (bios_size < 0 || bios_size > BIOS_SIZE) {
5cea8590 192 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
3cbee15b
JM
193 exit(1);
194 }
3cbee15b
JM
195
196 /* allocate and load VGA BIOS */
a748ab6d 197 vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
44654490 198 vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
5cea8590
PB
199 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
200 if (filename) {
201 vga_bios_size = load_image(filename, vga_bios_ptr + 8);
202 qemu_free(filename);
203 } else {
204 vga_bios_size = -1;
205 }
3cbee15b
JM
206 if (vga_bios_size < 0) {
207 /* if no bios is present, we can still work */
5cea8590
PB
208 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
209 VGABIOS_FILENAME);
3cbee15b
JM
210 vga_bios_size = 0;
211 } else {
212 /* set a specific header (XXX: find real Apple format for NDRV
213 drivers) */
44654490
PB
214 vga_bios_ptr[0] = 'N';
215 vga_bios_ptr[1] = 'D';
216 vga_bios_ptr[2] = 'R';
217 vga_bios_ptr[3] = 'V';
218 cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
3cbee15b 219 vga_bios_size += 8;
a7b022e0
AG
220
221 /* Round to page boundary */
222 vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
223 TARGET_PAGE_MASK;
3cbee15b 224 }
3cbee15b
JM
225
226 if (linux_boot) {
36bee1e3 227 uint64_t lowaddr = 0;
ca20cf32
BS
228 int bswap_needed;
229
230#ifdef BSWAP_NEEDED
231 bswap_needed = 1;
232#else
233 bswap_needed = 0;
234#endif
3cbee15b 235 kernel_base = KERNEL_LOAD_ADDR;
36bee1e3
AJ
236 /* Now we can load the kernel. The first step tries to load the kernel
237 supposing PhysAddr = 0x00000000. If that was wrong the kernel is
238 loaded again, the new PhysAddr being computed from lowaddr. */
ca20cf32
BS
239 kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL,
240 1, ELF_MACHINE, 0);
36bee1e3
AJ
241 if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
242 kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
ca20cf32 243 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
36bee1e3 244 }
52f163b7
BS
245 if (kernel_size < 0)
246 kernel_size = load_aout(kernel_filename, kernel_base,
ca20cf32
BS
247 ram_size - kernel_base, bswap_needed,
248 TARGET_PAGE_SIZE);
52f163b7
BS
249 if (kernel_size < 0)
250 kernel_size = load_image_targphys(kernel_filename,
251 kernel_base,
252 ram_size - kernel_base);
3cbee15b 253 if (kernel_size < 0) {
2ac71179 254 hw_error("qemu: could not load kernel '%s'\n",
3cbee15b
JM
255 kernel_filename);
256 exit(1);
257 }
258 /* load initrd */
259 if (initrd_filename) {
260 initrd_base = INITRD_LOAD_ADDR;
dcac9679
PB
261 initrd_size = load_image_targphys(initrd_filename, initrd_base,
262 ram_size - initrd_base);
3cbee15b 263 if (initrd_size < 0) {
2ac71179
PB
264 hw_error("qemu: could not load initial ram disk '%s'\n",
265 initrd_filename);
3cbee15b
JM
266 exit(1);
267 }
268 } else {
269 initrd_base = 0;
270 initrd_size = 0;
271 }
6ac0e82d 272 ppc_boot_device = 'm';
3cbee15b
JM
273 } else {
274 kernel_base = 0;
275 kernel_size = 0;
276 initrd_base = 0;
277 initrd_size = 0;
28c5af54 278 ppc_boot_device = '\0';
0d913fdb 279 for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54 280 /* TOFIX: for now, the second IDE channel is not properly
0d913fdb 281 * used by OHW. The Mac floppy disk are not emulated.
28c5af54
JM
282 * For now, OHW cannot boot from the network.
283 */
284#if 0
0d913fdb
JM
285 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
286 ppc_boot_device = boot_device[i];
28c5af54 287 break;
0d913fdb 288 }
28c5af54 289#else
0d913fdb
JM
290 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
291 ppc_boot_device = boot_device[i];
28c5af54 292 break;
0d913fdb 293 }
28c5af54
JM
294#endif
295 }
296 if (ppc_boot_device == '\0') {
8a901def 297 fprintf(stderr, "No valid boot device for G3 Beige machine\n");
28c5af54
JM
298 exit(1);
299 }
3cbee15b
JM
300 }
301
302 isa_mem_base = 0x80000000;
aae9366a 303
3cbee15b
JM
304 /* Register 2 MB of ISA IO space */
305 isa_mmio_init(0xfe000000, 0x00200000);
306
307 /* XXX: we register only 1 output pin for heathrow PIC */
308 heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
309 heathrow_irqs[0] =
310 qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
311 /* Connect the heathrow PIC outputs to the 6xx bus */
312 for (i = 0; i < smp_cpus; i++) {
313 switch (PPC_INPUT(env)) {
314 case PPC_FLAGS_INPUT_6xx:
315 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
316 heathrow_irqs[i][0] =
317 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
318 break;
319 default:
2ac71179 320 hw_error("Bus model not supported on OldWorld Mac machine\n");
3cbee15b
JM
321 }
322 }
323
324 /* init basic PC hardware */
325 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
2ac71179 326 hw_error("Only 6xx bus is supported on heathrow machine\n");
3cbee15b
JM
327 }
328 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
329 pci_bus = pci_grackle_init(0xfec00000, pic);
fbe1b595 330 pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
aae9366a 331
aeeb69c7 332 escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
7fa9ae1a 333 serial_hds[1], ESCC_CLOCK, 4);
aae9366a 334
cb457d76 335 for(i = 0; i < nb_nics; i++)
07caea31 336 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
0d913fdb 337
e4bcb14c
TS
338
339 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
340 fprintf(stderr, "qemu: too many IDE bus\n");
341 exit(1);
342 }
bd4524ed
AJ
343
344 /* First IDE channel is a MAC IDE on the MacIO bus */
f455e98c
GH
345 hd[0] = drive_get(IF_IDE, 0, 0);
346 hd[1] = drive_get(IF_IDE, 0, 1);
bd4524ed
AJ
347 dbdma = DBDMA_init(&dbdma_mem_index);
348 ide_mem_index[0] = -1;
349 ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
e4bcb14c 350
bd4524ed 351 /* Second IDE channel is a CMD646 on the PCI bus */
f455e98c
GH
352 hd[0] = drive_get(IF_IDE, 1, 0);
353 hd[1] = drive_get(IF_IDE, 1, 1);
bd4524ed
AJ
354 hd[3] = hd[2] = NULL;
355 pci_cmd646_ide_init(pci_bus, hd, 0);
3cbee15b
JM
356
357 /* cuda also initialize ADB */
358 cuda_init(&cuda_mem_index, pic[0x12]);
359
360 adb_kbd_init(&adb_bus);
361 adb_mouse_init(&adb_bus);
aae9366a 362
68af3f24 363 nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
3cbee15b
JM
364 pmac_format_nvram_partition(nvr, 0x2000);
365
4ebcf884
BS
366 macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
367 dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
368 escc_mem_index);
3cbee15b
JM
369
370 if (usb_enabled) {
5b19d9a2 371 usb_ohci_init_pci(pci_bus, -1);
3cbee15b
JM
372 }
373
374 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
375 graphic_depth = 15;
376
3cbee15b
JM
377 /* No PCI init: the BIOS will do it */
378
271dd5e0
BS
379 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
380 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
381 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
382 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
513f789f
BS
383 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
384 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
385 if (kernel_cmdline) {
386 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
387 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
388 } else {
389 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
390 }
391 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
392 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
393 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
7f1aec5f
LV
394
395 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
396 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
397 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
398
513f789f 399 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
3cbee15b
JM
400}
401
f80f9ec9 402static QEMUMachine heathrow_machine = {
4d7ca41e 403 .name = "g3beige",
4b32e168
AL
404 .desc = "Heathrow based PowerMAC",
405 .init = ppc_heathrow_init,
3d878caa 406 .max_cpus = MAX_CPUS,
0c257437 407 .is_default = 1,
3cbee15b 408};
f80f9ec9
AL
409
410static void heathrow_machine_init(void)
411{
412 qemu_register_machine(&heathrow_machine);
413}
414
415machine_init(heathrow_machine_init);