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Commit | Line | Data |
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3cbee15b | 1 | /* |
4d7ca41e | 2 | * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator |
3cbee15b JM |
3 | * |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
87ecb68b PB |
25 | #include "hw.h" |
26 | #include "ppc.h" | |
3cbee15b | 27 | #include "ppc_mac.h" |
28ce5ce6 | 28 | #include "mac_dbdma.h" |
87ecb68b PB |
29 | #include "nvram.h" |
30 | #include "pc.h" | |
31 | #include "sysemu.h" | |
32 | #include "net.h" | |
33 | #include "isa.h" | |
34 | #include "pci.h" | |
35 | #include "boards.h" | |
271dd5e0 | 36 | #include "fw_cfg.h" |
7fa9ae1a | 37 | #include "escc.h" |
3cbee15b | 38 | |
e4bcb14c | 39 | #define MAX_IDE_BUS 2 |
a748ab6d | 40 | #define VGA_BIOS_SIZE 65536 |
271dd5e0 BS |
41 | #define CFG_ADDR 0xf0000510 |
42 | ||
3cbee15b JM |
43 | /* temporary frame buffer OSI calls for the video.x driver. The right |
44 | solution is to modify the driver to use VGA PCI I/Os */ | |
45 | /* XXX: to be removed. This is no way related to emulation */ | |
46 | static int vga_osi_call (CPUState *env) | |
47 | { | |
48 | static int vga_vbl_enabled; | |
49 | int linesize; | |
50 | ||
aae9366a | 51 | // printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5)); |
3cbee15b JM |
52 | |
53 | /* same handler as PearPC, coming from the original MOL video | |
54 | driver. */ | |
55 | switch(env->gpr[5]) { | |
56 | case 4: | |
57 | break; | |
58 | case 28: /* set_vmode */ | |
59 | if (env->gpr[6] != 1 || env->gpr[7] != 0) | |
60 | env->gpr[3] = 1; | |
61 | else | |
62 | env->gpr[3] = 0; | |
63 | break; | |
64 | case 29: /* get_vmode_info */ | |
65 | if (env->gpr[6] != 0) { | |
66 | if (env->gpr[6] != 1 || env->gpr[7] != 0) { | |
67 | env->gpr[3] = 1; | |
68 | break; | |
69 | } | |
70 | } | |
71 | env->gpr[3] = 0; | |
72 | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ | |
73 | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ | |
74 | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ | |
75 | env->gpr[7] = 85 << 16; /* refresh rate */ | |
76 | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ | |
77 | linesize = ((graphic_depth + 7) >> 3) * graphic_width; | |
78 | linesize = (linesize + 3) & ~3; | |
79 | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ | |
80 | break; | |
81 | case 31: /* set_video power */ | |
82 | env->gpr[3] = 0; | |
83 | break; | |
84 | case 39: /* video_ctrl */ | |
85 | if (env->gpr[6] == 0 || env->gpr[6] == 1) | |
86 | vga_vbl_enabled = env->gpr[6]; | |
87 | env->gpr[3] = 0; | |
88 | break; | |
89 | case 47: | |
90 | break; | |
91 | case 59: /* set_color */ | |
92 | /* R6 = index, R7 = RGB */ | |
93 | env->gpr[3] = 0; | |
94 | break; | |
95 | case 64: /* get color */ | |
96 | /* R6 = index */ | |
97 | env->gpr[3] = 0; | |
98 | break; | |
99 | case 116: /* set hwcursor */ | |
100 | /* R6 = x, R7 = y, R8 = visible, R9 = data */ | |
101 | break; | |
102 | default: | |
aae9366a JM |
103 | fprintf(stderr, "unsupported OSI call R5=" REGX "\n", |
104 | ppc_dump_gpr(env, 5)); | |
3cbee15b JM |
105 | break; |
106 | } | |
107 | ||
108 | return 1; /* osi_call handled */ | |
109 | } | |
110 | ||
00f82b8a | 111 | static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size, |
3023f332 | 112 | const char *boot_device, |
3cbee15b JM |
113 | const char *kernel_filename, |
114 | const char *kernel_cmdline, | |
115 | const char *initrd_filename, | |
116 | const char *cpu_model) | |
117 | { | |
aaed909a | 118 | CPUState *env = NULL, *envs[MAX_CPUS]; |
3cbee15b JM |
119 | char buf[1024]; |
120 | qemu_irq *pic, **heathrow_irqs; | |
121 | nvram_t nvram; | |
122 | m48t59_t *m48t59; | |
123 | int linux_boot, i; | |
a748ab6d | 124 | ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset; |
7373048c BS |
125 | uint32_t kernel_base, initrd_base; |
126 | int32_t kernel_size, initrd_size; | |
3cbee15b JM |
127 | PCIBus *pci_bus; |
128 | MacIONVRAMState *nvr; | |
129 | int vga_bios_size, bios_size; | |
3cbee15b | 130 | int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index; |
7fa9ae1a | 131 | int escc_mem_index, ide_mem_index[2]; |
28c5af54 | 132 | int ppc_boot_device; |
e4bcb14c TS |
133 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
134 | int index; | |
271dd5e0 | 135 | void *fw_cfg; |
28ce5ce6 | 136 | void *dbdma; |
3cbee15b JM |
137 | |
138 | linux_boot = (kernel_filename != NULL); | |
139 | ||
140 | /* init CPUs */ | |
3cbee15b | 141 | if (cpu_model == NULL) |
f2fde45a | 142 | cpu_model = "G3"; |
3cbee15b | 143 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
144 | env = cpu_init(cpu_model); |
145 | if (!env) { | |
146 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
147 | exit(1); | |
148 | } | |
b0fb43d8 AJ |
149 | /* Set time-base frequency to 16.6 Mhz */ |
150 | cpu_ppc_tb_init(env, 16600000UL); | |
3cbee15b JM |
151 | env->osi_call = vga_osi_call; |
152 | qemu_register_reset(&cpu_ppc_reset, env); | |
3cbee15b JM |
153 | envs[i] = env; |
154 | } | |
155 | ||
156 | /* allocate RAM */ | |
6b4079f8 AJ |
157 | if (ram_size > (2047 << 20)) { |
158 | fprintf(stderr, | |
159 | "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", | |
160 | ((unsigned int)ram_size / (1 << 20))); | |
161 | exit(1); | |
162 | } | |
163 | ||
a748ab6d AJ |
164 | ram_offset = qemu_ram_alloc(ram_size); |
165 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
166 | ||
167 | /* allocate VGA RAM */ | |
168 | vga_ram_offset = qemu_ram_alloc(vga_ram_size); | |
3cbee15b JM |
169 | |
170 | /* allocate and load BIOS */ | |
a748ab6d | 171 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
3cbee15b | 172 | if (bios_name == NULL) |
992e5acd | 173 | bios_name = PROM_FILENAME; |
3cbee15b | 174 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
992e5acd BS |
175 | cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); |
176 | ||
177 | /* Load OpenBIOS (ELF) */ | |
178 | bios_size = load_elf(buf, 0, NULL, NULL, NULL); | |
3cbee15b JM |
179 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
180 | cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf); | |
181 | exit(1); | |
182 | } | |
3cbee15b JM |
183 | |
184 | /* allocate and load VGA BIOS */ | |
a748ab6d | 185 | vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE); |
3cbee15b JM |
186 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
187 | vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8); | |
188 | if (vga_bios_size < 0) { | |
189 | /* if no bios is present, we can still work */ | |
190 | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf); | |
191 | vga_bios_size = 0; | |
192 | } else { | |
193 | /* set a specific header (XXX: find real Apple format for NDRV | |
194 | drivers) */ | |
195 | phys_ram_base[vga_bios_offset] = 'N'; | |
196 | phys_ram_base[vga_bios_offset + 1] = 'D'; | |
197 | phys_ram_base[vga_bios_offset + 2] = 'R'; | |
198 | phys_ram_base[vga_bios_offset + 3] = 'V'; | |
199 | cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), | |
200 | vga_bios_size); | |
201 | vga_bios_size += 8; | |
202 | } | |
3cbee15b JM |
203 | |
204 | if (linux_boot) { | |
36bee1e3 | 205 | uint64_t lowaddr = 0; |
3cbee15b | 206 | kernel_base = KERNEL_LOAD_ADDR; |
36bee1e3 AJ |
207 | /* Now we can load the kernel. The first step tries to load the kernel |
208 | supposing PhysAddr = 0x00000000. If that was wrong the kernel is | |
209 | loaded again, the new PhysAddr being computed from lowaddr. */ | |
210 | kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL); | |
211 | if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) { | |
212 | kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr, | |
213 | NULL, 0, NULL); | |
214 | } | |
52f163b7 BS |
215 | if (kernel_size < 0) |
216 | kernel_size = load_aout(kernel_filename, kernel_base, | |
217 | ram_size - kernel_base); | |
218 | if (kernel_size < 0) | |
219 | kernel_size = load_image_targphys(kernel_filename, | |
220 | kernel_base, | |
221 | ram_size - kernel_base); | |
3cbee15b JM |
222 | if (kernel_size < 0) { |
223 | cpu_abort(env, "qemu: could not load kernel '%s'\n", | |
224 | kernel_filename); | |
225 | exit(1); | |
226 | } | |
227 | /* load initrd */ | |
228 | if (initrd_filename) { | |
229 | initrd_base = INITRD_LOAD_ADDR; | |
230 | initrd_size = load_image(initrd_filename, | |
231 | phys_ram_base + initrd_base); | |
232 | if (initrd_size < 0) { | |
233 | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", | |
234 | initrd_filename); | |
235 | exit(1); | |
236 | } | |
237 | } else { | |
238 | initrd_base = 0; | |
239 | initrd_size = 0; | |
240 | } | |
6ac0e82d | 241 | ppc_boot_device = 'm'; |
3cbee15b JM |
242 | } else { |
243 | kernel_base = 0; | |
244 | kernel_size = 0; | |
245 | initrd_base = 0; | |
246 | initrd_size = 0; | |
28c5af54 | 247 | ppc_boot_device = '\0'; |
0d913fdb | 248 | for (i = 0; boot_device[i] != '\0'; i++) { |
28c5af54 | 249 | /* TOFIX: for now, the second IDE channel is not properly |
0d913fdb | 250 | * used by OHW. The Mac floppy disk are not emulated. |
28c5af54 JM |
251 | * For now, OHW cannot boot from the network. |
252 | */ | |
253 | #if 0 | |
0d913fdb JM |
254 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
255 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 256 | break; |
0d913fdb | 257 | } |
28c5af54 | 258 | #else |
0d913fdb JM |
259 | if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { |
260 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 261 | break; |
0d913fdb | 262 | } |
28c5af54 JM |
263 | #endif |
264 | } | |
265 | if (ppc_boot_device == '\0') { | |
8a901def | 266 | fprintf(stderr, "No valid boot device for G3 Beige machine\n"); |
28c5af54 JM |
267 | exit(1); |
268 | } | |
3cbee15b JM |
269 | } |
270 | ||
271 | isa_mem_base = 0x80000000; | |
aae9366a | 272 | |
3cbee15b JM |
273 | /* Register 2 MB of ISA IO space */ |
274 | isa_mmio_init(0xfe000000, 0x00200000); | |
275 | ||
276 | /* XXX: we register only 1 output pin for heathrow PIC */ | |
277 | heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *)); | |
278 | heathrow_irqs[0] = | |
279 | qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1); | |
280 | /* Connect the heathrow PIC outputs to the 6xx bus */ | |
281 | for (i = 0; i < smp_cpus; i++) { | |
282 | switch (PPC_INPUT(env)) { | |
283 | case PPC_FLAGS_INPUT_6xx: | |
284 | heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); | |
285 | heathrow_irqs[i][0] = | |
286 | ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; | |
287 | break; | |
288 | default: | |
289 | cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n"); | |
290 | exit(1); | |
291 | } | |
292 | } | |
293 | ||
294 | /* init basic PC hardware */ | |
295 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { | |
296 | cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n"); | |
297 | exit(1); | |
298 | } | |
299 | pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs); | |
300 | pci_bus = pci_grackle_init(0xfec00000, pic); | |
3023f332 | 301 | pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset, |
a748ab6d | 302 | vga_ram_offset, vga_ram_size, |
3cbee15b | 303 | vga_bios_offset, vga_bios_size); |
aae9366a | 304 | |
aeeb69c7 | 305 | escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0], |
7fa9ae1a | 306 | serial_hds[1], ESCC_CLOCK, 4); |
aae9366a | 307 | |
cb457d76 AL |
308 | for(i = 0; i < nb_nics; i++) |
309 | pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); | |
0d913fdb | 310 | |
e4bcb14c TS |
311 | |
312 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { | |
313 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
314 | exit(1); | |
315 | } | |
bd4524ed AJ |
316 | |
317 | /* First IDE channel is a MAC IDE on the MacIO bus */ | |
e4bcb14c TS |
318 | index = drive_get_index(IF_IDE, 0, 0); |
319 | if (index == -1) | |
320 | hd[0] = NULL; | |
321 | else | |
322 | hd[0] = drives_table[index].bdrv; | |
323 | index = drive_get_index(IF_IDE, 0, 1); | |
324 | if (index == -1) | |
325 | hd[1] = NULL; | |
326 | else | |
327 | hd[1] = drives_table[index].bdrv; | |
bd4524ed AJ |
328 | dbdma = DBDMA_init(&dbdma_mem_index); |
329 | ide_mem_index[0] = -1; | |
330 | ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]); | |
e4bcb14c | 331 | |
bd4524ed | 332 | /* Second IDE channel is a CMD646 on the PCI bus */ |
e4bcb14c TS |
333 | index = drive_get_index(IF_IDE, 1, 0); |
334 | if (index == -1) | |
335 | hd[0] = NULL; | |
336 | else | |
337 | hd[0] = drives_table[index].bdrv; | |
338 | index = drive_get_index(IF_IDE, 1, 1); | |
339 | if (index == -1) | |
340 | hd[1] = NULL; | |
341 | else | |
342 | hd[1] = drives_table[index].bdrv; | |
bd4524ed AJ |
343 | hd[3] = hd[2] = NULL; |
344 | pci_cmd646_ide_init(pci_bus, hd, 0); | |
3cbee15b JM |
345 | |
346 | /* cuda also initialize ADB */ | |
347 | cuda_init(&cuda_mem_index, pic[0x12]); | |
348 | ||
349 | adb_kbd_init(&adb_bus); | |
350 | adb_mouse_init(&adb_bus); | |
aae9366a | 351 | |
68af3f24 | 352 | nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4); |
3cbee15b JM |
353 | pmac_format_nvram_partition(nvr, 0x2000); |
354 | ||
4ebcf884 BS |
355 | macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index, |
356 | dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index, | |
357 | escc_mem_index); | |
3cbee15b JM |
358 | |
359 | if (usb_enabled) { | |
360 | usb_ohci_init_pci(pci_bus, 3, -1); | |
361 | } | |
362 | ||
363 | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) | |
364 | graphic_depth = 15; | |
365 | ||
570724dc | 366 | m48t59 = m48t59_init(0, 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
3cbee15b JM |
367 | nvram.opaque = m48t59; |
368 | nvram.read_fn = &m48t59_read; | |
369 | nvram.write_fn = &m48t59_write; | |
6ac0e82d AZ |
370 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size, |
371 | ppc_boot_device, kernel_base, kernel_size, | |
3cbee15b JM |
372 | kernel_cmdline, |
373 | initrd_base, initrd_size, | |
374 | /* XXX: need an option to load a NVRAM image */ | |
375 | 0, | |
376 | graphic_width, graphic_height, graphic_depth); | |
377 | /* No PCI init: the BIOS will do it */ | |
378 | ||
271dd5e0 BS |
379 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
380 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
381 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); | |
382 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); | |
3cbee15b JM |
383 | } |
384 | ||
385 | QEMUMachine heathrow_machine = { | |
4d7ca41e | 386 | .name = "g3beige", |
4b32e168 AL |
387 | .desc = "Heathrow based PowerMAC", |
388 | .init = ppc_heathrow_init, | |
a748ab6d | 389 | .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE, |
3d878caa | 390 | .max_cpus = MAX_CPUS, |
3cbee15b | 391 | }; |