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3cbee15b 1/*
4d7ca41e 2 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
3cbee15b
JM
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
87ecb68b
PB
25#include "hw.h"
26#include "ppc.h"
3cbee15b 27#include "ppc_mac.h"
28ce5ce6 28#include "mac_dbdma.h"
87ecb68b
PB
29#include "nvram.h"
30#include "pc.h"
31#include "sysemu.h"
32#include "net.h"
33#include "isa.h"
34#include "pci.h"
35#include "boards.h"
271dd5e0 36#include "fw_cfg.h"
7fa9ae1a 37#include "escc.h"
3cbee15b 38
e4bcb14c 39#define MAX_IDE_BUS 2
a748ab6d 40#define VGA_BIOS_SIZE 65536
271dd5e0
BS
41#define CFG_ADDR 0xf0000510
42
3cbee15b
JM
43/* temporary frame buffer OSI calls for the video.x driver. The right
44 solution is to modify the driver to use VGA PCI I/Os */
45/* XXX: to be removed. This is no way related to emulation */
46static int vga_osi_call (CPUState *env)
47{
48 static int vga_vbl_enabled;
49 int linesize;
50
b11ebf64
BS
51#if 0
52 printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
53#endif
3cbee15b
JM
54
55 /* same handler as PearPC, coming from the original MOL video
56 driver. */
57 switch(env->gpr[5]) {
58 case 4:
59 break;
60 case 28: /* set_vmode */
61 if (env->gpr[6] != 1 || env->gpr[7] != 0)
62 env->gpr[3] = 1;
63 else
64 env->gpr[3] = 0;
65 break;
66 case 29: /* get_vmode_info */
67 if (env->gpr[6] != 0) {
68 if (env->gpr[6] != 1 || env->gpr[7] != 0) {
69 env->gpr[3] = 1;
70 break;
71 }
72 }
73 env->gpr[3] = 0;
74 env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
75 env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
76 env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
77 env->gpr[7] = 85 << 16; /* refresh rate */
78 env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
79 linesize = ((graphic_depth + 7) >> 3) * graphic_width;
80 linesize = (linesize + 3) & ~3;
81 env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
82 break;
83 case 31: /* set_video power */
84 env->gpr[3] = 0;
85 break;
86 case 39: /* video_ctrl */
87 if (env->gpr[6] == 0 || env->gpr[6] == 1)
88 vga_vbl_enabled = env->gpr[6];
89 env->gpr[3] = 0;
90 break;
91 case 47:
92 break;
93 case 59: /* set_color */
94 /* R6 = index, R7 = RGB */
95 env->gpr[3] = 0;
96 break;
97 case 64: /* get color */
98 /* R6 = index */
99 env->gpr[3] = 0;
100 break;
101 case 116: /* set hwcursor */
102 /* R6 = x, R7 = y, R8 = visible, R9 = data */
103 break;
104 default:
b11ebf64 105 fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
aae9366a 106 ppc_dump_gpr(env, 5));
3cbee15b
JM
107 break;
108 }
109
110 return 1; /* osi_call handled */
111}
112
513f789f
BS
113static int fw_cfg_boot_set(void *opaque, const char *boot_device)
114{
115 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
116 return 0;
117}
118
fbe1b595 119static void ppc_heathrow_init (ram_addr_t ram_size,
3023f332 120 const char *boot_device,
3cbee15b
JM
121 const char *kernel_filename,
122 const char *kernel_cmdline,
123 const char *initrd_filename,
124 const char *cpu_model)
125{
aaed909a 126 CPUState *env = NULL, *envs[MAX_CPUS];
5cea8590 127 char *filename;
3cbee15b 128 qemu_irq *pic, **heathrow_irqs;
3cbee15b 129 int linux_boot, i;
b584726d 130 ram_addr_t ram_offset, bios_offset, vga_bios_offset;
7373048c
BS
131 uint32_t kernel_base, initrd_base;
132 int32_t kernel_size, initrd_size;
3cbee15b
JM
133 PCIBus *pci_bus;
134 MacIONVRAMState *nvr;
135 int vga_bios_size, bios_size;
3cbee15b 136 int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
7fa9ae1a 137 int escc_mem_index, ide_mem_index[2];
513f789f 138 uint16_t ppc_boot_device;
e4bcb14c 139 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
751c6a17 140 DriveInfo *dinfo;
271dd5e0 141 void *fw_cfg;
28ce5ce6 142 void *dbdma;
44654490 143 uint8_t *vga_bios_ptr;
3cbee15b
JM
144
145 linux_boot = (kernel_filename != NULL);
146
147 /* init CPUs */
3cbee15b 148 if (cpu_model == NULL)
f2fde45a 149 cpu_model = "G3";
3cbee15b 150 for (i = 0; i < smp_cpus; i++) {
aaed909a
FB
151 env = cpu_init(cpu_model);
152 if (!env) {
153 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
154 exit(1);
155 }
b0fb43d8
AJ
156 /* Set time-base frequency to 16.6 Mhz */
157 cpu_ppc_tb_init(env, 16600000UL);
3cbee15b 158 env->osi_call = vga_osi_call;
a08d4367 159 qemu_register_reset(&cpu_ppc_reset, env);
3cbee15b
JM
160 envs[i] = env;
161 }
162
163 /* allocate RAM */
6b4079f8
AJ
164 if (ram_size > (2047 << 20)) {
165 fprintf(stderr,
166 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
167 ((unsigned int)ram_size / (1 << 20)));
168 exit(1);
169 }
170
a748ab6d
AJ
171 ram_offset = qemu_ram_alloc(ram_size);
172 cpu_register_physical_memory(0, ram_size, ram_offset);
173
3cbee15b 174 /* allocate and load BIOS */
a748ab6d 175 bios_offset = qemu_ram_alloc(BIOS_SIZE);
3cbee15b 176 if (bios_name == NULL)
992e5acd 177 bios_name = PROM_FILENAME;
5cea8590 178 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
992e5acd
BS
179 cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
180
181 /* Load OpenBIOS (ELF) */
5cea8590
PB
182 if (filename) {
183 bios_size = load_elf(filename, 0, NULL, NULL, NULL);
184 qemu_free(filename);
185 } else {
186 bios_size = -1;
187 }
3cbee15b 188 if (bios_size < 0 || bios_size > BIOS_SIZE) {
5cea8590 189 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
3cbee15b
JM
190 exit(1);
191 }
3cbee15b
JM
192
193 /* allocate and load VGA BIOS */
a748ab6d 194 vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
44654490 195 vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
5cea8590
PB
196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
197 if (filename) {
198 vga_bios_size = load_image(filename, vga_bios_ptr + 8);
199 qemu_free(filename);
200 } else {
201 vga_bios_size = -1;
202 }
3cbee15b
JM
203 if (vga_bios_size < 0) {
204 /* if no bios is present, we can still work */
5cea8590
PB
205 fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
206 VGABIOS_FILENAME);
3cbee15b
JM
207 vga_bios_size = 0;
208 } else {
209 /* set a specific header (XXX: find real Apple format for NDRV
210 drivers) */
44654490
PB
211 vga_bios_ptr[0] = 'N';
212 vga_bios_ptr[1] = 'D';
213 vga_bios_ptr[2] = 'R';
214 vga_bios_ptr[3] = 'V';
215 cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
3cbee15b 216 vga_bios_size += 8;
a7b022e0
AG
217
218 /* Round to page boundary */
219 vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
220 TARGET_PAGE_MASK;
3cbee15b 221 }
3cbee15b
JM
222
223 if (linux_boot) {
36bee1e3 224 uint64_t lowaddr = 0;
3cbee15b 225 kernel_base = KERNEL_LOAD_ADDR;
36bee1e3
AJ
226 /* Now we can load the kernel. The first step tries to load the kernel
227 supposing PhysAddr = 0x00000000. If that was wrong the kernel is
228 loaded again, the new PhysAddr being computed from lowaddr. */
229 kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
230 if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
231 kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
660f11be 232 NULL, NULL, NULL);
36bee1e3 233 }
52f163b7
BS
234 if (kernel_size < 0)
235 kernel_size = load_aout(kernel_filename, kernel_base,
236 ram_size - kernel_base);
237 if (kernel_size < 0)
238 kernel_size = load_image_targphys(kernel_filename,
239 kernel_base,
240 ram_size - kernel_base);
3cbee15b 241 if (kernel_size < 0) {
2ac71179 242 hw_error("qemu: could not load kernel '%s'\n",
3cbee15b
JM
243 kernel_filename);
244 exit(1);
245 }
246 /* load initrd */
247 if (initrd_filename) {
248 initrd_base = INITRD_LOAD_ADDR;
dcac9679
PB
249 initrd_size = load_image_targphys(initrd_filename, initrd_base,
250 ram_size - initrd_base);
3cbee15b 251 if (initrd_size < 0) {
2ac71179
PB
252 hw_error("qemu: could not load initial ram disk '%s'\n",
253 initrd_filename);
3cbee15b
JM
254 exit(1);
255 }
256 } else {
257 initrd_base = 0;
258 initrd_size = 0;
259 }
6ac0e82d 260 ppc_boot_device = 'm';
3cbee15b
JM
261 } else {
262 kernel_base = 0;
263 kernel_size = 0;
264 initrd_base = 0;
265 initrd_size = 0;
28c5af54 266 ppc_boot_device = '\0';
0d913fdb 267 for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54 268 /* TOFIX: for now, the second IDE channel is not properly
0d913fdb 269 * used by OHW. The Mac floppy disk are not emulated.
28c5af54
JM
270 * For now, OHW cannot boot from the network.
271 */
272#if 0
0d913fdb
JM
273 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
274 ppc_boot_device = boot_device[i];
28c5af54 275 break;
0d913fdb 276 }
28c5af54 277#else
0d913fdb
JM
278 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
279 ppc_boot_device = boot_device[i];
28c5af54 280 break;
0d913fdb 281 }
28c5af54
JM
282#endif
283 }
284 if (ppc_boot_device == '\0') {
8a901def 285 fprintf(stderr, "No valid boot device for G3 Beige machine\n");
28c5af54
JM
286 exit(1);
287 }
3cbee15b
JM
288 }
289
290 isa_mem_base = 0x80000000;
aae9366a 291
3cbee15b
JM
292 /* Register 2 MB of ISA IO space */
293 isa_mmio_init(0xfe000000, 0x00200000);
294
295 /* XXX: we register only 1 output pin for heathrow PIC */
296 heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
297 heathrow_irqs[0] =
298 qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
299 /* Connect the heathrow PIC outputs to the 6xx bus */
300 for (i = 0; i < smp_cpus; i++) {
301 switch (PPC_INPUT(env)) {
302 case PPC_FLAGS_INPUT_6xx:
303 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
304 heathrow_irqs[i][0] =
305 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
306 break;
307 default:
2ac71179 308 hw_error("Bus model not supported on OldWorld Mac machine\n");
3cbee15b
JM
309 }
310 }
311
312 /* init basic PC hardware */
313 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
2ac71179 314 hw_error("Only 6xx bus is supported on heathrow machine\n");
3cbee15b
JM
315 }
316 pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
317 pci_bus = pci_grackle_init(0xfec00000, pic);
fbe1b595 318 pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
aae9366a 319
aeeb69c7 320 escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
7fa9ae1a 321 serial_hds[1], ESCC_CLOCK, 4);
aae9366a 322
cb457d76 323 for(i = 0; i < nb_nics; i++)
5607c388 324 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
0d913fdb 325
e4bcb14c
TS
326
327 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
328 fprintf(stderr, "qemu: too many IDE bus\n");
329 exit(1);
330 }
bd4524ed
AJ
331
332 /* First IDE channel is a MAC IDE on the MacIO bus */
751c6a17
GH
333 dinfo = drive_get(IF_IDE, 0, 0);
334 hd[0] = dinfo ? dinfo->bdrv : NULL;
335 dinfo = drive_get(IF_IDE, 0, 1);
336 hd[1] = dinfo ? dinfo->bdrv : NULL;
bd4524ed
AJ
337 dbdma = DBDMA_init(&dbdma_mem_index);
338 ide_mem_index[0] = -1;
339 ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
e4bcb14c 340
bd4524ed 341 /* Second IDE channel is a CMD646 on the PCI bus */
751c6a17
GH
342 dinfo = drive_get(IF_IDE, 1, 0);
343 hd[0] = dinfo ? dinfo->bdrv : NULL;
344 dinfo = drive_get(IF_IDE, 1, 1);
345 hd[1] = dinfo ? dinfo->bdrv : NULL;
bd4524ed
AJ
346 hd[3] = hd[2] = NULL;
347 pci_cmd646_ide_init(pci_bus, hd, 0);
3cbee15b
JM
348
349 /* cuda also initialize ADB */
350 cuda_init(&cuda_mem_index, pic[0x12]);
351
352 adb_kbd_init(&adb_bus);
353 adb_mouse_init(&adb_bus);
aae9366a 354
68af3f24 355 nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
3cbee15b
JM
356 pmac_format_nvram_partition(nvr, 0x2000);
357
4ebcf884
BS
358 macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
359 dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
360 escc_mem_index);
3cbee15b
JM
361
362 if (usb_enabled) {
363 usb_ohci_init_pci(pci_bus, 3, -1);
364 }
365
366 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
367 graphic_depth = 15;
368
3cbee15b
JM
369 /* No PCI init: the BIOS will do it */
370
271dd5e0
BS
371 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
372 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
373 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
374 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
513f789f
BS
375 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
376 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
377 if (kernel_cmdline) {
378 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
379 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
380 } else {
381 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
382 }
383 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
384 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
385 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
7f1aec5f
LV
386
387 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
388 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
389 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
390
513f789f 391 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
3cbee15b
JM
392}
393
f80f9ec9 394static QEMUMachine heathrow_machine = {
4d7ca41e 395 .name = "g3beige",
4b32e168
AL
396 .desc = "Heathrow based PowerMAC",
397 .init = ppc_heathrow_init,
3d878caa 398 .max_cpus = MAX_CPUS,
0c257437 399 .is_default = 1,
3cbee15b 400};
f80f9ec9
AL
401
402static void heathrow_machine_init(void)
403{
404 qemu_register_machine(&heathrow_machine);
405}
406
407machine_init(heathrow_machine_init);