[qemu.git] / hw / ppc_prep.c

/*
 * QEMU PPC PREP hardware System Emulator
 * 
 * Copyright (c) 2003-2004 Jocelyn Mayer
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define HARD_DEBUG_PPC_IO
//#define DEBUG_PPC_IO

#define KERNEL_LOAD_ADDR 0x01000000;
#define INITRD_LOAD_ADDR 0x01800000;

extern int loglevel;
extern FILE *logfile;

#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
#define DEBUG_PPC_IO
#endif

#if defined (HARD_DEBUG_PPC_IO)
#define PPC_IO_DPRINTF(fmt, args...)                     \
do {                                                     \
    if (loglevel > 0) {                                  \
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
    } else {                                             \
        printf("%s : " fmt, __func__ , ##args);          \
    }                                                    \
} while (0)
#elif defined (DEBUG_PPC_IO)
#define PPC_IO_DPRINTF(fmt, args...)                     \
do {                                                     \
    if (loglevel > 0) {                                  \
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
    }                                                    \
} while (0)
#else
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
#endif

#define BIOS_FILENAME "ppc_rom.bin"
/* Constants for devices init */
static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 13, 13 };

#define NE2000_NB_MAX 6

static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };

//static PITState *pit;

/* ISA IO ports bridge */
#define PPC_IO_BASE 0x80000000

/* Speaker port 0x61 */
int speaker_data_on;
int dummy_refresh_clock;

static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
#if 0
    speaker_data_on = (val >> 1) & 1;
    pit_set_gate(pit, 2, val & 1);
#endif
}

static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
{
#if 0
    int out;
    out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
    dummy_refresh_clock ^= 1;
    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
      (dummy_refresh_clock << 4);
#endif
    return 0;
}

/* PCI intack register */
/* Read-only register (?) */
static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
}

static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
{
    uint32_t retval = 0;

    if (addr == 0xBFFFFFF0)
        retval = pic_intack_read(NULL);
       //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);

    return retval;
}

static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
{
    return _PPC_intack_read(addr);
}

static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef TARGET_WORDS_BIGENDIAN
    return bswap16(_PPC_intack_read(addr));
#else
    return _PPC_intack_read(addr);
#endif
}

static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
{
#ifdef TARGET_WORDS_BIGENDIAN
    return bswap32(_PPC_intack_read(addr));
#else
    return _PPC_intack_read(addr);
#endif
}

static CPUWriteMemoryFunc *PPC_intack_write[] = {
    &_PPC_intack_write,
    &_PPC_intack_write,
    &_PPC_intack_write,
};

static CPUReadMemoryFunc *PPC_intack_read[] = {
    &PPC_intack_readb,
    &PPC_intack_readw,
    &PPC_intack_readl,
};

/* PowerPC control and status registers */
#if 0 // Not used
static struct {
    /* IDs */
    uint32_t veni_devi;
    uint32_t revi;
    /* Control and status */
    uint32_t gcsr;
    uint32_t xcfr;
    uint32_t ct32;
    uint32_t mcsr;
    /* General purpose registers */
    uint32_t gprg[6];
    /* Exceptions */
    uint32_t feen;
    uint32_t fest;
    uint32_t fema;
    uint32_t fecl;
    uint32_t eeen;
    uint32_t eest;
    uint32_t eecl;
    uint32_t eeint;
    uint32_t eemck0;
    uint32_t eemck1;
    /* Error diagnostic */
} XCSR;
#endif

static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
}

static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap16(value);
#endif
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
}

static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
#ifdef TARGET_WORDS_BIGENDIAN
    value = bswap32(value);
#endif
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
}

static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
    uint32_t retval = 0;

    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);

    return retval;
}

static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
{
    uint32_t retval = 0;

    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
#ifdef TARGET_WORDS_BIGENDIAN
    retval = bswap16(retval);
#endif

    return retval;
}

static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
{
    uint32_t retval = 0;

    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
#ifdef TARGET_WORDS_BIGENDIAN
    retval = bswap32(retval);
#endif

    return retval;
}

static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
    &PPC_XCSR_writeb,
    &PPC_XCSR_writew,
    &PPC_XCSR_writel,
};

static CPUReadMemoryFunc *PPC_XCSR_read[] = {
    &PPC_XCSR_readb,
    &PPC_XCSR_readw,
    &PPC_XCSR_readl,
};

/* Fake super-io ports for PREP platform (Intel 82378ZB) */
typedef struct sysctrl_t {
    m48t59_t *nvram;
    uint8_t state;
    uint8_t syscontrol;
    uint8_t fake_io[2];
} sysctrl_t;

enum {
    STATE_HARDFILE = 0x01,
};

static sysctrl_t *sysctrl;

static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
{
    sysctrl_t *sysctrl = opaque;

    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
    sysctrl->fake_io[addr - 0x0398] = val;
}

static uint32_t PREP_io_read (void *opaque, uint32_t addr)
{
    sysctrl_t *sysctrl = opaque;

    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
                   sysctrl->fake_io[addr - 0x0398]);
    return sysctrl->fake_io[addr - 0x0398];
}

static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
{
    sysctrl_t *sysctrl = opaque;

    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
    switch (addr) {
    case 0x0092:
        /* Special port 92 */
        /* Check soft reset asked */
        if (val & 0x01) {
            //            cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
        }
        /* Check LE mode */
        if (val & 0x02) {
            printf("Little Endian mode isn't supported (yet ?)\n");
            abort();
        }
        break;
    case 0x0800:
        /* Motorola CPU configuration register : read-only */
        break;
    case 0x0802:
        /* Motorola base module feature register : read-only */
        break;
    case 0x0803:
        /* Motorola base module status register : read-only */
        break;
    case 0x0808:
        /* Hardfile light register */
        if (val & 1)
            sysctrl->state |= STATE_HARDFILE;
        else
            sysctrl->state &= ~STATE_HARDFILE;
        break;
    case 0x0810:
        /* Password protect 1 register */
        if (sysctrl->nvram != NULL)
            m48t59_toggle_lock(sysctrl->nvram, 1);
        break;
    case 0x0812:
        /* Password protect 2 register */
        if (sysctrl->nvram != NULL)
            m48t59_toggle_lock(sysctrl->nvram, 2);
        break;
    case 0x0814:
        /* L2 invalidate register */
        //        tlb_flush(cpu_single_env, 1);
        break;
    case 0x081C:
        /* system control register */
        sysctrl->syscontrol = val & 0x0F;
        break;
    case 0x0850:
        /* I/O map type register */
        if (!(val & 0x01)) {
            printf("No support for non-continuous I/O map mode\n");
            abort();
        }
        break;
    default:
        printf("ERROR: unaffected IO port write: %04lx => %02x\n",
               (long)addr, val);
        break;
    }
}

static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
{
    sysctrl_t *sysctrl = opaque;
    uint32_t retval = 0xFF;

    switch (addr) {
    case 0x0092:
        /* Special port 92 */
        retval = 0x00;
        break;
    case 0x0800:
        /* Motorola CPU configuration register */
        retval = 0xEF; /* MPC750 */
        break;
    case 0x0802:
        /* Motorola Base module feature register */
        retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
        break;
    case 0x0803:
        /* Motorola base module status register */
        retval = 0xE0; /* Standard MPC750 */
        break;
    case 0x080C:
        /* Equipment present register:
         *  no L2 cache
         *  no upgrade processor
         *  no cards in PCI slots
         *  SCSI fuse is bad
         */
        retval = 0x3C;
        break;
    case 0x0810:
        /* Motorola base module extended feature register */
        retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
        break;
    case 0x0818:
        /* Keylock */
        retval = 0x00;
        break;
    case 0x081C:
        /* system control register
         * 7 - 6 / 1 - 0: L2 cache enable
         */
        retval = sysctrl->syscontrol;
        break;
    case 0x0823:
        /* */
        retval = 0x03; /* no L2 cache */
        break;
    case 0x0850:
        /* I/O map type register */
        retval = 0x01;
        break;
    default:
        printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
        break;
    }
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);

    return retval;
}

extern CPUPPCState *global_env;

#define NVRAM_SIZE        0x2000

/* PowerPC PREP hardware initialisation */
void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
		   DisplayState *ds, const char **fd_filename, int snapshot,
		   const char *kernel_filename, const char *kernel_cmdline,
		   const char *initrd_filename)
{
    char buf[1024];
    //    void *openpic;
    m48t59_t *nvram;
    int PPC_io_memory;
    int ret, linux_boot, i, nb_nics1, fd;
    unsigned long bios_offset;
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;

    sysctrl = qemu_mallocz(sizeof(sysctrl_t));
    if (sysctrl == NULL)
	return;

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    /* allocate and load BIOS */
    bios_offset = ram_size + vga_ram_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
    ret = load_image(buf, phys_ram_base + bios_offset);
    if (ret != BIOS_SIZE) {
        fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
        exit(1);
    }
    cpu_register_physical_memory((uint32_t)(-BIOS_SIZE), 
                                 BIOS_SIZE, bios_offset | IO_MEM_ROM);
    cpu_single_env->nip = 0xfffffffc;

    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
                    kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image(initrd_filename,
                                     phys_ram_base + initrd_base);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
                        initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
    }

    /* Register CPU as a 74x/75x */
    cpu_ppc_register(cpu_single_env, 0x00080000);
    /* Set time-base frequency to 100 Mhz */
    cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);

    isa_mem_base = 0xc0000000;
    pci_prep_init();
    /* Register 64 KB of ISA IO space */
    PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
    cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory);

    /* init basic PC hardware */
    vga_initialize(ds, phys_ram_base + ram_size, ram_size, 
                   vga_ram_size, 1);
    rtc_init(0x70, 8);
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
    //    pic_init(openpic);
    pic_init();
    //    pit = pit_init(0x40, 0);

    fd = serial_open_device();
    serial_init(0x3f8, 4, fd);
    nb_nics1 = nb_nics;
    if (nb_nics1 > NE2000_NB_MAX)
        nb_nics1 = NE2000_NB_MAX;
    for(i = 0; i < nb_nics1; i++) {
        isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
    }

    for(i = 0; i < 2; i++) {
        isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
                     bs_table[2 * i], bs_table[2 * i + 1]);
    }
    kbd_init();
    DMA_init();
    //    AUD_init();
    //    SB16_init();

    fdctrl_init(6, 2, 0, 0x3f0, fd_table);

    /* Register speaker port */
    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
    /* Register fake IO ports for PREP */
    register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
    register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
    /* System control ports */
    register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
    register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
    /* PCI intack location */
    PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
                                           PPC_intack_write, NULL);
    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
    /* PowerPC control and status register group */
    PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
    cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);

    nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
    if (nvram == NULL)
        return;
    sysctrl->nvram = nvram;

    /* Initialise NVRAM */
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
                         kernel_base, kernel_size,
                         (uint32_t)(long)kernel_cmdline,
                         strlen(kernel_cmdline),
                         initrd_base, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0
                         );

    /* Special port to get debug messages from Open-Firmware */
    register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
    register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);

    pci_ppc_bios_init();
}
Commit	Line	Data
9a64fbe4	1	/*
a541f297 FB	2	* QEMU PPC PREP hardware System Emulator
	3	*
	4	* Copyright (c) 2003-2004 Jocelyn Mayer
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
9a64fbe4	23	*/
9a64fbe4	24	#include "vl.h"
9fddaa0c	25
9a64fbe4	26	//#define HARD_DEBUG_PPC_IO
a541f297	27	//#define DEBUG_PPC_IO
9a64fbe4	28
64201201 FB	29	#define KERNEL_LOAD_ADDR 0x01000000;
	30	#define INITRD_LOAD_ADDR 0x01800000;
	31
9a64fbe4 FB	32	extern int loglevel;
	33	extern FILE *logfile;
	34
	35	#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
	36	#define DEBUG_PPC_IO
	37	#endif
	38
	39	#if defined (HARD_DEBUG_PPC_IO)
	40	#define PPC_IO_DPRINTF(fmt, args...) \
	41	do { \
	42	if (loglevel > 0) { \
	43	fprintf(logfile, "%s: " fmt, __func__ , ##args); \
	44	} else { \
	45	printf("%s : " fmt, __func__ , ##args); \
	46	} \
	47	} while (0)
	48	#elif defined (DEBUG_PPC_IO)
	49	#define PPC_IO_DPRINTF(fmt, args...) \
	50	do { \
	51	if (loglevel > 0) { \
	52	fprintf(logfile, "%s: " fmt, __func__ , ##args); \
	53	} \
	54	} while (0)
	55	#else
	56	#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
	57	#endif
	58
a541f297	59	#define BIOS_FILENAME "ppc_rom.bin"
64201201	60	/* Constants for devices init */
a541f297 FB	61	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	62	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	63	static const int ide_irq[2] = { 13, 13 };
	64
	65	#define NE2000_NB_MAX 6
	66
	67	static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
	68	static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
9a64fbe4	69
64201201 FB	70	//static PITState *pit;
	71
	72	/* ISA IO ports bridge */
9a64fbe4 FB	73	#define PPC_IO_BASE 0x80000000
9a64fbe4 FB	74
64201201 FB	75	/* Speaker port 0x61 */
	76	int speaker_data_on;
	77	int dummy_refresh_clock;
	78
	79	static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val)
9a64fbe4	80	{
a541f297	81	#if 0
64201201 FB	82	speaker_data_on = (val >> 1) & 1;
64201201 FB	83	pit_set_gate(pit, 2, val & 1);
a541f297	84	#endif
9a64fbe4 FB	85	}
9a64fbe4 FB	86
64201201	87	static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
9a64fbe4	88	{
a541f297	89	#if 0
64201201 FB	90	int out;
	91	out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
	92	dummy_refresh_clock ^= 1;
	93	return (speaker_data_on << 1) \| pit_get_gate(pit, 2) \| (out << 5) \|
	94	(dummy_refresh_clock << 4);
a541f297	95	#endif
64201201	96	return 0;
9a64fbe4 FB	97	}
9a64fbe4 FB	98
64201201 FB	99	/* PCI intack register */
64201201 FB	100	/* Read-only register (?) */
a4193c8a	101	static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value)
64201201 FB	102	{
	103	// printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
	104	}
	105
	106	static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
	107	{
	108	uint32_t retval = 0;
	109
	110	if (addr == 0xBFFFFFF0)
	111	retval = pic_intack_read(NULL);
	112	// printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
	113
	114	return retval;
	115	}
	116
a4193c8a	117	static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
64201201 FB	118	{
	119	return _PPC_intack_read(addr);
	120	}
	121
a4193c8a	122	static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
9a64fbe4	123	{
f658b4db	124	#ifdef TARGET_WORDS_BIGENDIAN
64201201 FB	125	return bswap16(_PPC_intack_read(addr));
	126	#else
	127	return _PPC_intack_read(addr);
f658b4db	128	#endif
9a64fbe4 FB	129	}
9a64fbe4 FB	130
a4193c8a	131	static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
9a64fbe4	132	{
f658b4db	133	#ifdef TARGET_WORDS_BIGENDIAN
64201201 FB	134	return bswap32(_PPC_intack_read(addr));
	135	#else
	136	return _PPC_intack_read(addr);
f658b4db	137	#endif
9a64fbe4 FB	138	}
9a64fbe4 FB	139
64201201 FB	140	static CPUWriteMemoryFunc *PPC_intack_write[] = {
	141	&_PPC_intack_write,
	142	&_PPC_intack_write,
	143	&_PPC_intack_write,
	144	};
	145
	146	static CPUReadMemoryFunc *PPC_intack_read[] = {
	147	&PPC_intack_readb,
	148	&PPC_intack_readw,
	149	&PPC_intack_readl,
	150	};
	151
	152	/* PowerPC control and status registers */
	153	#if 0 // Not used
	154	static struct {
	155	/* IDs */
	156	uint32_t veni_devi;
	157	uint32_t revi;
	158	/* Control and status */
	159	uint32_t gcsr;
	160	uint32_t xcfr;
	161	uint32_t ct32;
	162	uint32_t mcsr;
	163	/* General purpose registers */
	164	uint32_t gprg[6];
	165	/* Exceptions */
	166	uint32_t feen;
	167	uint32_t fest;
	168	uint32_t fema;
	169	uint32_t fecl;
	170	uint32_t eeen;
	171	uint32_t eest;
	172	uint32_t eecl;
	173	uint32_t eeint;
	174	uint32_t eemck0;
	175	uint32_t eemck1;
	176	/* Error diagnostic */
	177	} XCSR;
	178	#endif
	179
a4193c8a	180	static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
64201201 FB	181	{
	182	printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
	183	}
	184
a4193c8a	185	static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
9a64fbe4	186	{
f658b4db	187	#ifdef TARGET_WORDS_BIGENDIAN
64201201	188	value = bswap16(value);
f658b4db	189	#endif
64201201	190	printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
9a64fbe4 FB	191	}
9a64fbe4 FB	192
a4193c8a	193	static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
9a64fbe4	194	{
f658b4db	195	#ifdef TARGET_WORDS_BIGENDIAN
64201201	196	value = bswap32(value);
f658b4db	197	#endif
64201201	198	printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
9a64fbe4 FB	199	}
9a64fbe4 FB	200
a4193c8a	201	static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
64201201 FB	202	{
64201201 FB	203	uint32_t retval = 0;
9a64fbe4	204
64201201	205	printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
9a64fbe4	206
64201201 FB	207	return retval;
	208	}
	209
a4193c8a	210	static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
9a64fbe4	211	{
64201201 FB	212	uint32_t retval = 0;
	213
	214	printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
	215	#ifdef TARGET_WORDS_BIGENDIAN
	216	retval = bswap16(retval);
	217	#endif
	218
	219	return retval;
9a64fbe4 FB	220	}
9a64fbe4 FB	221
a4193c8a	222	static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
9a64fbe4 FB	223	{
	224	uint32_t retval = 0;
	225
64201201 FB	226	printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
	227	#ifdef TARGET_WORDS_BIGENDIAN
	228	retval = bswap32(retval);
	229	#endif
9a64fbe4 FB	230
	231	return retval;
	232	}
	233
64201201 FB	234	static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
	235	&PPC_XCSR_writeb,
	236	&PPC_XCSR_writew,
	237	&PPC_XCSR_writel,
9a64fbe4 FB	238	};
9a64fbe4 FB	239
64201201 FB	240	static CPUReadMemoryFunc *PPC_XCSR_read[] = {
	241	&PPC_XCSR_readb,
	242	&PPC_XCSR_readw,
	243	&PPC_XCSR_readl,
9a64fbe4 FB	244	};
9a64fbe4 FB	245
64201201 FB	246	/* Fake super-io ports for PREP platform (Intel 82378ZB) */
	247	typedef struct sysctrl_t {
	248	m48t59_t *nvram;
	249	uint8_t state;
	250	uint8_t syscontrol;
	251	uint8_t fake_io[2];
	252	} sysctrl_t;
9a64fbe4	253
64201201 FB	254	enum {
64201201 FB	255	STATE_HARDFILE = 0x01,
9a64fbe4	256	};
9a64fbe4	257
64201201	258	static sysctrl_t *sysctrl;
9a64fbe4	259
a541f297	260	static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
9a64fbe4	261	{
64201201 FB	262	sysctrl_t *sysctrl = opaque;
	263
	264	PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
	265	sysctrl->fake_io[addr - 0x0398] = val;
9a64fbe4 FB	266	}
9a64fbe4 FB	267
a541f297	268	static uint32_t PREP_io_read (void *opaque, uint32_t addr)
9a64fbe4	269	{
64201201	270	sysctrl_t *sysctrl = opaque;
9a64fbe4	271
64201201 FB	272	PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
	273	sysctrl->fake_io[addr - 0x0398]);
	274	return sysctrl->fake_io[addr - 0x0398];
	275	}
9a64fbe4	276
a541f297	277	static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
9a64fbe4	278	{
64201201 FB	279	sysctrl_t *sysctrl = opaque;
	280
	281	PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
9a64fbe4 FB	282	switch (addr) {
	283	case 0x0092:
	284	/* Special port 92 */
	285	/* Check soft reset asked */
64201201 FB	286	if (val & 0x01) {
64201201 FB	287	// cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
9a64fbe4 FB	288	}
9a64fbe4 FB	289	/* Check LE mode */
64201201	290	if (val & 0x02) {
9a64fbe4 FB	291	printf("Little Endian mode isn't supported (yet ?)\n");
	292	abort();
	293	}
	294	break;
64201201 FB	295	case 0x0800:
	296	/* Motorola CPU configuration register : read-only */
	297	break;
	298	case 0x0802:
	299	/* Motorola base module feature register : read-only */
	300	break;
	301	case 0x0803:
	302	/* Motorola base module status register : read-only */
	303	break;
9a64fbe4	304	case 0x0808:
64201201 FB	305	/* Hardfile light register */
	306	if (val & 1)
	307	sysctrl->state \|= STATE_HARDFILE;
	308	else
	309	sysctrl->state &= ~STATE_HARDFILE;
9a64fbe4 FB	310	break;
	311	case 0x0810:
	312	/* Password protect 1 register */
64201201 FB	313	if (sysctrl->nvram != NULL)
64201201 FB	314	m48t59_toggle_lock(sysctrl->nvram, 1);
9a64fbe4 FB	315	break;
	316	case 0x0812:
	317	/* Password protect 2 register */
64201201 FB	318	if (sysctrl->nvram != NULL)
64201201 FB	319	m48t59_toggle_lock(sysctrl->nvram, 2);
9a64fbe4 FB	320	break;
9a64fbe4 FB	321	case 0x0814:
64201201 FB	322	/* L2 invalidate register */
64201201 FB	323	// tlb_flush(cpu_single_env, 1);
9a64fbe4 FB	324	break;
	325	case 0x081C:
	326	/* system control register */
64201201	327	sysctrl->syscontrol = val & 0x0F;
9a64fbe4 FB	328	break;
	329	case 0x0850:
	330	/* I/O map type register */
64201201	331	if (!(val & 0x01)) {
9a64fbe4 FB	332	printf("No support for non-continuous I/O map mode\n");
	333	abort();
	334	}
	335	break;
	336	default:
64201201 FB	337	printf("ERROR: unaffected IO port write: %04lx => %02x\n",
64201201 FB	338	(long)addr, val);
9a64fbe4 FB	339	break;
	340	}
	341	}
	342
a541f297	343	static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
9a64fbe4	344	{
64201201	345	sysctrl_t *sysctrl = opaque;
9a64fbe4 FB	346	uint32_t retval = 0xFF;
	347
	348	switch (addr) {
	349	case 0x0092:
	350	/* Special port 92 */
64201201 FB	351	retval = 0x00;
	352	break;
	353	case 0x0800:
	354	/* Motorola CPU configuration register */
	355	retval = 0xEF; /* MPC750 */
	356	break;
	357	case 0x0802:
	358	/* Motorola Base module feature register */
	359	retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
	360	break;
	361	case 0x0803:
	362	/* Motorola base module status register */
	363	retval = 0xE0; /* Standard MPC750 */
9a64fbe4 FB	364	break;
	365	case 0x080C:
	366	/* Equipment present register:
	367	* no L2 cache
	368	* no upgrade processor
	369	* no cards in PCI slots
	370	* SCSI fuse is bad
	371	*/
64201201 FB	372	retval = 0x3C;
	373	break;
	374	case 0x0810:
	375	/* Motorola base module extended feature register */
	376	retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
9a64fbe4 FB	377	break;
	378	case 0x0818:
	379	/* Keylock */
	380	retval = 0x00;
	381	break;
	382	case 0x081C:
	383	/* system control register
	384	* 7 - 6 / 1 - 0: L2 cache enable
	385	*/
64201201	386	retval = sysctrl->syscontrol;
9a64fbe4 FB	387	break;
	388	case 0x0823:
	389	/* */
	390	retval = 0x03; /* no L2 cache */
	391	break;
	392	case 0x0850:
	393	/* I/O map type register */
64201201	394	retval = 0x01;
9a64fbe4 FB	395	break;
9a64fbe4 FB	396	default:
64201201	397	printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
9a64fbe4 FB	398	break;
9a64fbe4 FB	399	}
64201201	400	PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
9a64fbe4 FB	401
	402	return retval;
	403	}
	404
a541f297 FB	405	extern CPUPPCState *global_env;
a541f297 FB	406
64201201	407	#define NVRAM_SIZE 0x2000
a541f297	408
26aa7d72	409	/* PowerPC PREP hardware initialisation */
a541f297 FB	410	void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
	411	DisplayState ds, const char *fd_filename, int snapshot,
	412	const char kernel_filename, const char kernel_cmdline,
	413	const char *initrd_filename)
	414	{
	415	char buf[1024];
64201201 FB	416	// void *openpic;
64201201 FB	417	m48t59_t *nvram;
a541f297	418	int PPC_io_memory;
64201201 FB	419	int ret, linux_boot, i, nb_nics1, fd;
	420	unsigned long bios_offset;
	421	uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
	422
	423	sysctrl = qemu_mallocz(sizeof(sysctrl_t));
	424	if (sysctrl == NULL)
	425	return;
a541f297 FB	426
	427	linux_boot = (kernel_filename != NULL);
	428
	429	/* allocate RAM */
64201201 FB	430	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
	431
	432	/* allocate and load BIOS */
	433	bios_offset = ram_size + vga_ram_size;
	434	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
	435	ret = load_image(buf, phys_ram_base + bios_offset);
	436	if (ret != BIOS_SIZE) {
	437	fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
	438	exit(1);
	439	}
	440	cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
	441	BIOS_SIZE, bios_offset \| IO_MEM_ROM);
	442	cpu_single_env->nip = 0xfffffffc;
26aa7d72	443
a541f297	444	if (linux_boot) {
64201201	445	kernel_base = KERNEL_LOAD_ADDR;
a541f297	446	/* now we can load the kernel */
64201201 FB	447	kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
64201201 FB	448	if (kernel_size < 0) {
a541f297 FB	449	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	450	kernel_filename);
	451	exit(1);
	452	}
	453	/* load initrd */
a541f297	454	if (initrd_filename) {
64201201 FB	455	initrd_base = INITRD_LOAD_ADDR;
	456	initrd_size = load_image(initrd_filename,
	457	phys_ram_base + initrd_base);
a541f297 FB	458	if (initrd_size < 0) {
	459	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	460	initrd_filename);
	461	exit(1);
	462	}
64201201 FB	463	} else {
	464	initrd_base = 0;
	465	initrd_size = 0;
a541f297	466	}
64201201	467	boot_device = 'm';
a541f297	468	} else {
64201201 FB	469	kernel_base = 0;
	470	kernel_size = 0;
	471	initrd_base = 0;
	472	initrd_size = 0;
a541f297 FB	473	}
a541f297 FB	474
a2a444d6 FB	475	/* Register CPU as a 74x/75x */
	476	cpu_ppc_register(cpu_single_env, 0x00080000);
	477	/* Set time-base frequency to 100 Mhz */
9fddaa0c FB	478	cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
9fddaa0c FB	479
64201201 FB	480	isa_mem_base = 0xc0000000;
	481	pci_prep_init();
	482	/* Register 64 KB of ISA IO space */
a4193c8a	483	PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
64201201 FB	484	cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory);
64201201 FB	485
a541f297 FB	486	/* init basic PC hardware */
a541f297 FB	487	vga_initialize(ds, phys_ram_base + ram_size, ram_size,
64201201	488	vga_ram_size, 1);
a541f297	489	rtc_init(0x70, 8);
64201201 FB	490	// openpic = openpic_init(0x00000000, 0xF0000000, 1);
64201201 FB	491	// pic_init(openpic);
a541f297	492	pic_init();
64201201	493	// pit = pit_init(0x40, 0);
a541f297 FB	494
	495	fd = serial_open_device();
	496	serial_init(0x3f8, 4, fd);
a541f297 FB	497	nb_nics1 = nb_nics;
	498	if (nb_nics1 > NE2000_NB_MAX)
	499	nb_nics1 = NE2000_NB_MAX;
	500	for(i = 0; i < nb_nics1; i++) {
69b91039	501	isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
a541f297	502	}
a541f297 FB	503
a541f297 FB	504	for(i = 0; i < 2; i++) {
69b91039 FB	505	isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
69b91039 FB	506	bs_table[2 * i], bs_table[2 * i + 1]);
a541f297 FB	507	}
a541f297 FB	508	kbd_init();
a541f297	509	DMA_init();
64201201	510	// AUD_init();
a541f297 FB	511	// SB16_init();
	512
	513	fdctrl_init(6, 2, 0, 0x3f0, fd_table);
	514
64201201 FB	515	/* Register speaker port */
	516	register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
	517	register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
a541f297	518	/* Register fake IO ports for PREP */
64201201 FB	519	register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
64201201 FB	520	register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
a541f297	521	/* System control ports */
64201201 FB	522	register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
	523	register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
	524	register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
	525	register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
	526	/* PCI intack location */
	527	PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
a4193c8a	528	PPC_intack_write, NULL);
a541f297	529	cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
64201201	530	/* PowerPC control and status register group */
a4193c8a	531	PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
64201201	532	cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
a541f297	533
64201201 FB	534	nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
	535	if (nvram == NULL)
	536	return;
	537	sysctrl->nvram = nvram;
	538
	539	/* Initialise NVRAM */
	540	PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
	541	kernel_base, kernel_size,
	542	(uint32_t)(long)kernel_cmdline,
	543	strlen(kernel_cmdline),
	544	initrd_base, initrd_size,
	545	/* XXX: need an option to load a NVRAM image */
	546	0
	547	);
	548
	549	/* Special port to get debug messages from Open-Firmware */
	550	register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
	551	register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);
	552
	553	pci_ppc_bios_init();
a541f297	554	}