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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
9a64fbe4 | 24 | #include "vl.h" |
9fddaa0c | 25 | |
9a64fbe4 | 26 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 27 | //#define DEBUG_PPC_IO |
9a64fbe4 | 28 | |
b6b8bd18 FB |
29 | #define BIOS_FILENAME "ppc_rom.bin" |
30 | #define KERNEL_LOAD_ADDR 0x01000000 | |
31 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 32 | |
9a64fbe4 FB |
33 | extern int loglevel; |
34 | extern FILE *logfile; | |
35 | ||
36 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) | |
37 | #define DEBUG_PPC_IO | |
38 | #endif | |
39 | ||
40 | #if defined (HARD_DEBUG_PPC_IO) | |
41 | #define PPC_IO_DPRINTF(fmt, args...) \ | |
42 | do { \ | |
b6b8bd18 | 43 | if (loglevel & CPU_LOG_IOPORT) { \ |
9a64fbe4 FB |
44 | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
45 | } else { \ | |
46 | printf("%s : " fmt, __func__ , ##args); \ | |
47 | } \ | |
48 | } while (0) | |
49 | #elif defined (DEBUG_PPC_IO) | |
50 | #define PPC_IO_DPRINTF(fmt, args...) \ | |
51 | do { \ | |
b6b8bd18 | 52 | if (loglevel & CPU_LOG_IOPORT) { \ |
9a64fbe4 FB |
53 | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
54 | } \ | |
55 | } while (0) | |
56 | #else | |
57 | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) | |
58 | #endif | |
59 | ||
64201201 | 60 | /* Constants for devices init */ |
a541f297 FB |
61 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
62 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
63 | static const int ide_irq[2] = { 13, 13 }; | |
64 | ||
65 | #define NE2000_NB_MAX 6 | |
66 | ||
67 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
68 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 69 | |
64201201 FB |
70 | //static PITState *pit; |
71 | ||
72 | /* ISA IO ports bridge */ | |
9a64fbe4 FB |
73 | #define PPC_IO_BASE 0x80000000 |
74 | ||
64201201 FB |
75 | /* Speaker port 0x61 */ |
76 | int speaker_data_on; | |
77 | int dummy_refresh_clock; | |
78 | ||
36081602 | 79 | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 80 | { |
a541f297 | 81 | #if 0 |
64201201 FB |
82 | speaker_data_on = (val >> 1) & 1; |
83 | pit_set_gate(pit, 2, val & 1); | |
a541f297 | 84 | #endif |
9a64fbe4 FB |
85 | } |
86 | ||
47103572 | 87 | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
9a64fbe4 | 88 | { |
a541f297 | 89 | #if 0 |
64201201 FB |
90 | int out; |
91 | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); | |
92 | dummy_refresh_clock ^= 1; | |
93 | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | | |
47103572 | 94 | (dummy_refresh_clock << 4); |
a541f297 | 95 | #endif |
64201201 | 96 | return 0; |
9a64fbe4 FB |
97 | } |
98 | ||
64201201 FB |
99 | /* PCI intack register */ |
100 | /* Read-only register (?) */ | |
47103572 JM |
101 | static void _PPC_intack_write (void *opaque, |
102 | target_phys_addr_t addr, uint32_t value) | |
64201201 FB |
103 | { |
104 | // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value); | |
105 | } | |
106 | ||
107 | static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) | |
108 | { | |
109 | uint32_t retval = 0; | |
110 | ||
111 | if (addr == 0xBFFFFFF0) | |
3de388f6 | 112 | retval = pic_intack_read(isa_pic); |
36081602 | 113 | // printf("%s: 0x%08x <= %d\n", __func__, addr, retval); |
64201201 FB |
114 | |
115 | return retval; | |
116 | } | |
117 | ||
a4193c8a | 118 | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
119 | { |
120 | return _PPC_intack_read(addr); | |
121 | } | |
122 | ||
a4193c8a | 123 | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 124 | { |
f658b4db | 125 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
126 | return bswap16(_PPC_intack_read(addr)); |
127 | #else | |
128 | return _PPC_intack_read(addr); | |
f658b4db | 129 | #endif |
9a64fbe4 FB |
130 | } |
131 | ||
a4193c8a | 132 | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 133 | { |
f658b4db | 134 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
135 | return bswap32(_PPC_intack_read(addr)); |
136 | #else | |
137 | return _PPC_intack_read(addr); | |
f658b4db | 138 | #endif |
9a64fbe4 FB |
139 | } |
140 | ||
64201201 FB |
141 | static CPUWriteMemoryFunc *PPC_intack_write[] = { |
142 | &_PPC_intack_write, | |
143 | &_PPC_intack_write, | |
144 | &_PPC_intack_write, | |
145 | }; | |
146 | ||
147 | static CPUReadMemoryFunc *PPC_intack_read[] = { | |
148 | &PPC_intack_readb, | |
149 | &PPC_intack_readw, | |
150 | &PPC_intack_readl, | |
151 | }; | |
152 | ||
153 | /* PowerPC control and status registers */ | |
154 | #if 0 // Not used | |
155 | static struct { | |
156 | /* IDs */ | |
157 | uint32_t veni_devi; | |
158 | uint32_t revi; | |
159 | /* Control and status */ | |
160 | uint32_t gcsr; | |
161 | uint32_t xcfr; | |
162 | uint32_t ct32; | |
163 | uint32_t mcsr; | |
164 | /* General purpose registers */ | |
165 | uint32_t gprg[6]; | |
166 | /* Exceptions */ | |
167 | uint32_t feen; | |
168 | uint32_t fest; | |
169 | uint32_t fema; | |
170 | uint32_t fecl; | |
171 | uint32_t eeen; | |
172 | uint32_t eest; | |
173 | uint32_t eecl; | |
174 | uint32_t eeint; | |
175 | uint32_t eemck0; | |
176 | uint32_t eemck1; | |
177 | /* Error diagnostic */ | |
178 | } XCSR; | |
64201201 | 179 | |
36081602 JM |
180 | static void PPC_XCSR_writeb (void *opaque, |
181 | target_phys_addr_t addr, uint32_t value) | |
64201201 FB |
182 | { |
183 | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); | |
184 | } | |
185 | ||
36081602 JM |
186 | static void PPC_XCSR_writew (void *opaque, |
187 | target_phys_addr_t addr, uint32_t value) | |
9a64fbe4 | 188 | { |
f658b4db | 189 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 190 | value = bswap16(value); |
f658b4db | 191 | #endif |
64201201 | 192 | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
9a64fbe4 FB |
193 | } |
194 | ||
36081602 JM |
195 | static void PPC_XCSR_writel (void *opaque, |
196 | target_phys_addr_t addr, uint32_t value) | |
9a64fbe4 | 197 | { |
f658b4db | 198 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 199 | value = bswap32(value); |
f658b4db | 200 | #endif |
64201201 | 201 | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
9a64fbe4 FB |
202 | } |
203 | ||
a4193c8a | 204 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
205 | { |
206 | uint32_t retval = 0; | |
9a64fbe4 | 207 | |
64201201 | 208 | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
9a64fbe4 | 209 | |
64201201 FB |
210 | return retval; |
211 | } | |
212 | ||
a4193c8a | 213 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 214 | { |
64201201 FB |
215 | uint32_t retval = 0; |
216 | ||
217 | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); | |
218 | #ifdef TARGET_WORDS_BIGENDIAN | |
219 | retval = bswap16(retval); | |
220 | #endif | |
221 | ||
222 | return retval; | |
9a64fbe4 FB |
223 | } |
224 | ||
a4193c8a | 225 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 FB |
226 | { |
227 | uint32_t retval = 0; | |
228 | ||
64201201 FB |
229 | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
230 | #ifdef TARGET_WORDS_BIGENDIAN | |
231 | retval = bswap32(retval); | |
232 | #endif | |
9a64fbe4 FB |
233 | |
234 | return retval; | |
235 | } | |
236 | ||
64201201 FB |
237 | static CPUWriteMemoryFunc *PPC_XCSR_write[] = { |
238 | &PPC_XCSR_writeb, | |
239 | &PPC_XCSR_writew, | |
240 | &PPC_XCSR_writel, | |
9a64fbe4 FB |
241 | }; |
242 | ||
64201201 FB |
243 | static CPUReadMemoryFunc *PPC_XCSR_read[] = { |
244 | &PPC_XCSR_readb, | |
245 | &PPC_XCSR_readw, | |
246 | &PPC_XCSR_readl, | |
9a64fbe4 | 247 | }; |
b6b8bd18 | 248 | #endif |
9a64fbe4 | 249 | |
64201201 FB |
250 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
251 | typedef struct sysctrl_t { | |
252 | m48t59_t *nvram; | |
253 | uint8_t state; | |
254 | uint8_t syscontrol; | |
255 | uint8_t fake_io[2]; | |
da9b266b | 256 | int contiguous_map; |
fb3444b8 | 257 | int endian; |
64201201 | 258 | } sysctrl_t; |
9a64fbe4 | 259 | |
64201201 FB |
260 | enum { |
261 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 262 | }; |
9a64fbe4 | 263 | |
64201201 | 264 | static sysctrl_t *sysctrl; |
9a64fbe4 | 265 | |
a541f297 | 266 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 267 | { |
64201201 FB |
268 | sysctrl_t *sysctrl = opaque; |
269 | ||
270 | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); | |
271 | sysctrl->fake_io[addr - 0x0398] = val; | |
9a64fbe4 FB |
272 | } |
273 | ||
a541f297 | 274 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
9a64fbe4 | 275 | { |
64201201 | 276 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 | 277 | |
64201201 FB |
278 | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, |
279 | sysctrl->fake_io[addr - 0x0398]); | |
280 | return sysctrl->fake_io[addr - 0x0398]; | |
281 | } | |
9a64fbe4 | 282 | |
a541f297 | 283 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 284 | { |
64201201 FB |
285 | sysctrl_t *sysctrl = opaque; |
286 | ||
287 | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
288 | switch (addr) { |
289 | case 0x0092: | |
290 | /* Special port 92 */ | |
291 | /* Check soft reset asked */ | |
64201201 | 292 | if (val & 0x01) { |
47103572 | 293 | // cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET); |
9a64fbe4 FB |
294 | } |
295 | /* Check LE mode */ | |
64201201 | 296 | if (val & 0x02) { |
fb3444b8 FB |
297 | sysctrl->endian = 1; |
298 | } else { | |
299 | sysctrl->endian = 0; | |
9a64fbe4 FB |
300 | } |
301 | break; | |
64201201 FB |
302 | case 0x0800: |
303 | /* Motorola CPU configuration register : read-only */ | |
304 | break; | |
305 | case 0x0802: | |
306 | /* Motorola base module feature register : read-only */ | |
307 | break; | |
308 | case 0x0803: | |
309 | /* Motorola base module status register : read-only */ | |
310 | break; | |
9a64fbe4 | 311 | case 0x0808: |
64201201 FB |
312 | /* Hardfile light register */ |
313 | if (val & 1) | |
314 | sysctrl->state |= STATE_HARDFILE; | |
315 | else | |
316 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
317 | break; |
318 | case 0x0810: | |
319 | /* Password protect 1 register */ | |
64201201 FB |
320 | if (sysctrl->nvram != NULL) |
321 | m48t59_toggle_lock(sysctrl->nvram, 1); | |
9a64fbe4 FB |
322 | break; |
323 | case 0x0812: | |
324 | /* Password protect 2 register */ | |
64201201 FB |
325 | if (sysctrl->nvram != NULL) |
326 | m48t59_toggle_lock(sysctrl->nvram, 2); | |
9a64fbe4 FB |
327 | break; |
328 | case 0x0814: | |
64201201 | 329 | /* L2 invalidate register */ |
c68ea704 | 330 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
331 | break; |
332 | case 0x081C: | |
333 | /* system control register */ | |
64201201 | 334 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
335 | break; |
336 | case 0x0850: | |
337 | /* I/O map type register */ | |
da9b266b | 338 | sysctrl->contiguous_map = val & 0x01; |
9a64fbe4 FB |
339 | break; |
340 | default: | |
64201201 FB |
341 | printf("ERROR: unaffected IO port write: %04lx => %02x\n", |
342 | (long)addr, val); | |
9a64fbe4 FB |
343 | break; |
344 | } | |
345 | } | |
346 | ||
a541f297 | 347 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 348 | { |
64201201 | 349 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
350 | uint32_t retval = 0xFF; |
351 | ||
352 | switch (addr) { | |
353 | case 0x0092: | |
354 | /* Special port 92 */ | |
64201201 FB |
355 | retval = 0x00; |
356 | break; | |
357 | case 0x0800: | |
358 | /* Motorola CPU configuration register */ | |
359 | retval = 0xEF; /* MPC750 */ | |
360 | break; | |
361 | case 0x0802: | |
362 | /* Motorola Base module feature register */ | |
363 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
364 | break; | |
365 | case 0x0803: | |
366 | /* Motorola base module status register */ | |
367 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
368 | break; |
369 | case 0x080C: | |
370 | /* Equipment present register: | |
371 | * no L2 cache | |
372 | * no upgrade processor | |
373 | * no cards in PCI slots | |
374 | * SCSI fuse is bad | |
375 | */ | |
64201201 FB |
376 | retval = 0x3C; |
377 | break; | |
378 | case 0x0810: | |
379 | /* Motorola base module extended feature register */ | |
380 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 381 | break; |
da9b266b FB |
382 | case 0x0814: |
383 | /* L2 invalidate: don't care */ | |
384 | break; | |
9a64fbe4 FB |
385 | case 0x0818: |
386 | /* Keylock */ | |
387 | retval = 0x00; | |
388 | break; | |
389 | case 0x081C: | |
390 | /* system control register | |
391 | * 7 - 6 / 1 - 0: L2 cache enable | |
392 | */ | |
64201201 | 393 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
394 | break; |
395 | case 0x0823: | |
396 | /* */ | |
397 | retval = 0x03; /* no L2 cache */ | |
398 | break; | |
399 | case 0x0850: | |
400 | /* I/O map type register */ | |
da9b266b | 401 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
402 | break; |
403 | default: | |
64201201 | 404 | printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); |
9a64fbe4 FB |
405 | break; |
406 | } | |
64201201 | 407 | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); |
9a64fbe4 FB |
408 | |
409 | return retval; | |
410 | } | |
411 | ||
da9b266b FB |
412 | static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, |
413 | target_phys_addr_t addr) | |
414 | { | |
415 | if (sysctrl->contiguous_map == 0) { | |
416 | /* 64 KB contiguous space for IOs */ | |
417 | addr &= 0xFFFF; | |
418 | } else { | |
419 | /* 8 MB non-contiguous space for IOs */ | |
420 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
421 | } | |
422 | ||
423 | return addr; | |
424 | } | |
425 | ||
426 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, | |
427 | uint32_t value) | |
428 | { | |
429 | sysctrl_t *sysctrl = opaque; | |
430 | ||
431 | addr = prep_IO_address(sysctrl, addr); | |
432 | cpu_outb(NULL, addr, value); | |
433 | } | |
434 | ||
435 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) | |
436 | { | |
437 | sysctrl_t *sysctrl = opaque; | |
438 | uint32_t ret; | |
439 | ||
440 | addr = prep_IO_address(sysctrl, addr); | |
441 | ret = cpu_inb(NULL, addr); | |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
446 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, | |
447 | uint32_t value) | |
448 | { | |
449 | sysctrl_t *sysctrl = opaque; | |
450 | ||
451 | addr = prep_IO_address(sysctrl, addr); | |
452 | #ifdef TARGET_WORDS_BIGENDIAN | |
453 | value = bswap16(value); | |
454 | #endif | |
455 | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); | |
456 | cpu_outw(NULL, addr, value); | |
457 | } | |
458 | ||
459 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) | |
460 | { | |
461 | sysctrl_t *sysctrl = opaque; | |
462 | uint32_t ret; | |
463 | ||
464 | addr = prep_IO_address(sysctrl, addr); | |
465 | ret = cpu_inw(NULL, addr); | |
466 | #ifdef TARGET_WORDS_BIGENDIAN | |
467 | ret = bswap16(ret); | |
468 | #endif | |
469 | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); | |
470 | ||
471 | return ret; | |
472 | } | |
473 | ||
474 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, | |
475 | uint32_t value) | |
476 | { | |
477 | sysctrl_t *sysctrl = opaque; | |
478 | ||
479 | addr = prep_IO_address(sysctrl, addr); | |
480 | #ifdef TARGET_WORDS_BIGENDIAN | |
481 | value = bswap32(value); | |
482 | #endif | |
483 | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); | |
484 | cpu_outl(NULL, addr, value); | |
485 | } | |
486 | ||
487 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) | |
488 | { | |
489 | sysctrl_t *sysctrl = opaque; | |
490 | uint32_t ret; | |
491 | ||
492 | addr = prep_IO_address(sysctrl, addr); | |
493 | ret = cpu_inl(NULL, addr); | |
494 | #ifdef TARGET_WORDS_BIGENDIAN | |
495 | ret = bswap32(ret); | |
496 | #endif | |
497 | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); | |
498 | ||
499 | return ret; | |
500 | } | |
501 | ||
502 | CPUWriteMemoryFunc *PPC_prep_io_write[] = { | |
503 | &PPC_prep_io_writeb, | |
504 | &PPC_prep_io_writew, | |
505 | &PPC_prep_io_writel, | |
506 | }; | |
507 | ||
508 | CPUReadMemoryFunc *PPC_prep_io_read[] = { | |
509 | &PPC_prep_io_readb, | |
510 | &PPC_prep_io_readw, | |
511 | &PPC_prep_io_readl, | |
512 | }; | |
513 | ||
64201201 | 514 | #define NVRAM_SIZE 0x2000 |
a541f297 | 515 | |
26aa7d72 | 516 | /* PowerPC PREP hardware initialisation */ |
94fc95cd JM |
517 | static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device, |
518 | DisplayState *ds, const char **fd_filename, | |
519 | int snapshot, const char *kernel_filename, | |
520 | const char *kernel_cmdline, | |
521 | const char *initrd_filename, | |
522 | const char *cpu_model) | |
a541f297 | 523 | { |
c68ea704 | 524 | CPUState *env; |
a541f297 | 525 | char buf[1024]; |
64201201 | 526 | m48t59_t *nvram; |
a541f297 | 527 | int PPC_io_memory; |
4157a662 | 528 | int linux_boot, i, nb_nics1, bios_size; |
64201201 FB |
529 | unsigned long bios_offset; |
530 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; | |
3fc6c082 | 531 | ppc_def_t *def; |
46e50e9d | 532 | PCIBus *pci_bus; |
d537cf6c | 533 | qemu_irq *i8259; |
64201201 FB |
534 | |
535 | sysctrl = qemu_mallocz(sizeof(sysctrl_t)); | |
536 | if (sysctrl == NULL) | |
0a032cbe | 537 | return; |
a541f297 FB |
538 | |
539 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 540 | |
c68ea704 FB |
541 | /* init CPUs */ |
542 | ||
543 | env = cpu_init(); | |
0a032cbe | 544 | qemu_register_reset(&cpu_ppc_reset, env); |
c68ea704 | 545 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
94fc95cd | 546 | |
94fc95cd | 547 | if (cpu_model == NULL) |
d12f4c38 | 548 | cpu_model = "default"; |
94fc95cd | 549 | ppc_find_by_name(cpu_model, &def); |
c68ea704 FB |
550 | if (def == NULL) { |
551 | cpu_abort(env, "Unable to find PowerPC CPU definition\n"); | |
552 | } | |
553 | cpu_ppc_register(env, def); | |
554 | /* Set time-base frequency to 100 Mhz */ | |
555 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
a541f297 FB |
556 | |
557 | /* allocate RAM */ | |
64201201 FB |
558 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
559 | ||
560 | /* allocate and load BIOS */ | |
561 | bios_offset = ram_size + vga_ram_size; | |
562 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
4157a662 FB |
563 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
564 | if (bios_size < 0 || bios_size > BIOS_SIZE) { | |
4a057712 | 565 | cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf); |
64201201 FB |
566 | exit(1); |
567 | } | |
4157a662 | 568 | bios_size = (bios_size + 0xfff) & ~0xfff; |
4a057712 | 569 | cpu_register_physical_memory((uint32_t)(-bios_size), |
4157a662 | 570 | bios_size, bios_offset | IO_MEM_ROM); |
26aa7d72 | 571 | |
a541f297 | 572 | if (linux_boot) { |
64201201 | 573 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 574 | /* now we can load the kernel */ |
64201201 FB |
575 | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
576 | if (kernel_size < 0) { | |
4a057712 JM |
577 | cpu_abort(env, "qemu: could not load kernel '%s'\n", |
578 | kernel_filename); | |
a541f297 FB |
579 | exit(1); |
580 | } | |
581 | /* load initrd */ | |
a541f297 | 582 | if (initrd_filename) { |
64201201 FB |
583 | initrd_base = INITRD_LOAD_ADDR; |
584 | initrd_size = load_image(initrd_filename, | |
585 | phys_ram_base + initrd_base); | |
a541f297 | 586 | if (initrd_size < 0) { |
4a057712 JM |
587 | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n", |
588 | initrd_filename); | |
a541f297 FB |
589 | exit(1); |
590 | } | |
64201201 FB |
591 | } else { |
592 | initrd_base = 0; | |
593 | initrd_size = 0; | |
a541f297 | 594 | } |
64201201 | 595 | boot_device = 'm'; |
a541f297 | 596 | } else { |
64201201 FB |
597 | kernel_base = 0; |
598 | kernel_size = 0; | |
599 | initrd_base = 0; | |
600 | initrd_size = 0; | |
a541f297 FB |
601 | } |
602 | ||
64201201 | 603 | isa_mem_base = 0xc0000000; |
dd37a5e4 JM |
604 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
605 | cpu_abort(env, "Only 6xx bus is supported on PREP machine\n"); | |
606 | exit(1); | |
607 | } | |
24be5ae3 | 608 | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
d537cf6c | 609 | pci_bus = pci_prep_init(i8259); |
da9b266b FB |
610 | // pci_bus = i440fx_init(); |
611 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ | |
612 | PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read, | |
613 | PPC_prep_io_write, sysctrl); | |
614 | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); | |
64201201 | 615 | |
a541f297 | 616 | /* init basic PC hardware */ |
5fafdf24 | 617 | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
89b6b508 | 618 | vga_ram_size, 0, 0); |
64201201 | 619 | // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
d537cf6c PB |
620 | // pit = pit_init(0x40, i8259[0]); |
621 | rtc_init(0x70, i8259[8]); | |
a541f297 | 622 | |
d537cf6c | 623 | serial_init(0x3f8, i8259[4], serial_hds[0]); |
a541f297 FB |
624 | nb_nics1 = nb_nics; |
625 | if (nb_nics1 > NE2000_NB_MAX) | |
626 | nb_nics1 = NE2000_NB_MAX; | |
627 | for(i = 0; i < nb_nics1; i++) { | |
a41b2ff2 PB |
628 | if (nd_table[0].model == NULL |
629 | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | |
d537cf6c | 630 | isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
c4a7060c BS |
631 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
632 | fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n"); | |
633 | exit (1); | |
a41b2ff2 | 634 | } else { |
4a057712 JM |
635 | /* Why ? */ |
636 | cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
a41b2ff2 PB |
637 | exit (1); |
638 | } | |
a541f297 | 639 | } |
a541f297 FB |
640 | |
641 | for(i = 0; i < 2; i++) { | |
d537cf6c | 642 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
69b91039 | 643 | bs_table[2 * i], bs_table[2 * i + 1]); |
a541f297 | 644 | } |
d537cf6c | 645 | i8042_init(i8259[1], i8259[12], 0x60); |
b6b8bd18 | 646 | DMA_init(1); |
64201201 | 647 | // AUD_init(); |
a541f297 FB |
648 | // SB16_init(); |
649 | ||
d537cf6c | 650 | fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); |
a541f297 | 651 | |
64201201 FB |
652 | /* Register speaker port */ |
653 | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); | |
654 | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); | |
a541f297 | 655 | /* Register fake IO ports for PREP */ |
64201201 FB |
656 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
657 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); | |
a541f297 | 658 | /* System control ports */ |
64201201 FB |
659 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
660 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); | |
661 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); | |
662 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); | |
663 | /* PCI intack location */ | |
664 | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read, | |
a4193c8a | 665 | PPC_intack_write, NULL); |
a541f297 | 666 | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
64201201 | 667 | /* PowerPC control and status register group */ |
b6b8bd18 | 668 | #if 0 |
36081602 JM |
669 | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, |
670 | NULL); | |
64201201 | 671 | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
b6b8bd18 | 672 | #endif |
a541f297 | 673 | |
0d92ed30 | 674 | if (usb_enabled) { |
e24ad6f1 | 675 | usb_ohci_init_pci(pci_bus, 3, -1); |
0d92ed30 PB |
676 | } |
677 | ||
d537cf6c | 678 | nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
64201201 FB |
679 | if (nvram == NULL) |
680 | return; | |
681 | sysctrl->nvram = nvram; | |
682 | ||
683 | /* Initialise NVRAM */ | |
684 | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device, | |
685 | kernel_base, kernel_size, | |
b6b8bd18 | 686 | kernel_cmdline, |
64201201 FB |
687 | initrd_base, initrd_size, |
688 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
689 | 0, |
690 | graphic_width, graphic_height, graphic_depth); | |
c0e564d5 FB |
691 | |
692 | /* Special port to get debug messages from Open-Firmware */ | |
693 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
a541f297 | 694 | } |
c0e564d5 FB |
695 | |
696 | QEMUMachine prep_machine = { | |
697 | "prep", | |
698 | "PowerPC PREP platform", | |
699 | ppc_prep_init, | |
700 | }; |