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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
26 | #include "pc.h" | |
27 | #include "fdc.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "isa.h" | |
31 | #include "pci.h" | |
18e08a55 MT |
32 | #include "prep_pci.h" |
33 | #include "usb-ohci.h" | |
87ecb68b PB |
34 | #include "ppc.h" |
35 | #include "boards.h" | |
3b3fb322 | 36 | #include "qemu-log.h" |
ec82026c | 37 | #include "ide.h" |
ca20cf32 | 38 | #include "loader.h" |
1d914fa0 | 39 | #include "mc146818rtc.h" |
2446333c | 40 | #include "blockdev.h" |
9fddaa0c | 41 | |
9a64fbe4 | 42 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 43 | //#define DEBUG_PPC_IO |
9a64fbe4 | 44 | |
fe33cc71 JM |
45 | /* SMP is not enabled, for now */ |
46 | #define MAX_CPUS 1 | |
47 | ||
e4bcb14c TS |
48 | #define MAX_IDE_BUS 2 |
49 | ||
bba831e8 | 50 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
51 | #define BIOS_FILENAME "ppc_rom.bin" |
52 | #define KERNEL_LOAD_ADDR 0x01000000 | |
53 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 54 | |
9a64fbe4 FB |
55 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
56 | #define DEBUG_PPC_IO | |
57 | #endif | |
58 | ||
59 | #if defined (HARD_DEBUG_PPC_IO) | |
001faf32 | 60 | #define PPC_IO_DPRINTF(fmt, ...) \ |
9a64fbe4 | 61 | do { \ |
8fec2b8c | 62 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
001faf32 | 63 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 | 64 | } else { \ |
001faf32 | 65 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 FB |
66 | } \ |
67 | } while (0) | |
68 | #elif defined (DEBUG_PPC_IO) | |
0bf9e31a BS |
69 | #define PPC_IO_DPRINTF(fmt, ...) \ |
70 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) | |
9a64fbe4 | 71 | #else |
001faf32 | 72 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
9a64fbe4 FB |
73 | #endif |
74 | ||
64201201 | 75 | /* Constants for devices init */ |
a541f297 FB |
76 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
77 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
78 | static const int ide_irq[2] = { 13, 13 }; | |
79 | ||
80 | #define NE2000_NB_MAX 6 | |
81 | ||
82 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
83 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 84 | |
64201201 FB |
85 | //static PITState *pit; |
86 | ||
87 | /* ISA IO ports bridge */ | |
9a64fbe4 FB |
88 | #define PPC_IO_BASE 0x80000000 |
89 | ||
b1d8e52e | 90 | #if 0 |
64201201 | 91 | /* Speaker port 0x61 */ |
b1d8e52e BS |
92 | static int speaker_data_on; |
93 | static int dummy_refresh_clock; | |
94 | #endif | |
64201201 | 95 | |
36081602 | 96 | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 97 | { |
a541f297 | 98 | #if 0 |
64201201 FB |
99 | speaker_data_on = (val >> 1) & 1; |
100 | pit_set_gate(pit, 2, val & 1); | |
a541f297 | 101 | #endif |
9a64fbe4 FB |
102 | } |
103 | ||
47103572 | 104 | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
9a64fbe4 | 105 | { |
a541f297 | 106 | #if 0 |
64201201 FB |
107 | int out; |
108 | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); | |
109 | dummy_refresh_clock ^= 1; | |
110 | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | | |
47103572 | 111 | (dummy_refresh_clock << 4); |
a541f297 | 112 | #endif |
64201201 | 113 | return 0; |
9a64fbe4 FB |
114 | } |
115 | ||
64201201 FB |
116 | /* PCI intack register */ |
117 | /* Read-only register (?) */ | |
47103572 | 118 | static void _PPC_intack_write (void *opaque, |
c227f099 | 119 | target_phys_addr_t addr, uint32_t value) |
64201201 | 120 | { |
90e189ec BS |
121 | #if 0 |
122 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, | |
123 | value); | |
124 | #endif | |
64201201 FB |
125 | } |
126 | ||
c227f099 | 127 | static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
64201201 FB |
128 | { |
129 | uint32_t retval = 0; | |
130 | ||
4dd8c138 | 131 | if ((addr & 0xf) == 0) |
3de388f6 | 132 | retval = pic_intack_read(isa_pic); |
90e189ec BS |
133 | #if 0 |
134 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, | |
135 | retval); | |
136 | #endif | |
64201201 FB |
137 | |
138 | return retval; | |
139 | } | |
140 | ||
c227f099 | 141 | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
142 | { |
143 | return _PPC_intack_read(addr); | |
144 | } | |
145 | ||
c227f099 | 146 | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 147 | { |
f658b4db | 148 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
149 | return bswap16(_PPC_intack_read(addr)); |
150 | #else | |
151 | return _PPC_intack_read(addr); | |
f658b4db | 152 | #endif |
9a64fbe4 FB |
153 | } |
154 | ||
c227f099 | 155 | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 156 | { |
f658b4db | 157 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
158 | return bswap32(_PPC_intack_read(addr)); |
159 | #else | |
160 | return _PPC_intack_read(addr); | |
f658b4db | 161 | #endif |
9a64fbe4 FB |
162 | } |
163 | ||
d60efc6b | 164 | static CPUWriteMemoryFunc * const PPC_intack_write[] = { |
64201201 FB |
165 | &_PPC_intack_write, |
166 | &_PPC_intack_write, | |
167 | &_PPC_intack_write, | |
168 | }; | |
169 | ||
d60efc6b | 170 | static CPUReadMemoryFunc * const PPC_intack_read[] = { |
64201201 FB |
171 | &PPC_intack_readb, |
172 | &PPC_intack_readw, | |
173 | &PPC_intack_readl, | |
174 | }; | |
175 | ||
176 | /* PowerPC control and status registers */ | |
177 | #if 0 // Not used | |
178 | static struct { | |
179 | /* IDs */ | |
180 | uint32_t veni_devi; | |
181 | uint32_t revi; | |
182 | /* Control and status */ | |
183 | uint32_t gcsr; | |
184 | uint32_t xcfr; | |
185 | uint32_t ct32; | |
186 | uint32_t mcsr; | |
187 | /* General purpose registers */ | |
188 | uint32_t gprg[6]; | |
189 | /* Exceptions */ | |
190 | uint32_t feen; | |
191 | uint32_t fest; | |
192 | uint32_t fema; | |
193 | uint32_t fecl; | |
194 | uint32_t eeen; | |
195 | uint32_t eest; | |
196 | uint32_t eecl; | |
197 | uint32_t eeint; | |
198 | uint32_t eemck0; | |
199 | uint32_t eemck1; | |
200 | /* Error diagnostic */ | |
201 | } XCSR; | |
64201201 | 202 | |
36081602 | 203 | static void PPC_XCSR_writeb (void *opaque, |
c227f099 | 204 | target_phys_addr_t addr, uint32_t value) |
64201201 | 205 | { |
90e189ec BS |
206 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
207 | value); | |
64201201 FB |
208 | } |
209 | ||
36081602 | 210 | static void PPC_XCSR_writew (void *opaque, |
c227f099 | 211 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 212 | { |
f658b4db | 213 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 214 | value = bswap16(value); |
f658b4db | 215 | #endif |
90e189ec BS |
216 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
217 | value); | |
9a64fbe4 FB |
218 | } |
219 | ||
36081602 | 220 | static void PPC_XCSR_writel (void *opaque, |
c227f099 | 221 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 222 | { |
f658b4db | 223 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 224 | value = bswap32(value); |
f658b4db | 225 | #endif |
90e189ec BS |
226 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
227 | value); | |
9a64fbe4 FB |
228 | } |
229 | ||
c227f099 | 230 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
231 | { |
232 | uint32_t retval = 0; | |
9a64fbe4 | 233 | |
90e189ec BS |
234 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
235 | retval); | |
9a64fbe4 | 236 | |
64201201 FB |
237 | return retval; |
238 | } | |
239 | ||
c227f099 | 240 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 241 | { |
64201201 FB |
242 | uint32_t retval = 0; |
243 | ||
90e189ec BS |
244 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
245 | retval); | |
64201201 FB |
246 | #ifdef TARGET_WORDS_BIGENDIAN |
247 | retval = bswap16(retval); | |
248 | #endif | |
249 | ||
250 | return retval; | |
9a64fbe4 FB |
251 | } |
252 | ||
c227f099 | 253 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 FB |
254 | { |
255 | uint32_t retval = 0; | |
256 | ||
90e189ec BS |
257 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
258 | retval); | |
64201201 FB |
259 | #ifdef TARGET_WORDS_BIGENDIAN |
260 | retval = bswap32(retval); | |
261 | #endif | |
9a64fbe4 FB |
262 | |
263 | return retval; | |
264 | } | |
265 | ||
d60efc6b | 266 | static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { |
64201201 FB |
267 | &PPC_XCSR_writeb, |
268 | &PPC_XCSR_writew, | |
269 | &PPC_XCSR_writel, | |
9a64fbe4 FB |
270 | }; |
271 | ||
d60efc6b | 272 | static CPUReadMemoryFunc * const PPC_XCSR_read[] = { |
64201201 FB |
273 | &PPC_XCSR_readb, |
274 | &PPC_XCSR_readw, | |
275 | &PPC_XCSR_readl, | |
9a64fbe4 | 276 | }; |
b6b8bd18 | 277 | #endif |
9a64fbe4 | 278 | |
64201201 | 279 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 280 | typedef struct sysctrl_t { |
c4781a51 | 281 | qemu_irq reset_irq; |
43a34704 | 282 | M48t59State *nvram; |
64201201 FB |
283 | uint8_t state; |
284 | uint8_t syscontrol; | |
285 | uint8_t fake_io[2]; | |
da9b266b | 286 | int contiguous_map; |
fb3444b8 | 287 | int endian; |
c227f099 | 288 | } sysctrl_t; |
9a64fbe4 | 289 | |
64201201 FB |
290 | enum { |
291 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 292 | }; |
9a64fbe4 | 293 | |
c227f099 | 294 | static sysctrl_t *sysctrl; |
9a64fbe4 | 295 | |
a541f297 | 296 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 297 | { |
c227f099 | 298 | sysctrl_t *sysctrl = opaque; |
64201201 | 299 | |
aae9366a JM |
300 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
301 | val); | |
64201201 | 302 | sysctrl->fake_io[addr - 0x0398] = val; |
9a64fbe4 FB |
303 | } |
304 | ||
a541f297 | 305 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
9a64fbe4 | 306 | { |
c227f099 | 307 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 | 308 | |
aae9366a | 309 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
64201201 FB |
310 | sysctrl->fake_io[addr - 0x0398]); |
311 | return sysctrl->fake_io[addr - 0x0398]; | |
312 | } | |
9a64fbe4 | 313 | |
a541f297 | 314 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 315 | { |
c227f099 | 316 | sysctrl_t *sysctrl = opaque; |
64201201 | 317 | |
aae9366a JM |
318 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
319 | addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
320 | switch (addr) { |
321 | case 0x0092: | |
322 | /* Special port 92 */ | |
323 | /* Check soft reset asked */ | |
64201201 | 324 | if (val & 0x01) { |
c4781a51 JM |
325 | qemu_irq_raise(sysctrl->reset_irq); |
326 | } else { | |
327 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
328 | } |
329 | /* Check LE mode */ | |
64201201 | 330 | if (val & 0x02) { |
fb3444b8 FB |
331 | sysctrl->endian = 1; |
332 | } else { | |
333 | sysctrl->endian = 0; | |
9a64fbe4 FB |
334 | } |
335 | break; | |
64201201 FB |
336 | case 0x0800: |
337 | /* Motorola CPU configuration register : read-only */ | |
338 | break; | |
339 | case 0x0802: | |
340 | /* Motorola base module feature register : read-only */ | |
341 | break; | |
342 | case 0x0803: | |
343 | /* Motorola base module status register : read-only */ | |
344 | break; | |
9a64fbe4 | 345 | case 0x0808: |
64201201 FB |
346 | /* Hardfile light register */ |
347 | if (val & 1) | |
348 | sysctrl->state |= STATE_HARDFILE; | |
349 | else | |
350 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
351 | break; |
352 | case 0x0810: | |
353 | /* Password protect 1 register */ | |
64201201 FB |
354 | if (sysctrl->nvram != NULL) |
355 | m48t59_toggle_lock(sysctrl->nvram, 1); | |
9a64fbe4 FB |
356 | break; |
357 | case 0x0812: | |
358 | /* Password protect 2 register */ | |
64201201 FB |
359 | if (sysctrl->nvram != NULL) |
360 | m48t59_toggle_lock(sysctrl->nvram, 2); | |
9a64fbe4 FB |
361 | break; |
362 | case 0x0814: | |
64201201 | 363 | /* L2 invalidate register */ |
c68ea704 | 364 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
365 | break; |
366 | case 0x081C: | |
367 | /* system control register */ | |
64201201 | 368 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
369 | break; |
370 | case 0x0850: | |
371 | /* I/O map type register */ | |
da9b266b | 372 | sysctrl->contiguous_map = val & 0x01; |
9a64fbe4 FB |
373 | break; |
374 | default: | |
aae9366a JM |
375 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
376 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
377 | break; |
378 | } | |
379 | } | |
380 | ||
a541f297 | 381 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 382 | { |
c227f099 | 383 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
384 | uint32_t retval = 0xFF; |
385 | ||
386 | switch (addr) { | |
387 | case 0x0092: | |
388 | /* Special port 92 */ | |
64201201 FB |
389 | retval = 0x00; |
390 | break; | |
391 | case 0x0800: | |
392 | /* Motorola CPU configuration register */ | |
393 | retval = 0xEF; /* MPC750 */ | |
394 | break; | |
395 | case 0x0802: | |
396 | /* Motorola Base module feature register */ | |
397 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
398 | break; | |
399 | case 0x0803: | |
400 | /* Motorola base module status register */ | |
401 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
402 | break; |
403 | case 0x080C: | |
404 | /* Equipment present register: | |
405 | * no L2 cache | |
406 | * no upgrade processor | |
407 | * no cards in PCI slots | |
408 | * SCSI fuse is bad | |
409 | */ | |
64201201 FB |
410 | retval = 0x3C; |
411 | break; | |
412 | case 0x0810: | |
413 | /* Motorola base module extended feature register */ | |
414 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 415 | break; |
da9b266b FB |
416 | case 0x0814: |
417 | /* L2 invalidate: don't care */ | |
418 | break; | |
9a64fbe4 FB |
419 | case 0x0818: |
420 | /* Keylock */ | |
421 | retval = 0x00; | |
422 | break; | |
423 | case 0x081C: | |
424 | /* system control register | |
425 | * 7 - 6 / 1 - 0: L2 cache enable | |
426 | */ | |
64201201 | 427 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
428 | break; |
429 | case 0x0823: | |
430 | /* */ | |
431 | retval = 0x03; /* no L2 cache */ | |
432 | break; | |
433 | case 0x0850: | |
434 | /* I/O map type register */ | |
da9b266b | 435 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
436 | break; |
437 | default: | |
aae9366a | 438 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
439 | break; |
440 | } | |
aae9366a JM |
441 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
442 | addr - PPC_IO_BASE, retval); | |
9a64fbe4 FB |
443 | |
444 | return retval; | |
445 | } | |
446 | ||
c227f099 AL |
447 | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
448 | target_phys_addr_t addr) | |
da9b266b FB |
449 | { |
450 | if (sysctrl->contiguous_map == 0) { | |
451 | /* 64 KB contiguous space for IOs */ | |
452 | addr &= 0xFFFF; | |
453 | } else { | |
454 | /* 8 MB non-contiguous space for IOs */ | |
455 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
456 | } | |
457 | ||
458 | return addr; | |
459 | } | |
460 | ||
c227f099 | 461 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
462 | uint32_t value) |
463 | { | |
c227f099 | 464 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
465 | |
466 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 467 | cpu_outb(addr, value); |
da9b266b FB |
468 | } |
469 | ||
c227f099 | 470 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
da9b266b | 471 | { |
c227f099 | 472 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
473 | uint32_t ret; |
474 | ||
475 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 476 | ret = cpu_inb(addr); |
da9b266b FB |
477 | |
478 | return ret; | |
479 | } | |
480 | ||
c227f099 | 481 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
482 | uint32_t value) |
483 | { | |
c227f099 | 484 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
485 | |
486 | addr = prep_IO_address(sysctrl, addr); | |
487 | #ifdef TARGET_WORDS_BIGENDIAN | |
488 | value = bswap16(value); | |
489 | #endif | |
90e189ec | 490 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 491 | cpu_outw(addr, value); |
da9b266b FB |
492 | } |
493 | ||
c227f099 | 494 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
da9b266b | 495 | { |
c227f099 | 496 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
497 | uint32_t ret; |
498 | ||
499 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 500 | ret = cpu_inw(addr); |
da9b266b FB |
501 | #ifdef TARGET_WORDS_BIGENDIAN |
502 | ret = bswap16(ret); | |
503 | #endif | |
90e189ec | 504 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
505 | |
506 | return ret; | |
507 | } | |
508 | ||
c227f099 | 509 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
510 | uint32_t value) |
511 | { | |
c227f099 | 512 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
513 | |
514 | addr = prep_IO_address(sysctrl, addr); | |
515 | #ifdef TARGET_WORDS_BIGENDIAN | |
516 | value = bswap32(value); | |
517 | #endif | |
90e189ec | 518 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 519 | cpu_outl(addr, value); |
da9b266b FB |
520 | } |
521 | ||
c227f099 | 522 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
da9b266b | 523 | { |
c227f099 | 524 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
525 | uint32_t ret; |
526 | ||
527 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 528 | ret = cpu_inl(addr); |
da9b266b FB |
529 | #ifdef TARGET_WORDS_BIGENDIAN |
530 | ret = bswap32(ret); | |
531 | #endif | |
90e189ec | 532 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
533 | |
534 | return ret; | |
535 | } | |
536 | ||
d60efc6b | 537 | static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { |
da9b266b FB |
538 | &PPC_prep_io_writeb, |
539 | &PPC_prep_io_writew, | |
540 | &PPC_prep_io_writel, | |
541 | }; | |
542 | ||
d60efc6b | 543 | static CPUReadMemoryFunc * const PPC_prep_io_read[] = { |
da9b266b FB |
544 | &PPC_prep_io_readb, |
545 | &PPC_prep_io_readw, | |
546 | &PPC_prep_io_readl, | |
547 | }; | |
548 | ||
64201201 | 549 | #define NVRAM_SIZE 0x2000 |
a541f297 | 550 | |
4556bd8b BS |
551 | static void cpu_request_exit(void *opaque, int irq, int level) |
552 | { | |
553 | CPUState *env = cpu_single_env; | |
554 | ||
555 | if (env && level) { | |
556 | cpu_exit(env); | |
557 | } | |
558 | } | |
559 | ||
26aa7d72 | 560 | /* PowerPC PREP hardware initialisation */ |
c227f099 | 561 | static void ppc_prep_init (ram_addr_t ram_size, |
3023f332 | 562 | const char *boot_device, |
b881c2c6 | 563 | const char *kernel_filename, |
94fc95cd JM |
564 | const char *kernel_cmdline, |
565 | const char *initrd_filename, | |
566 | const char *cpu_model) | |
a541f297 | 567 | { |
49a2942d | 568 | CPUState *env = NULL; |
5cea8590 | 569 | char *filename; |
c227f099 | 570 | nvram_t nvram; |
43a34704 | 571 | M48t59State *m48t59; |
a541f297 | 572 | int PPC_io_memory; |
4157a662 | 573 | int linux_boot, i, nb_nics1, bios_size; |
c227f099 | 574 | ram_addr_t ram_offset, bios_offset; |
093209cd BS |
575 | uint32_t kernel_base, initrd_base; |
576 | long kernel_size, initrd_size; | |
46e50e9d | 577 | PCIBus *pci_bus; |
d537cf6c | 578 | qemu_irq *i8259; |
4556bd8b | 579 | qemu_irq *cpu_exit_irq; |
28c5af54 | 580 | int ppc_boot_device; |
f455e98c | 581 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 582 | DriveInfo *fd[MAX_FD]; |
64201201 | 583 | |
c227f099 | 584 | sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
a541f297 FB |
585 | |
586 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 587 | |
c68ea704 | 588 | /* init CPUs */ |
94fc95cd | 589 | if (cpu_model == NULL) |
b37fc148 | 590 | cpu_model = "602"; |
fe33cc71 | 591 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
592 | env = cpu_init(cpu_model); |
593 | if (!env) { | |
594 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
595 | exit(1); | |
596 | } | |
4018bae9 JM |
597 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
598 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
599 | cpu_ppc_tb_init(env, 7812500UL); | |
600 | } else { | |
601 | /* Set time-base frequency to 100 Mhz */ | |
602 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
603 | } | |
d84bda46 | 604 | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
fe33cc71 | 605 | } |
a541f297 FB |
606 | |
607 | /* allocate RAM */ | |
1724f049 | 608 | ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size); |
cf9c147c BS |
609 | cpu_register_physical_memory(0, ram_size, ram_offset); |
610 | ||
64201201 | 611 | /* allocate and load BIOS */ |
1724f049 | 612 | bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE); |
1192dad8 JM |
613 | if (bios_name == NULL) |
614 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
615 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
616 | if (filename) { | |
617 | bios_size = get_image_size(filename); | |
618 | } else { | |
619 | bios_size = -1; | |
620 | } | |
dcac9679 | 621 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
c227f099 | 622 | target_phys_addr_t bios_addr; |
dcac9679 PB |
623 | bios_size = (bios_size + 0xfff) & ~0xfff; |
624 | bios_addr = (uint32_t)(-bios_size); | |
625 | cpu_register_physical_memory(bios_addr, bios_size, | |
626 | bios_offset | IO_MEM_ROM); | |
5cea8590 | 627 | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
dcac9679 | 628 | } |
4157a662 | 629 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
630 | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); |
631 | } | |
632 | if (filename) { | |
633 | qemu_free(filename); | |
64201201 | 634 | } |
4c823cff | 635 | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
2ac71179 | 636 | hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); |
4c823cff | 637 | } |
26aa7d72 | 638 | |
a541f297 | 639 | if (linux_boot) { |
64201201 | 640 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 641 | /* now we can load the kernel */ |
dcac9679 PB |
642 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
643 | ram_size - kernel_base); | |
64201201 | 644 | if (kernel_size < 0) { |
2ac71179 | 645 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
a541f297 FB |
646 | exit(1); |
647 | } | |
648 | /* load initrd */ | |
a541f297 | 649 | if (initrd_filename) { |
64201201 | 650 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
651 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
652 | ram_size - initrd_base); | |
a541f297 | 653 | if (initrd_size < 0) { |
2ac71179 | 654 | hw_error("qemu: could not load initial ram disk '%s'\n", |
4a057712 | 655 | initrd_filename); |
a541f297 | 656 | } |
64201201 FB |
657 | } else { |
658 | initrd_base = 0; | |
659 | initrd_size = 0; | |
a541f297 | 660 | } |
6ac0e82d | 661 | ppc_boot_device = 'm'; |
a541f297 | 662 | } else { |
64201201 FB |
663 | kernel_base = 0; |
664 | kernel_size = 0; | |
665 | initrd_base = 0; | |
666 | initrd_size = 0; | |
28c5af54 JM |
667 | ppc_boot_device = '\0'; |
668 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
669 | for (i = 0; boot_device[i] != '\0'; i++) { |
670 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
671 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 672 | break; |
0d913fdb | 673 | } |
28c5af54 JM |
674 | } |
675 | if (ppc_boot_device == '\0') { | |
676 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
677 | exit(1); | |
678 | } | |
a541f297 FB |
679 | } |
680 | ||
64201201 | 681 | isa_mem_base = 0xc0000000; |
dd37a5e4 | 682 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
2ac71179 | 683 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
dd37a5e4 | 684 | } |
24be5ae3 | 685 | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
d537cf6c | 686 | pci_bus = pci_prep_init(i8259); |
b37fc148 GH |
687 | /* Hmm, prep has no pci-isa bridge ??? */ |
688 | isa_bus_new(NULL); | |
689 | isa_bus_irqs(i8259); | |
da9b266b FB |
690 | // pci_bus = i440fx_init(); |
691 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ | |
1eed09cb | 692 | PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
2507c12a AG |
693 | PPC_prep_io_write, sysctrl, |
694 | DEVICE_NATIVE_ENDIAN); | |
da9b266b | 695 | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
64201201 | 696 | |
a541f297 | 697 | /* init basic PC hardware */ |
78895427 | 698 | pci_vga_init(pci_bus); |
64201201 | 699 | // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
d537cf6c | 700 | // pit = pit_init(0x40, i8259[0]); |
7d932dfd | 701 | rtc_init(2000, NULL); |
a541f297 | 702 | |
ac0be998 GH |
703 | if (serial_hds[0]) |
704 | serial_isa_init(0, serial_hds[0]); | |
a541f297 FB |
705 | nb_nics1 = nb_nics; |
706 | if (nb_nics1 > NE2000_NB_MAX) | |
707 | nb_nics1 = NE2000_NB_MAX; | |
708 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 709 | if (nd_table[i].model == NULL) { |
9203f520 | 710 | nd_table[i].model = qemu_strdup("ne2k_isa"); |
5652ef78 AJ |
711 | } |
712 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
9453c5bc | 713 | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
a41b2ff2 | 714 | } else { |
07caea31 | 715 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
a41b2ff2 | 716 | } |
a541f297 | 717 | } |
a541f297 | 718 | |
e4bcb14c TS |
719 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
720 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
721 | exit(1); | |
722 | } | |
723 | ||
724 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 725 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
726 | } |
727 | ||
728 | for(i = 0; i < MAX_IDE_BUS; i++) { | |
dea21e97 | 729 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
730 | hd[2 * i], |
731 | hd[2 * i + 1]); | |
a541f297 | 732 | } |
11d23c35 | 733 | isa_create_simple("i8042"); |
4556bd8b BS |
734 | |
735 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); | |
736 | DMA_init(1, cpu_exit_irq); | |
737 | ||
a541f297 FB |
738 | // SB16_init(); |
739 | ||
e4bcb14c | 740 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 741 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 742 | } |
86c86157 | 743 | fdctrl_init_isa(fd); |
a541f297 | 744 | |
64201201 FB |
745 | /* Register speaker port */ |
746 | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); | |
747 | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); | |
a541f297 | 748 | /* Register fake IO ports for PREP */ |
c4781a51 | 749 | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
64201201 FB |
750 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
751 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); | |
a541f297 | 752 | /* System control ports */ |
64201201 FB |
753 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
754 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); | |
755 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); | |
756 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); | |
757 | /* PCI intack location */ | |
1eed09cb | 758 | PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
2507c12a AG |
759 | PPC_intack_write, NULL, |
760 | DEVICE_NATIVE_ENDIAN); | |
a541f297 | 761 | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
64201201 | 762 | /* PowerPC control and status register group */ |
b6b8bd18 | 763 | #if 0 |
1eed09cb | 764 | PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, |
2507c12a | 765 | NULL, DEVICE_NATIVE_ENDIAN); |
64201201 | 766 | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
b6b8bd18 | 767 | #endif |
a541f297 | 768 | |
0d92ed30 | 769 | if (usb_enabled) { |
a67ba3b6 | 770 | usb_ohci_init_pci(pci_bus, -1); |
0d92ed30 PB |
771 | } |
772 | ||
3cbee15b JM |
773 | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
774 | if (m48t59 == NULL) | |
64201201 | 775 | return; |
3cbee15b | 776 | sysctrl->nvram = m48t59; |
64201201 FB |
777 | |
778 | /* Initialise NVRAM */ | |
3cbee15b JM |
779 | nvram.opaque = m48t59; |
780 | nvram.read_fn = &m48t59_read; | |
781 | nvram.write_fn = &m48t59_write; | |
6ac0e82d | 782 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
64201201 | 783 | kernel_base, kernel_size, |
b6b8bd18 | 784 | kernel_cmdline, |
64201201 FB |
785 | initrd_base, initrd_size, |
786 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
787 | 0, |
788 | graphic_width, graphic_height, graphic_depth); | |
c0e564d5 FB |
789 | |
790 | /* Special port to get debug messages from Open-Firmware */ | |
791 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
a541f297 | 792 | } |
c0e564d5 | 793 | |
f80f9ec9 | 794 | static QEMUMachine prep_machine = { |
4b32e168 AL |
795 | .name = "prep", |
796 | .desc = "PowerPC PREP platform", | |
797 | .init = ppc_prep_init, | |
3d878caa | 798 | .max_cpus = MAX_CPUS, |
c0e564d5 | 799 | }; |
f80f9ec9 AL |
800 | |
801 | static void prep_machine_init(void) | |
802 | { | |
803 | qemu_register_machine(&prep_machine); | |
804 | } | |
805 | ||
806 | machine_init(prep_machine_init); |