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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
26 | #include "pc.h" | |
27 | #include "fdc.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "isa.h" | |
31 | #include "pci.h" | |
8ca8c7bc | 32 | #include "pci_host.h" |
87ecb68b PB |
33 | #include "ppc.h" |
34 | #include "boards.h" | |
3b3fb322 | 35 | #include "qemu-log.h" |
ec82026c | 36 | #include "ide.h" |
ca20cf32 | 37 | #include "loader.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
2446333c | 39 | #include "blockdev.h" |
1e39101c | 40 | #include "exec-memory.h" |
9fddaa0c | 41 | |
9a64fbe4 | 42 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 43 | //#define DEBUG_PPC_IO |
9a64fbe4 | 44 | |
fe33cc71 JM |
45 | /* SMP is not enabled, for now */ |
46 | #define MAX_CPUS 1 | |
47 | ||
e4bcb14c TS |
48 | #define MAX_IDE_BUS 2 |
49 | ||
bba831e8 | 50 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
51 | #define BIOS_FILENAME "ppc_rom.bin" |
52 | #define KERNEL_LOAD_ADDR 0x01000000 | |
53 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 54 | |
9a64fbe4 FB |
55 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
56 | #define DEBUG_PPC_IO | |
57 | #endif | |
58 | ||
59 | #if defined (HARD_DEBUG_PPC_IO) | |
001faf32 | 60 | #define PPC_IO_DPRINTF(fmt, ...) \ |
9a64fbe4 | 61 | do { \ |
8fec2b8c | 62 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
001faf32 | 63 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 | 64 | } else { \ |
001faf32 | 65 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 FB |
66 | } \ |
67 | } while (0) | |
68 | #elif defined (DEBUG_PPC_IO) | |
0bf9e31a BS |
69 | #define PPC_IO_DPRINTF(fmt, ...) \ |
70 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) | |
9a64fbe4 | 71 | #else |
001faf32 | 72 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
9a64fbe4 FB |
73 | #endif |
74 | ||
64201201 | 75 | /* Constants for devices init */ |
a541f297 FB |
76 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
77 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
78 | static const int ide_irq[2] = { 13, 13 }; | |
79 | ||
80 | #define NE2000_NB_MAX 6 | |
81 | ||
82 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
83 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 84 | |
64201201 | 85 | /* ISA IO ports bridge */ |
9a64fbe4 FB |
86 | #define PPC_IO_BASE 0x80000000 |
87 | ||
64201201 FB |
88 | /* PCI intack register */ |
89 | /* Read-only register (?) */ | |
0c90c52f AK |
90 | static void PPC_intack_write (void *opaque, target_phys_addr_t addr, |
91 | uint64_t value, unsigned size) | |
64201201 | 92 | { |
90e189ec | 93 | #if 0 |
0c90c52f | 94 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr, |
90e189ec BS |
95 | value); |
96 | #endif | |
64201201 FB |
97 | } |
98 | ||
0c90c52f AK |
99 | static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr, |
100 | unsigned size) | |
64201201 FB |
101 | { |
102 | uint32_t retval = 0; | |
103 | ||
4dd8c138 | 104 | if ((addr & 0xf) == 0) |
6e5580ca | 105 | retval = pic_read_irq(isa_pic); |
90e189ec BS |
106 | #if 0 |
107 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, | |
108 | retval); | |
109 | #endif | |
64201201 FB |
110 | |
111 | return retval; | |
112 | } | |
113 | ||
0c90c52f AK |
114 | static const MemoryRegionOps PPC_intack_ops = { |
115 | .read = PPC_intack_read, | |
116 | .write = PPC_intack_write, | |
117 | .endianness = DEVICE_LITTLE_ENDIAN, | |
64201201 FB |
118 | }; |
119 | ||
120 | /* PowerPC control and status registers */ | |
121 | #if 0 // Not used | |
122 | static struct { | |
123 | /* IDs */ | |
124 | uint32_t veni_devi; | |
125 | uint32_t revi; | |
126 | /* Control and status */ | |
127 | uint32_t gcsr; | |
128 | uint32_t xcfr; | |
129 | uint32_t ct32; | |
130 | uint32_t mcsr; | |
131 | /* General purpose registers */ | |
132 | uint32_t gprg[6]; | |
133 | /* Exceptions */ | |
134 | uint32_t feen; | |
135 | uint32_t fest; | |
136 | uint32_t fema; | |
137 | uint32_t fecl; | |
138 | uint32_t eeen; | |
139 | uint32_t eest; | |
140 | uint32_t eecl; | |
141 | uint32_t eeint; | |
142 | uint32_t eemck0; | |
143 | uint32_t eemck1; | |
144 | /* Error diagnostic */ | |
145 | } XCSR; | |
64201201 | 146 | |
36081602 | 147 | static void PPC_XCSR_writeb (void *opaque, |
c227f099 | 148 | target_phys_addr_t addr, uint32_t value) |
64201201 | 149 | { |
90e189ec BS |
150 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
151 | value); | |
64201201 FB |
152 | } |
153 | ||
36081602 | 154 | static void PPC_XCSR_writew (void *opaque, |
c227f099 | 155 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 156 | { |
90e189ec BS |
157 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
158 | value); | |
9a64fbe4 FB |
159 | } |
160 | ||
36081602 | 161 | static void PPC_XCSR_writel (void *opaque, |
c227f099 | 162 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 163 | { |
90e189ec BS |
164 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
165 | value); | |
9a64fbe4 FB |
166 | } |
167 | ||
c227f099 | 168 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
169 | { |
170 | uint32_t retval = 0; | |
9a64fbe4 | 171 | |
90e189ec BS |
172 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
173 | retval); | |
9a64fbe4 | 174 | |
64201201 FB |
175 | return retval; |
176 | } | |
177 | ||
c227f099 | 178 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 179 | { |
64201201 FB |
180 | uint32_t retval = 0; |
181 | ||
90e189ec BS |
182 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
183 | retval); | |
64201201 FB |
184 | |
185 | return retval; | |
9a64fbe4 FB |
186 | } |
187 | ||
c227f099 | 188 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 FB |
189 | { |
190 | uint32_t retval = 0; | |
191 | ||
90e189ec BS |
192 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
193 | retval); | |
9a64fbe4 FB |
194 | |
195 | return retval; | |
196 | } | |
197 | ||
0c90c52f AK |
198 | static const MemoryRegionOps PPC_XCSR_ops = { |
199 | .old_mmio = { | |
200 | .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, | |
201 | .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, | |
202 | }, | |
203 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9a64fbe4 FB |
204 | }; |
205 | ||
b6b8bd18 | 206 | #endif |
9a64fbe4 | 207 | |
64201201 | 208 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 209 | typedef struct sysctrl_t { |
c4781a51 | 210 | qemu_irq reset_irq; |
43a34704 | 211 | M48t59State *nvram; |
64201201 FB |
212 | uint8_t state; |
213 | uint8_t syscontrol; | |
214 | uint8_t fake_io[2]; | |
da9b266b | 215 | int contiguous_map; |
fb3444b8 | 216 | int endian; |
c227f099 | 217 | } sysctrl_t; |
9a64fbe4 | 218 | |
64201201 FB |
219 | enum { |
220 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 221 | }; |
9a64fbe4 | 222 | |
c227f099 | 223 | static sysctrl_t *sysctrl; |
9a64fbe4 | 224 | |
a541f297 | 225 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 226 | { |
c227f099 | 227 | sysctrl_t *sysctrl = opaque; |
64201201 | 228 | |
aae9366a JM |
229 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
230 | val); | |
64201201 | 231 | sysctrl->fake_io[addr - 0x0398] = val; |
9a64fbe4 FB |
232 | } |
233 | ||
a541f297 | 234 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
9a64fbe4 | 235 | { |
c227f099 | 236 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 | 237 | |
aae9366a | 238 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
64201201 FB |
239 | sysctrl->fake_io[addr - 0x0398]); |
240 | return sysctrl->fake_io[addr - 0x0398]; | |
241 | } | |
9a64fbe4 | 242 | |
a541f297 | 243 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 244 | { |
c227f099 | 245 | sysctrl_t *sysctrl = opaque; |
64201201 | 246 | |
aae9366a JM |
247 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
248 | addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
249 | switch (addr) { |
250 | case 0x0092: | |
251 | /* Special port 92 */ | |
252 | /* Check soft reset asked */ | |
64201201 | 253 | if (val & 0x01) { |
c4781a51 JM |
254 | qemu_irq_raise(sysctrl->reset_irq); |
255 | } else { | |
256 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
257 | } |
258 | /* Check LE mode */ | |
64201201 | 259 | if (val & 0x02) { |
fb3444b8 FB |
260 | sysctrl->endian = 1; |
261 | } else { | |
262 | sysctrl->endian = 0; | |
9a64fbe4 FB |
263 | } |
264 | break; | |
64201201 FB |
265 | case 0x0800: |
266 | /* Motorola CPU configuration register : read-only */ | |
267 | break; | |
268 | case 0x0802: | |
269 | /* Motorola base module feature register : read-only */ | |
270 | break; | |
271 | case 0x0803: | |
272 | /* Motorola base module status register : read-only */ | |
273 | break; | |
9a64fbe4 | 274 | case 0x0808: |
64201201 FB |
275 | /* Hardfile light register */ |
276 | if (val & 1) | |
277 | sysctrl->state |= STATE_HARDFILE; | |
278 | else | |
279 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
280 | break; |
281 | case 0x0810: | |
282 | /* Password protect 1 register */ | |
64201201 FB |
283 | if (sysctrl->nvram != NULL) |
284 | m48t59_toggle_lock(sysctrl->nvram, 1); | |
9a64fbe4 FB |
285 | break; |
286 | case 0x0812: | |
287 | /* Password protect 2 register */ | |
64201201 FB |
288 | if (sysctrl->nvram != NULL) |
289 | m48t59_toggle_lock(sysctrl->nvram, 2); | |
9a64fbe4 FB |
290 | break; |
291 | case 0x0814: | |
64201201 | 292 | /* L2 invalidate register */ |
c68ea704 | 293 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
294 | break; |
295 | case 0x081C: | |
296 | /* system control register */ | |
64201201 | 297 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
298 | break; |
299 | case 0x0850: | |
300 | /* I/O map type register */ | |
da9b266b | 301 | sysctrl->contiguous_map = val & 0x01; |
9a64fbe4 FB |
302 | break; |
303 | default: | |
aae9366a JM |
304 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
305 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
306 | break; |
307 | } | |
308 | } | |
309 | ||
a541f297 | 310 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 311 | { |
c227f099 | 312 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
313 | uint32_t retval = 0xFF; |
314 | ||
315 | switch (addr) { | |
316 | case 0x0092: | |
317 | /* Special port 92 */ | |
64201201 FB |
318 | retval = 0x00; |
319 | break; | |
320 | case 0x0800: | |
321 | /* Motorola CPU configuration register */ | |
322 | retval = 0xEF; /* MPC750 */ | |
323 | break; | |
324 | case 0x0802: | |
325 | /* Motorola Base module feature register */ | |
326 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
327 | break; | |
328 | case 0x0803: | |
329 | /* Motorola base module status register */ | |
330 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
331 | break; |
332 | case 0x080C: | |
333 | /* Equipment present register: | |
334 | * no L2 cache | |
335 | * no upgrade processor | |
336 | * no cards in PCI slots | |
337 | * SCSI fuse is bad | |
338 | */ | |
64201201 FB |
339 | retval = 0x3C; |
340 | break; | |
341 | case 0x0810: | |
342 | /* Motorola base module extended feature register */ | |
343 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 344 | break; |
da9b266b FB |
345 | case 0x0814: |
346 | /* L2 invalidate: don't care */ | |
347 | break; | |
9a64fbe4 FB |
348 | case 0x0818: |
349 | /* Keylock */ | |
350 | retval = 0x00; | |
351 | break; | |
352 | case 0x081C: | |
353 | /* system control register | |
354 | * 7 - 6 / 1 - 0: L2 cache enable | |
355 | */ | |
64201201 | 356 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
357 | break; |
358 | case 0x0823: | |
359 | /* */ | |
360 | retval = 0x03; /* no L2 cache */ | |
361 | break; | |
362 | case 0x0850: | |
363 | /* I/O map type register */ | |
da9b266b | 364 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
365 | break; |
366 | default: | |
aae9366a | 367 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
368 | break; |
369 | } | |
aae9366a JM |
370 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
371 | addr - PPC_IO_BASE, retval); | |
9a64fbe4 FB |
372 | |
373 | return retval; | |
374 | } | |
375 | ||
c227f099 AL |
376 | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
377 | target_phys_addr_t addr) | |
da9b266b FB |
378 | { |
379 | if (sysctrl->contiguous_map == 0) { | |
380 | /* 64 KB contiguous space for IOs */ | |
381 | addr &= 0xFFFF; | |
382 | } else { | |
383 | /* 8 MB non-contiguous space for IOs */ | |
384 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
385 | } | |
386 | ||
387 | return addr; | |
388 | } | |
389 | ||
c227f099 | 390 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
391 | uint32_t value) |
392 | { | |
c227f099 | 393 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
394 | |
395 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 396 | cpu_outb(addr, value); |
da9b266b FB |
397 | } |
398 | ||
c227f099 | 399 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
da9b266b | 400 | { |
c227f099 | 401 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
402 | uint32_t ret; |
403 | ||
404 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 405 | ret = cpu_inb(addr); |
da9b266b FB |
406 | |
407 | return ret; | |
408 | } | |
409 | ||
c227f099 | 410 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
411 | uint32_t value) |
412 | { | |
c227f099 | 413 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
414 | |
415 | addr = prep_IO_address(sysctrl, addr); | |
90e189ec | 416 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 417 | cpu_outw(addr, value); |
da9b266b FB |
418 | } |
419 | ||
c227f099 | 420 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
da9b266b | 421 | { |
c227f099 | 422 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
423 | uint32_t ret; |
424 | ||
425 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 426 | ret = cpu_inw(addr); |
90e189ec | 427 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
428 | |
429 | return ret; | |
430 | } | |
431 | ||
c227f099 | 432 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
433 | uint32_t value) |
434 | { | |
c227f099 | 435 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
436 | |
437 | addr = prep_IO_address(sysctrl, addr); | |
90e189ec | 438 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 439 | cpu_outl(addr, value); |
da9b266b FB |
440 | } |
441 | ||
c227f099 | 442 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
da9b266b | 443 | { |
c227f099 | 444 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
445 | uint32_t ret; |
446 | ||
447 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 448 | ret = cpu_inl(addr); |
90e189ec | 449 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
450 | |
451 | return ret; | |
452 | } | |
453 | ||
0c90c52f AK |
454 | static const MemoryRegionOps PPC_prep_io_ops = { |
455 | .old_mmio = { | |
456 | .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, | |
457 | .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, | |
458 | }, | |
459 | .endianness = DEVICE_LITTLE_ENDIAN, | |
da9b266b FB |
460 | }; |
461 | ||
64201201 | 462 | #define NVRAM_SIZE 0x2000 |
a541f297 | 463 | |
4556bd8b BS |
464 | static void cpu_request_exit(void *opaque, int irq, int level) |
465 | { | |
e2684c0b | 466 | CPUPPCState *env = cpu_single_env; |
4556bd8b BS |
467 | |
468 | if (env && level) { | |
469 | cpu_exit(env); | |
470 | } | |
471 | } | |
472 | ||
1bba0dc9 AF |
473 | static void ppc_prep_reset(void *opaque) |
474 | { | |
e2684c0b | 475 | CPUPPCState *env = opaque; |
1bba0dc9 AF |
476 | |
477 | cpu_state_reset(env); | |
478 | } | |
479 | ||
26aa7d72 | 480 | /* PowerPC PREP hardware initialisation */ |
c227f099 | 481 | static void ppc_prep_init (ram_addr_t ram_size, |
3023f332 | 482 | const char *boot_device, |
b881c2c6 | 483 | const char *kernel_filename, |
94fc95cd JM |
484 | const char *kernel_cmdline, |
485 | const char *initrd_filename, | |
486 | const char *cpu_model) | |
a541f297 | 487 | { |
0c90c52f | 488 | MemoryRegion *sysmem = get_system_memory(); |
e2684c0b | 489 | CPUPPCState *env = NULL; |
5cea8590 | 490 | char *filename; |
c227f099 | 491 | nvram_t nvram; |
43a34704 | 492 | M48t59State *m48t59; |
0c90c52f AK |
493 | MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); |
494 | MemoryRegion *intack = g_new(MemoryRegion, 1); | |
495 | #if 0 | |
496 | MemoryRegion *xcsr = g_new(MemoryRegion, 1); | |
497 | #endif | |
4157a662 | 498 | int linux_boot, i, nb_nics1, bios_size; |
0c90c52f AK |
499 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
500 | MemoryRegion *bios = g_new(MemoryRegion, 1); | |
093209cd BS |
501 | uint32_t kernel_base, initrd_base; |
502 | long kernel_size, initrd_size; | |
8ca8c7bc AF |
503 | DeviceState *dev; |
504 | SysBusDevice *sys; | |
505 | PCIHostState *pcihost; | |
46e50e9d | 506 | PCIBus *pci_bus; |
506b7ddf | 507 | PCIDevice *pci; |
48a18b3c | 508 | ISABus *isa_bus; |
4556bd8b | 509 | qemu_irq *cpu_exit_irq; |
28c5af54 | 510 | int ppc_boot_device; |
f455e98c | 511 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 512 | DriveInfo *fd[MAX_FD]; |
64201201 | 513 | |
7267c094 | 514 | sysctrl = g_malloc0(sizeof(sysctrl_t)); |
a541f297 FB |
515 | |
516 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 517 | |
c68ea704 | 518 | /* init CPUs */ |
94fc95cd | 519 | if (cpu_model == NULL) |
b37fc148 | 520 | cpu_model = "602"; |
fe33cc71 | 521 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
522 | env = cpu_init(cpu_model); |
523 | if (!env) { | |
524 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
525 | exit(1); | |
526 | } | |
4018bae9 JM |
527 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
528 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
529 | cpu_ppc_tb_init(env, 7812500UL); | |
530 | } else { | |
531 | /* Set time-base frequency to 100 Mhz */ | |
532 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
533 | } | |
1bba0dc9 | 534 | qemu_register_reset(ppc_prep_reset, env); |
fe33cc71 | 535 | } |
a541f297 FB |
536 | |
537 | /* allocate RAM */ | |
c5705a77 AK |
538 | memory_region_init_ram(ram, "ppc_prep.ram", ram_size); |
539 | vmstate_register_ram_global(ram); | |
0c90c52f | 540 | memory_region_add_subregion(sysmem, 0, ram); |
cf9c147c | 541 | |
64201201 | 542 | /* allocate and load BIOS */ |
c5705a77 | 543 | memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE); |
809680c0 AF |
544 | memory_region_set_readonly(bios, true); |
545 | memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); | |
c5705a77 | 546 | vmstate_register_ram_global(bios); |
1192dad8 JM |
547 | if (bios_name == NULL) |
548 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
549 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
550 | if (filename) { | |
551 | bios_size = get_image_size(filename); | |
552 | } else { | |
553 | bios_size = -1; | |
554 | } | |
dcac9679 | 555 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
c227f099 | 556 | target_phys_addr_t bios_addr; |
dcac9679 PB |
557 | bios_size = (bios_size + 0xfff) & ~0xfff; |
558 | bios_addr = (uint32_t)(-bios_size); | |
5cea8590 | 559 | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
dcac9679 | 560 | } |
4157a662 | 561 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
562 | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); |
563 | } | |
564 | if (filename) { | |
7267c094 | 565 | g_free(filename); |
64201201 | 566 | } |
26aa7d72 | 567 | |
a541f297 | 568 | if (linux_boot) { |
64201201 | 569 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 570 | /* now we can load the kernel */ |
dcac9679 PB |
571 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
572 | ram_size - kernel_base); | |
64201201 | 573 | if (kernel_size < 0) { |
2ac71179 | 574 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
a541f297 FB |
575 | exit(1); |
576 | } | |
577 | /* load initrd */ | |
a541f297 | 578 | if (initrd_filename) { |
64201201 | 579 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
580 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
581 | ram_size - initrd_base); | |
a541f297 | 582 | if (initrd_size < 0) { |
2ac71179 | 583 | hw_error("qemu: could not load initial ram disk '%s'\n", |
4a057712 | 584 | initrd_filename); |
a541f297 | 585 | } |
64201201 FB |
586 | } else { |
587 | initrd_base = 0; | |
588 | initrd_size = 0; | |
a541f297 | 589 | } |
6ac0e82d | 590 | ppc_boot_device = 'm'; |
a541f297 | 591 | } else { |
64201201 FB |
592 | kernel_base = 0; |
593 | kernel_size = 0; | |
594 | initrd_base = 0; | |
595 | initrd_size = 0; | |
28c5af54 JM |
596 | ppc_boot_device = '\0'; |
597 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
598 | for (i = 0; boot_device[i] != '\0'; i++) { |
599 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
600 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 601 | break; |
0d913fdb | 602 | } |
28c5af54 JM |
603 | } |
604 | if (ppc_boot_device == '\0') { | |
605 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
606 | exit(1); | |
607 | } | |
a541f297 FB |
608 | } |
609 | ||
dd37a5e4 | 610 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
2ac71179 | 611 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
dd37a5e4 | 612 | } |
8ca8c7bc AF |
613 | |
614 | dev = qdev_create(NULL, "raven-pcihost"); | |
615 | sys = sysbus_from_qdev(dev); | |
616 | pcihost = DO_UPCAST(PCIHostState, busdev, sys); | |
617 | pcihost->address_space = get_system_memory(); | |
618 | qdev_init_nofail(dev); | |
57c9fafe | 619 | object_property_add_child(object_get_root(), "raven", OBJECT(dev), NULL); |
8ca8c7bc AF |
620 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
621 | if (pci_bus == NULL) { | |
622 | fprintf(stderr, "Couldn't create PCI host controller.\n"); | |
623 | exit(1); | |
624 | } | |
8ca8c7bc | 625 | |
506b7ddf AF |
626 | /* PCI -> ISA bridge */ |
627 | pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); | |
628 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); | |
629 | qdev_connect_gpio_out(&pci->qdev, 0, | |
630 | first_cpu->irq_inputs[PPC6xx_INPUT_INT]); | |
631 | qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq); | |
632 | sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); | |
633 | sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); | |
634 | sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); | |
635 | sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); | |
636 | isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0")); | |
637 | ||
da9b266b | 638 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ |
0c90c52f AK |
639 | memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, |
640 | "ppc-io", 0x00800000); | |
641 | memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); | |
64201201 | 642 | |
a541f297 | 643 | /* init basic PC hardware */ |
78895427 | 644 | pci_vga_init(pci_bus); |
a541f297 | 645 | |
ac0be998 | 646 | if (serial_hds[0]) |
48a18b3c | 647 | serial_isa_init(isa_bus, 0, serial_hds[0]); |
a541f297 FB |
648 | nb_nics1 = nb_nics; |
649 | if (nb_nics1 > NE2000_NB_MAX) | |
650 | nb_nics1 = NE2000_NB_MAX; | |
651 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 652 | if (nd_table[i].model == NULL) { |
7267c094 | 653 | nd_table[i].model = g_strdup("ne2k_isa"); |
5652ef78 AJ |
654 | } |
655 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
48a18b3c HP |
656 | isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], |
657 | &nd_table[i]); | |
a41b2ff2 | 658 | } else { |
07caea31 | 659 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
a41b2ff2 | 660 | } |
a541f297 | 661 | } |
a541f297 | 662 | |
75717903 | 663 | ide_drive_get(hd, MAX_IDE_BUS); |
81aa0647 | 664 | for(i = 0; i < MAX_IDE_BUS; i++) { |
48a18b3c | 665 | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
666 | hd[2 * i], |
667 | hd[2 * i + 1]); | |
a541f297 | 668 | } |
48a18b3c | 669 | isa_create_simple(isa_bus, "i8042"); |
4556bd8b | 670 | |
a541f297 FB |
671 | // SB16_init(); |
672 | ||
e4bcb14c | 673 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 674 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 675 | } |
48a18b3c | 676 | fdctrl_init_isa(isa_bus, fd); |
a541f297 | 677 | |
a541f297 | 678 | /* Register fake IO ports for PREP */ |
c4781a51 | 679 | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
64201201 FB |
680 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
681 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); | |
a541f297 | 682 | /* System control ports */ |
64201201 FB |
683 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
684 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); | |
685 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); | |
686 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); | |
687 | /* PCI intack location */ | |
0c90c52f AK |
688 | memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4); |
689 | memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack); | |
64201201 | 690 | /* PowerPC control and status register group */ |
b6b8bd18 | 691 | #if 0 |
0c90c52f AK |
692 | memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); |
693 | memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); | |
b6b8bd18 | 694 | #endif |
a541f297 | 695 | |
0d92ed30 | 696 | if (usb_enabled) { |
afb9a60e | 697 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0d92ed30 PB |
698 | } |
699 | ||
48e93728 | 700 | m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
3cbee15b | 701 | if (m48t59 == NULL) |
64201201 | 702 | return; |
3cbee15b | 703 | sysctrl->nvram = m48t59; |
64201201 FB |
704 | |
705 | /* Initialise NVRAM */ | |
3cbee15b JM |
706 | nvram.opaque = m48t59; |
707 | nvram.read_fn = &m48t59_read; | |
708 | nvram.write_fn = &m48t59_write; | |
6ac0e82d | 709 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
64201201 | 710 | kernel_base, kernel_size, |
b6b8bd18 | 711 | kernel_cmdline, |
64201201 FB |
712 | initrd_base, initrd_size, |
713 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
714 | 0, |
715 | graphic_width, graphic_height, graphic_depth); | |
c0e564d5 FB |
716 | |
717 | /* Special port to get debug messages from Open-Firmware */ | |
718 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
a541f297 | 719 | } |
c0e564d5 | 720 | |
f80f9ec9 | 721 | static QEMUMachine prep_machine = { |
4b32e168 AL |
722 | .name = "prep", |
723 | .desc = "PowerPC PREP platform", | |
724 | .init = ppc_prep_init, | |
3d878caa | 725 | .max_cpus = MAX_CPUS, |
c0e564d5 | 726 | }; |
f80f9ec9 AL |
727 | |
728 | static void prep_machine_init(void) | |
729 | { | |
730 | qemu_register_machine(&prep_machine); | |
731 | } | |
732 | ||
733 | machine_init(prep_machine_init); |