]>
Commit | Line | Data |
---|---|---|
9a64fbe4 | 1 | /* |
a541f297 | 2 | * QEMU PPC PREP hardware System Emulator |
5fafdf24 | 3 | * |
47103572 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
9a64fbe4 | 23 | */ |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
26 | #include "pc.h" | |
27 | #include "fdc.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "isa.h" | |
31 | #include "pci.h" | |
18e08a55 MT |
32 | #include "prep_pci.h" |
33 | #include "usb-ohci.h" | |
87ecb68b PB |
34 | #include "ppc.h" |
35 | #include "boards.h" | |
3b3fb322 | 36 | #include "qemu-log.h" |
ec82026c | 37 | #include "ide.h" |
ca20cf32 | 38 | #include "loader.h" |
1d914fa0 | 39 | #include "mc146818rtc.h" |
9fddaa0c | 40 | |
9a64fbe4 | 41 | //#define HARD_DEBUG_PPC_IO |
a541f297 | 42 | //#define DEBUG_PPC_IO |
9a64fbe4 | 43 | |
fe33cc71 JM |
44 | /* SMP is not enabled, for now */ |
45 | #define MAX_CPUS 1 | |
46 | ||
e4bcb14c TS |
47 | #define MAX_IDE_BUS 2 |
48 | ||
bba831e8 | 49 | #define BIOS_SIZE (1024 * 1024) |
b6b8bd18 FB |
50 | #define BIOS_FILENAME "ppc_rom.bin" |
51 | #define KERNEL_LOAD_ADDR 0x01000000 | |
52 | #define INITRD_LOAD_ADDR 0x01800000 | |
64201201 | 53 | |
9a64fbe4 FB |
54 | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO) |
55 | #define DEBUG_PPC_IO | |
56 | #endif | |
57 | ||
58 | #if defined (HARD_DEBUG_PPC_IO) | |
001faf32 | 59 | #define PPC_IO_DPRINTF(fmt, ...) \ |
9a64fbe4 | 60 | do { \ |
8fec2b8c | 61 | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \ |
001faf32 | 62 | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 | 63 | } else { \ |
001faf32 | 64 | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
9a64fbe4 FB |
65 | } \ |
66 | } while (0) | |
67 | #elif defined (DEBUG_PPC_IO) | |
0bf9e31a BS |
68 | #define PPC_IO_DPRINTF(fmt, ...) \ |
69 | qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) | |
9a64fbe4 | 70 | #else |
001faf32 | 71 | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
9a64fbe4 FB |
72 | #endif |
73 | ||
64201201 | 74 | /* Constants for devices init */ |
a541f297 FB |
75 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
76 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
77 | static const int ide_irq[2] = { 13, 13 }; | |
78 | ||
79 | #define NE2000_NB_MAX 6 | |
80 | ||
81 | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; | |
82 | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; | |
9a64fbe4 | 83 | |
64201201 FB |
84 | //static PITState *pit; |
85 | ||
86 | /* ISA IO ports bridge */ | |
9a64fbe4 FB |
87 | #define PPC_IO_BASE 0x80000000 |
88 | ||
b1d8e52e | 89 | #if 0 |
64201201 | 90 | /* Speaker port 0x61 */ |
b1d8e52e BS |
91 | static int speaker_data_on; |
92 | static int dummy_refresh_clock; | |
93 | #endif | |
64201201 | 94 | |
36081602 | 95 | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 96 | { |
a541f297 | 97 | #if 0 |
64201201 FB |
98 | speaker_data_on = (val >> 1) & 1; |
99 | pit_set_gate(pit, 2, val & 1); | |
a541f297 | 100 | #endif |
9a64fbe4 FB |
101 | } |
102 | ||
47103572 | 103 | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
9a64fbe4 | 104 | { |
a541f297 | 105 | #if 0 |
64201201 FB |
106 | int out; |
107 | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock)); | |
108 | dummy_refresh_clock ^= 1; | |
109 | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) | | |
47103572 | 110 | (dummy_refresh_clock << 4); |
a541f297 | 111 | #endif |
64201201 | 112 | return 0; |
9a64fbe4 FB |
113 | } |
114 | ||
64201201 FB |
115 | /* PCI intack register */ |
116 | /* Read-only register (?) */ | |
47103572 | 117 | static void _PPC_intack_write (void *opaque, |
c227f099 | 118 | target_phys_addr_t addr, uint32_t value) |
64201201 | 119 | { |
90e189ec BS |
120 | #if 0 |
121 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, | |
122 | value); | |
123 | #endif | |
64201201 FB |
124 | } |
125 | ||
c227f099 | 126 | static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) |
64201201 FB |
127 | { |
128 | uint32_t retval = 0; | |
129 | ||
4dd8c138 | 130 | if ((addr & 0xf) == 0) |
3de388f6 | 131 | retval = pic_intack_read(isa_pic); |
90e189ec BS |
132 | #if 0 |
133 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, | |
134 | retval); | |
135 | #endif | |
64201201 FB |
136 | |
137 | return retval; | |
138 | } | |
139 | ||
c227f099 | 140 | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
141 | { |
142 | return _PPC_intack_read(addr); | |
143 | } | |
144 | ||
c227f099 | 145 | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 146 | { |
f658b4db | 147 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
148 | return bswap16(_PPC_intack_read(addr)); |
149 | #else | |
150 | return _PPC_intack_read(addr); | |
f658b4db | 151 | #endif |
9a64fbe4 FB |
152 | } |
153 | ||
c227f099 | 154 | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 155 | { |
f658b4db | 156 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 FB |
157 | return bswap32(_PPC_intack_read(addr)); |
158 | #else | |
159 | return _PPC_intack_read(addr); | |
f658b4db | 160 | #endif |
9a64fbe4 FB |
161 | } |
162 | ||
d60efc6b | 163 | static CPUWriteMemoryFunc * const PPC_intack_write[] = { |
64201201 FB |
164 | &_PPC_intack_write, |
165 | &_PPC_intack_write, | |
166 | &_PPC_intack_write, | |
167 | }; | |
168 | ||
d60efc6b | 169 | static CPUReadMemoryFunc * const PPC_intack_read[] = { |
64201201 FB |
170 | &PPC_intack_readb, |
171 | &PPC_intack_readw, | |
172 | &PPC_intack_readl, | |
173 | }; | |
174 | ||
175 | /* PowerPC control and status registers */ | |
176 | #if 0 // Not used | |
177 | static struct { | |
178 | /* IDs */ | |
179 | uint32_t veni_devi; | |
180 | uint32_t revi; | |
181 | /* Control and status */ | |
182 | uint32_t gcsr; | |
183 | uint32_t xcfr; | |
184 | uint32_t ct32; | |
185 | uint32_t mcsr; | |
186 | /* General purpose registers */ | |
187 | uint32_t gprg[6]; | |
188 | /* Exceptions */ | |
189 | uint32_t feen; | |
190 | uint32_t fest; | |
191 | uint32_t fema; | |
192 | uint32_t fecl; | |
193 | uint32_t eeen; | |
194 | uint32_t eest; | |
195 | uint32_t eecl; | |
196 | uint32_t eeint; | |
197 | uint32_t eemck0; | |
198 | uint32_t eemck1; | |
199 | /* Error diagnostic */ | |
200 | } XCSR; | |
64201201 | 201 | |
36081602 | 202 | static void PPC_XCSR_writeb (void *opaque, |
c227f099 | 203 | target_phys_addr_t addr, uint32_t value) |
64201201 | 204 | { |
90e189ec BS |
205 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
206 | value); | |
64201201 FB |
207 | } |
208 | ||
36081602 | 209 | static void PPC_XCSR_writew (void *opaque, |
c227f099 | 210 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 211 | { |
f658b4db | 212 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 213 | value = bswap16(value); |
f658b4db | 214 | #endif |
90e189ec BS |
215 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
216 | value); | |
9a64fbe4 FB |
217 | } |
218 | ||
36081602 | 219 | static void PPC_XCSR_writel (void *opaque, |
c227f099 | 220 | target_phys_addr_t addr, uint32_t value) |
9a64fbe4 | 221 | { |
f658b4db | 222 | #ifdef TARGET_WORDS_BIGENDIAN |
64201201 | 223 | value = bswap32(value); |
f658b4db | 224 | #endif |
90e189ec BS |
225 | printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, |
226 | value); | |
9a64fbe4 FB |
227 | } |
228 | ||
c227f099 | 229 | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
64201201 FB |
230 | { |
231 | uint32_t retval = 0; | |
9a64fbe4 | 232 | |
90e189ec BS |
233 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
234 | retval); | |
9a64fbe4 | 235 | |
64201201 FB |
236 | return retval; |
237 | } | |
238 | ||
c227f099 | 239 | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
9a64fbe4 | 240 | { |
64201201 FB |
241 | uint32_t retval = 0; |
242 | ||
90e189ec BS |
243 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
244 | retval); | |
64201201 FB |
245 | #ifdef TARGET_WORDS_BIGENDIAN |
246 | retval = bswap16(retval); | |
247 | #endif | |
248 | ||
249 | return retval; | |
9a64fbe4 FB |
250 | } |
251 | ||
c227f099 | 252 | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
9a64fbe4 FB |
253 | { |
254 | uint32_t retval = 0; | |
255 | ||
90e189ec BS |
256 | printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, |
257 | retval); | |
64201201 FB |
258 | #ifdef TARGET_WORDS_BIGENDIAN |
259 | retval = bswap32(retval); | |
260 | #endif | |
9a64fbe4 FB |
261 | |
262 | return retval; | |
263 | } | |
264 | ||
d60efc6b | 265 | static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { |
64201201 FB |
266 | &PPC_XCSR_writeb, |
267 | &PPC_XCSR_writew, | |
268 | &PPC_XCSR_writel, | |
9a64fbe4 FB |
269 | }; |
270 | ||
d60efc6b | 271 | static CPUReadMemoryFunc * const PPC_XCSR_read[] = { |
64201201 FB |
272 | &PPC_XCSR_readb, |
273 | &PPC_XCSR_readw, | |
274 | &PPC_XCSR_readl, | |
9a64fbe4 | 275 | }; |
b6b8bd18 | 276 | #endif |
9a64fbe4 | 277 | |
64201201 | 278 | /* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
c227f099 | 279 | typedef struct sysctrl_t { |
c4781a51 | 280 | qemu_irq reset_irq; |
43a34704 | 281 | M48t59State *nvram; |
64201201 FB |
282 | uint8_t state; |
283 | uint8_t syscontrol; | |
284 | uint8_t fake_io[2]; | |
da9b266b | 285 | int contiguous_map; |
fb3444b8 | 286 | int endian; |
c227f099 | 287 | } sysctrl_t; |
9a64fbe4 | 288 | |
64201201 FB |
289 | enum { |
290 | STATE_HARDFILE = 0x01, | |
9a64fbe4 | 291 | }; |
9a64fbe4 | 292 | |
c227f099 | 293 | static sysctrl_t *sysctrl; |
9a64fbe4 | 294 | |
a541f297 | 295 | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 296 | { |
c227f099 | 297 | sysctrl_t *sysctrl = opaque; |
64201201 | 298 | |
aae9366a JM |
299 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
300 | val); | |
64201201 | 301 | sysctrl->fake_io[addr - 0x0398] = val; |
9a64fbe4 FB |
302 | } |
303 | ||
a541f297 | 304 | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
9a64fbe4 | 305 | { |
c227f099 | 306 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 | 307 | |
aae9366a | 308 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
64201201 FB |
309 | sysctrl->fake_io[addr - 0x0398]); |
310 | return sysctrl->fake_io[addr - 0x0398]; | |
311 | } | |
9a64fbe4 | 312 | |
a541f297 | 313 | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
9a64fbe4 | 314 | { |
c227f099 | 315 | sysctrl_t *sysctrl = opaque; |
64201201 | 316 | |
aae9366a JM |
317 | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
318 | addr - PPC_IO_BASE, val); | |
9a64fbe4 FB |
319 | switch (addr) { |
320 | case 0x0092: | |
321 | /* Special port 92 */ | |
322 | /* Check soft reset asked */ | |
64201201 | 323 | if (val & 0x01) { |
c4781a51 JM |
324 | qemu_irq_raise(sysctrl->reset_irq); |
325 | } else { | |
326 | qemu_irq_lower(sysctrl->reset_irq); | |
9a64fbe4 FB |
327 | } |
328 | /* Check LE mode */ | |
64201201 | 329 | if (val & 0x02) { |
fb3444b8 FB |
330 | sysctrl->endian = 1; |
331 | } else { | |
332 | sysctrl->endian = 0; | |
9a64fbe4 FB |
333 | } |
334 | break; | |
64201201 FB |
335 | case 0x0800: |
336 | /* Motorola CPU configuration register : read-only */ | |
337 | break; | |
338 | case 0x0802: | |
339 | /* Motorola base module feature register : read-only */ | |
340 | break; | |
341 | case 0x0803: | |
342 | /* Motorola base module status register : read-only */ | |
343 | break; | |
9a64fbe4 | 344 | case 0x0808: |
64201201 FB |
345 | /* Hardfile light register */ |
346 | if (val & 1) | |
347 | sysctrl->state |= STATE_HARDFILE; | |
348 | else | |
349 | sysctrl->state &= ~STATE_HARDFILE; | |
9a64fbe4 FB |
350 | break; |
351 | case 0x0810: | |
352 | /* Password protect 1 register */ | |
64201201 FB |
353 | if (sysctrl->nvram != NULL) |
354 | m48t59_toggle_lock(sysctrl->nvram, 1); | |
9a64fbe4 FB |
355 | break; |
356 | case 0x0812: | |
357 | /* Password protect 2 register */ | |
64201201 FB |
358 | if (sysctrl->nvram != NULL) |
359 | m48t59_toggle_lock(sysctrl->nvram, 2); | |
9a64fbe4 FB |
360 | break; |
361 | case 0x0814: | |
64201201 | 362 | /* L2 invalidate register */ |
c68ea704 | 363 | // tlb_flush(first_cpu, 1); |
9a64fbe4 FB |
364 | break; |
365 | case 0x081C: | |
366 | /* system control register */ | |
64201201 | 367 | sysctrl->syscontrol = val & 0x0F; |
9a64fbe4 FB |
368 | break; |
369 | case 0x0850: | |
370 | /* I/O map type register */ | |
da9b266b | 371 | sysctrl->contiguous_map = val & 0x01; |
9a64fbe4 FB |
372 | break; |
373 | default: | |
aae9366a JM |
374 | printf("ERROR: unaffected IO port write: %04" PRIx32 |
375 | " => %02" PRIx32"\n", addr, val); | |
9a64fbe4 FB |
376 | break; |
377 | } | |
378 | } | |
379 | ||
a541f297 | 380 | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
9a64fbe4 | 381 | { |
c227f099 | 382 | sysctrl_t *sysctrl = opaque; |
9a64fbe4 FB |
383 | uint32_t retval = 0xFF; |
384 | ||
385 | switch (addr) { | |
386 | case 0x0092: | |
387 | /* Special port 92 */ | |
64201201 FB |
388 | retval = 0x00; |
389 | break; | |
390 | case 0x0800: | |
391 | /* Motorola CPU configuration register */ | |
392 | retval = 0xEF; /* MPC750 */ | |
393 | break; | |
394 | case 0x0802: | |
395 | /* Motorola Base module feature register */ | |
396 | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ | |
397 | break; | |
398 | case 0x0803: | |
399 | /* Motorola base module status register */ | |
400 | retval = 0xE0; /* Standard MPC750 */ | |
9a64fbe4 FB |
401 | break; |
402 | case 0x080C: | |
403 | /* Equipment present register: | |
404 | * no L2 cache | |
405 | * no upgrade processor | |
406 | * no cards in PCI slots | |
407 | * SCSI fuse is bad | |
408 | */ | |
64201201 FB |
409 | retval = 0x3C; |
410 | break; | |
411 | case 0x0810: | |
412 | /* Motorola base module extended feature register */ | |
413 | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ | |
9a64fbe4 | 414 | break; |
da9b266b FB |
415 | case 0x0814: |
416 | /* L2 invalidate: don't care */ | |
417 | break; | |
9a64fbe4 FB |
418 | case 0x0818: |
419 | /* Keylock */ | |
420 | retval = 0x00; | |
421 | break; | |
422 | case 0x081C: | |
423 | /* system control register | |
424 | * 7 - 6 / 1 - 0: L2 cache enable | |
425 | */ | |
64201201 | 426 | retval = sysctrl->syscontrol; |
9a64fbe4 FB |
427 | break; |
428 | case 0x0823: | |
429 | /* */ | |
430 | retval = 0x03; /* no L2 cache */ | |
431 | break; | |
432 | case 0x0850: | |
433 | /* I/O map type register */ | |
da9b266b | 434 | retval = sysctrl->contiguous_map; |
9a64fbe4 FB |
435 | break; |
436 | default: | |
aae9366a | 437 | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
9a64fbe4 FB |
438 | break; |
439 | } | |
aae9366a JM |
440 | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
441 | addr - PPC_IO_BASE, retval); | |
9a64fbe4 FB |
442 | |
443 | return retval; | |
444 | } | |
445 | ||
c227f099 AL |
446 | static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
447 | target_phys_addr_t addr) | |
da9b266b FB |
448 | { |
449 | if (sysctrl->contiguous_map == 0) { | |
450 | /* 64 KB contiguous space for IOs */ | |
451 | addr &= 0xFFFF; | |
452 | } else { | |
453 | /* 8 MB non-contiguous space for IOs */ | |
454 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); | |
455 | } | |
456 | ||
457 | return addr; | |
458 | } | |
459 | ||
c227f099 | 460 | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
461 | uint32_t value) |
462 | { | |
c227f099 | 463 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
464 | |
465 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 466 | cpu_outb(addr, value); |
da9b266b FB |
467 | } |
468 | ||
c227f099 | 469 | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
da9b266b | 470 | { |
c227f099 | 471 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
472 | uint32_t ret; |
473 | ||
474 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 475 | ret = cpu_inb(addr); |
da9b266b FB |
476 | |
477 | return ret; | |
478 | } | |
479 | ||
c227f099 | 480 | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
481 | uint32_t value) |
482 | { | |
c227f099 | 483 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
484 | |
485 | addr = prep_IO_address(sysctrl, addr); | |
486 | #ifdef TARGET_WORDS_BIGENDIAN | |
487 | value = bswap16(value); | |
488 | #endif | |
90e189ec | 489 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 490 | cpu_outw(addr, value); |
da9b266b FB |
491 | } |
492 | ||
c227f099 | 493 | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
da9b266b | 494 | { |
c227f099 | 495 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
496 | uint32_t ret; |
497 | ||
498 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 499 | ret = cpu_inw(addr); |
da9b266b FB |
500 | #ifdef TARGET_WORDS_BIGENDIAN |
501 | ret = bswap16(ret); | |
502 | #endif | |
90e189ec | 503 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
504 | |
505 | return ret; | |
506 | } | |
507 | ||
c227f099 | 508 | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
da9b266b FB |
509 | uint32_t value) |
510 | { | |
c227f099 | 511 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
512 | |
513 | addr = prep_IO_address(sysctrl, addr); | |
514 | #ifdef TARGET_WORDS_BIGENDIAN | |
515 | value = bswap32(value); | |
516 | #endif | |
90e189ec | 517 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
afcea8cb | 518 | cpu_outl(addr, value); |
da9b266b FB |
519 | } |
520 | ||
c227f099 | 521 | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
da9b266b | 522 | { |
c227f099 | 523 | sysctrl_t *sysctrl = opaque; |
da9b266b FB |
524 | uint32_t ret; |
525 | ||
526 | addr = prep_IO_address(sysctrl, addr); | |
afcea8cb | 527 | ret = cpu_inl(addr); |
da9b266b FB |
528 | #ifdef TARGET_WORDS_BIGENDIAN |
529 | ret = bswap32(ret); | |
530 | #endif | |
90e189ec | 531 | PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
da9b266b FB |
532 | |
533 | return ret; | |
534 | } | |
535 | ||
d60efc6b | 536 | static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { |
da9b266b FB |
537 | &PPC_prep_io_writeb, |
538 | &PPC_prep_io_writew, | |
539 | &PPC_prep_io_writel, | |
540 | }; | |
541 | ||
d60efc6b | 542 | static CPUReadMemoryFunc * const PPC_prep_io_read[] = { |
da9b266b FB |
543 | &PPC_prep_io_readb, |
544 | &PPC_prep_io_readw, | |
545 | &PPC_prep_io_readl, | |
546 | }; | |
547 | ||
64201201 | 548 | #define NVRAM_SIZE 0x2000 |
a541f297 | 549 | |
26aa7d72 | 550 | /* PowerPC PREP hardware initialisation */ |
c227f099 | 551 | static void ppc_prep_init (ram_addr_t ram_size, |
3023f332 | 552 | const char *boot_device, |
b881c2c6 | 553 | const char *kernel_filename, |
94fc95cd JM |
554 | const char *kernel_cmdline, |
555 | const char *initrd_filename, | |
556 | const char *cpu_model) | |
a541f297 | 557 | { |
0d913fdb | 558 | CPUState *env = NULL, *envs[MAX_CPUS]; |
5cea8590 | 559 | char *filename; |
c227f099 | 560 | nvram_t nvram; |
43a34704 | 561 | M48t59State *m48t59; |
a541f297 | 562 | int PPC_io_memory; |
4157a662 | 563 | int linux_boot, i, nb_nics1, bios_size; |
c227f099 | 564 | ram_addr_t ram_offset, bios_offset; |
64201201 | 565 | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
46e50e9d | 566 | PCIBus *pci_bus; |
d537cf6c | 567 | qemu_irq *i8259; |
28c5af54 | 568 | int ppc_boot_device; |
f455e98c | 569 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 570 | DriveInfo *fd[MAX_FD]; |
64201201 | 571 | |
c227f099 | 572 | sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
a541f297 FB |
573 | |
574 | linux_boot = (kernel_filename != NULL); | |
0a032cbe | 575 | |
c68ea704 | 576 | /* init CPUs */ |
94fc95cd | 577 | if (cpu_model == NULL) |
b37fc148 | 578 | cpu_model = "602"; |
fe33cc71 | 579 | for (i = 0; i < smp_cpus; i++) { |
aaed909a FB |
580 | env = cpu_init(cpu_model); |
581 | if (!env) { | |
582 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
583 | exit(1); | |
584 | } | |
4018bae9 JM |
585 | if (env->flags & POWERPC_FLAG_RTC_CLK) { |
586 | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ | |
587 | cpu_ppc_tb_init(env, 7812500UL); | |
588 | } else { | |
589 | /* Set time-base frequency to 100 Mhz */ | |
590 | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); | |
591 | } | |
d84bda46 | 592 | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
fe33cc71 JM |
593 | envs[i] = env; |
594 | } | |
a541f297 FB |
595 | |
596 | /* allocate RAM */ | |
cf9c147c BS |
597 | ram_offset = qemu_ram_alloc(ram_size); |
598 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
599 | ||
64201201 | 600 | /* allocate and load BIOS */ |
cf9c147c | 601 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
1192dad8 JM |
602 | if (bios_name == NULL) |
603 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
604 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
605 | if (filename) { | |
606 | bios_size = get_image_size(filename); | |
607 | } else { | |
608 | bios_size = -1; | |
609 | } | |
dcac9679 | 610 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
c227f099 | 611 | target_phys_addr_t bios_addr; |
dcac9679 PB |
612 | bios_size = (bios_size + 0xfff) & ~0xfff; |
613 | bios_addr = (uint32_t)(-bios_size); | |
614 | cpu_register_physical_memory(bios_addr, bios_size, | |
615 | bios_offset | IO_MEM_ROM); | |
5cea8590 | 616 | bios_size = load_image_targphys(filename, bios_addr, bios_size); |
dcac9679 | 617 | } |
4157a662 | 618 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
5cea8590 PB |
619 | hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name); |
620 | } | |
621 | if (filename) { | |
622 | qemu_free(filename); | |
64201201 | 623 | } |
4c823cff | 624 | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
2ac71179 | 625 | hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n"); |
4c823cff | 626 | } |
26aa7d72 | 627 | |
a541f297 | 628 | if (linux_boot) { |
64201201 | 629 | kernel_base = KERNEL_LOAD_ADDR; |
a541f297 | 630 | /* now we can load the kernel */ |
dcac9679 PB |
631 | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
632 | ram_size - kernel_base); | |
64201201 | 633 | if (kernel_size < 0) { |
2ac71179 | 634 | hw_error("qemu: could not load kernel '%s'\n", kernel_filename); |
a541f297 FB |
635 | exit(1); |
636 | } | |
637 | /* load initrd */ | |
a541f297 | 638 | if (initrd_filename) { |
64201201 | 639 | initrd_base = INITRD_LOAD_ADDR; |
dcac9679 PB |
640 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
641 | ram_size - initrd_base); | |
a541f297 | 642 | if (initrd_size < 0) { |
2ac71179 | 643 | hw_error("qemu: could not load initial ram disk '%s'\n", |
4a057712 | 644 | initrd_filename); |
a541f297 | 645 | } |
64201201 FB |
646 | } else { |
647 | initrd_base = 0; | |
648 | initrd_size = 0; | |
a541f297 | 649 | } |
6ac0e82d | 650 | ppc_boot_device = 'm'; |
a541f297 | 651 | } else { |
64201201 FB |
652 | kernel_base = 0; |
653 | kernel_size = 0; | |
654 | initrd_base = 0; | |
655 | initrd_size = 0; | |
28c5af54 JM |
656 | ppc_boot_device = '\0'; |
657 | /* For now, OHW cannot boot from the network. */ | |
0d913fdb JM |
658 | for (i = 0; boot_device[i] != '\0'; i++) { |
659 | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { | |
660 | ppc_boot_device = boot_device[i]; | |
28c5af54 | 661 | break; |
0d913fdb | 662 | } |
28c5af54 JM |
663 | } |
664 | if (ppc_boot_device == '\0') { | |
665 | fprintf(stderr, "No valid boot device for Mac99 machine\n"); | |
666 | exit(1); | |
667 | } | |
a541f297 FB |
668 | } |
669 | ||
64201201 | 670 | isa_mem_base = 0xc0000000; |
dd37a5e4 | 671 | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { |
2ac71179 | 672 | hw_error("Only 6xx bus is supported on PREP machine\n"); |
dd37a5e4 | 673 | } |
24be5ae3 | 674 | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
d537cf6c | 675 | pci_bus = pci_prep_init(i8259); |
b37fc148 GH |
676 | /* Hmm, prep has no pci-isa bridge ??? */ |
677 | isa_bus_new(NULL); | |
678 | isa_bus_irqs(i8259); | |
da9b266b FB |
679 | // pci_bus = i440fx_init(); |
680 | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ | |
1eed09cb | 681 | PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, |
da9b266b FB |
682 | PPC_prep_io_write, sysctrl); |
683 | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); | |
64201201 | 684 | |
a541f297 | 685 | /* init basic PC hardware */ |
fbe1b595 | 686 | pci_vga_init(pci_bus, 0, 0); |
64201201 | 687 | // openpic = openpic_init(0x00000000, 0xF0000000, 1); |
d537cf6c | 688 | // pit = pit_init(0x40, i8259[0]); |
32e0c826 | 689 | rtc_init(2000); |
a541f297 | 690 | |
ac0be998 GH |
691 | if (serial_hds[0]) |
692 | serial_isa_init(0, serial_hds[0]); | |
a541f297 FB |
693 | nb_nics1 = nb_nics; |
694 | if (nb_nics1 > NE2000_NB_MAX) | |
695 | nb_nics1 = NE2000_NB_MAX; | |
696 | for(i = 0; i < nb_nics1; i++) { | |
5652ef78 | 697 | if (nd_table[i].model == NULL) { |
9203f520 | 698 | nd_table[i].model = qemu_strdup("ne2k_isa"); |
5652ef78 AJ |
699 | } |
700 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { | |
9453c5bc | 701 | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
a41b2ff2 | 702 | } else { |
07caea31 | 703 | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
a41b2ff2 | 704 | } |
a541f297 | 705 | } |
a541f297 | 706 | |
e4bcb14c TS |
707 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
708 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
709 | exit(1); | |
710 | } | |
711 | ||
712 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 713 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
714 | } |
715 | ||
716 | for(i = 0; i < MAX_IDE_BUS; i++) { | |
dea21e97 | 717 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
718 | hd[2 * i], |
719 | hd[2 * i + 1]); | |
a541f297 | 720 | } |
11d23c35 | 721 | isa_create_simple("i8042"); |
b6b8bd18 | 722 | DMA_init(1); |
a541f297 FB |
723 | // SB16_init(); |
724 | ||
e4bcb14c | 725 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 726 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 727 | } |
86c86157 | 728 | fdctrl_init_isa(fd); |
a541f297 | 729 | |
64201201 FB |
730 | /* Register speaker port */ |
731 | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); | |
732 | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); | |
a541f297 | 733 | /* Register fake IO ports for PREP */ |
c4781a51 | 734 | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
64201201 FB |
735 | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
736 | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); | |
a541f297 | 737 | /* System control ports */ |
64201201 FB |
738 | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
739 | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); | |
740 | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); | |
741 | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); | |
742 | /* PCI intack location */ | |
1eed09cb | 743 | PPC_io_memory = cpu_register_io_memory(PPC_intack_read, |
a4193c8a | 744 | PPC_intack_write, NULL); |
a541f297 | 745 | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
64201201 | 746 | /* PowerPC control and status register group */ |
b6b8bd18 | 747 | #if 0 |
1eed09cb | 748 | PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, |
36081602 | 749 | NULL); |
64201201 | 750 | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); |
b6b8bd18 | 751 | #endif |
a541f297 | 752 | |
0d92ed30 | 753 | if (usb_enabled) { |
a67ba3b6 | 754 | usb_ohci_init_pci(pci_bus, -1); |
0d92ed30 PB |
755 | } |
756 | ||
3cbee15b JM |
757 | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
758 | if (m48t59 == NULL) | |
64201201 | 759 | return; |
3cbee15b | 760 | sysctrl->nvram = m48t59; |
64201201 FB |
761 | |
762 | /* Initialise NVRAM */ | |
3cbee15b JM |
763 | nvram.opaque = m48t59; |
764 | nvram.read_fn = &m48t59_read; | |
765 | nvram.write_fn = &m48t59_write; | |
6ac0e82d | 766 | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device, |
64201201 | 767 | kernel_base, kernel_size, |
b6b8bd18 | 768 | kernel_cmdline, |
64201201 FB |
769 | initrd_base, initrd_size, |
770 | /* XXX: need an option to load a NVRAM image */ | |
b6b8bd18 FB |
771 | 0, |
772 | graphic_width, graphic_height, graphic_depth); | |
c0e564d5 FB |
773 | |
774 | /* Special port to get debug messages from Open-Firmware */ | |
775 | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); | |
a541f297 | 776 | } |
c0e564d5 | 777 | |
f80f9ec9 | 778 | static QEMUMachine prep_machine = { |
4b32e168 AL |
779 | .name = "prep", |
780 | .desc = "PowerPC PREP platform", | |
781 | .init = ppc_prep_init, | |
3d878caa | 782 | .max_cpus = MAX_CPUS, |
c0e564d5 | 783 | }; |
f80f9ec9 AL |
784 | |
785 | static void prep_machine_init(void) | |
786 | { | |
787 | qemu_register_machine(&prep_machine); | |
788 | } | |
789 | ||
790 | machine_init(prep_machine_init); |