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1db09b84 AJ |
1 | /* |
2 | * Qemu PowerPC MPC8544DS board emualtion | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #include <dirent.h> | |
18 | ||
19 | #include "config.h" | |
20 | #include "qemu-common.h" | |
21 | #include "net.h" | |
22 | #include "hw.h" | |
23 | #include "pc.h" | |
24 | #include "pci.h" | |
1db09b84 AJ |
25 | #include "boards.h" |
26 | #include "sysemu.h" | |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "device_tree.h" | |
30 | #include "openpic.h" | |
31 | #include "ppce500.h" | |
ca20cf32 BS |
32 | #include "loader.h" |
33 | #include "elf.h" | |
1db09b84 AJ |
34 | |
35 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
36 | #define UIMAGE_LOAD_BASE 0 | |
37 | #define DTB_LOAD_BASE 0x600000 | |
38 | #define INITRD_LOAD_BASE 0x2000000 | |
39 | ||
40 | #define RAM_SIZES_ALIGN (64UL << 20) | |
41 | ||
42 | #define MPC8544_CCSRBAR_BASE 0xE0000000 | |
43 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) | |
44 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) | |
45 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) | |
46 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) | |
47 | #define MPC8544_PCI_REGS_SIZE 0x1000 | |
48 | #define MPC8544_PCI_IO 0xE1000000 | |
49 | #define MPC8544_PCI_IOLEN 0x10000 | |
50 | ||
3f0855b1 | 51 | #ifdef CONFIG_FDT |
1db09b84 AJ |
52 | static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop) |
53 | { | |
54 | uint32_t cell; | |
55 | int ret; | |
56 | ||
57 | ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell)); | |
58 | if (ret < 0) { | |
59 | fprintf(stderr, "couldn't read host %s/%s\n", node, prop); | |
60 | goto out; | |
61 | } | |
62 | ||
63 | ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0", | |
64 | prop, cell); | |
65 | if (ret < 0) { | |
66 | fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop); | |
67 | goto out; | |
68 | } | |
69 | ||
70 | out: | |
71 | return ret; | |
72 | } | |
511d2b14 | 73 | #endif |
1db09b84 | 74 | |
04088adb | 75 | static int mpc8544_load_device_tree(target_phys_addr_t addr, |
1db09b84 | 76 | uint32_t ramsize, |
c227f099 AL |
77 | target_phys_addr_t initrd_base, |
78 | target_phys_addr_t initrd_size, | |
1db09b84 AJ |
79 | const char *kernel_cmdline) |
80 | { | |
81 | void *fdt = NULL; | |
3f0855b1 | 82 | #ifdef CONFIG_FDT |
1db09b84 | 83 | uint32_t mem_reg_property[] = {0, ramsize}; |
5cea8590 | 84 | char *filename; |
7ec632b4 | 85 | int fdt_size; |
1db09b84 AJ |
86 | int ret; |
87 | ||
5cea8590 PB |
88 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
89 | if (!filename) { | |
04088adb | 90 | ret = -1; |
1db09b84 | 91 | goto out; |
5cea8590 PB |
92 | } |
93 | fdt = load_device_tree(filename, &fdt_size); | |
94 | qemu_free(filename); | |
95 | if (fdt == NULL) { | |
04088adb | 96 | ret = -1; |
5cea8590 PB |
97 | goto out; |
98 | } | |
1db09b84 AJ |
99 | |
100 | /* Manipulate device tree in memory. */ | |
101 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
102 | sizeof(mem_reg_property)); | |
103 | if (ret < 0) | |
104 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
105 | ||
106 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
107 | initrd_base); | |
108 | if (ret < 0) | |
109 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
110 | ||
111 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", | |
112 | (initrd_base + initrd_size)); | |
113 | if (ret < 0) | |
114 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
115 | ||
116 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
117 | kernel_cmdline); | |
118 | if (ret < 0) | |
119 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
120 | ||
121 | if (kvm_enabled()) { | |
122 | struct dirent *dirp; | |
123 | DIR *dp; | |
124 | char buf[128]; | |
125 | ||
126 | if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) { | |
127 | printf("Can't open directory /proc/device-tree/cpus/\n"); | |
04088adb | 128 | ret = -1; |
1db09b84 AJ |
129 | goto out; |
130 | } | |
131 | ||
132 | buf[0] = '\0'; | |
133 | while ((dirp = readdir(dp)) != NULL) { | |
134 | if (strncmp(dirp->d_name, "PowerPC", 7) == 0) { | |
135 | snprintf(buf, 128, "/cpus/%s", dirp->d_name); | |
136 | break; | |
137 | } | |
138 | } | |
139 | closedir(dp); | |
140 | if (buf[0] == '\0') { | |
141 | printf("Unknow host!\n"); | |
04088adb | 142 | ret = -1; |
1db09b84 AJ |
143 | goto out; |
144 | } | |
145 | ||
146 | mpc8544_copy_soc_cell(fdt, buf, "clock-frequency"); | |
147 | mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency"); | |
148 | } | |
149 | ||
04088adb LY |
150 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
151 | qemu_free(fdt); | |
7ec632b4 | 152 | |
1db09b84 AJ |
153 | out: |
154 | #endif | |
155 | ||
04088adb | 156 | return ret; |
1db09b84 AJ |
157 | } |
158 | ||
c227f099 | 159 | static void mpc8544ds_init(ram_addr_t ram_size, |
1db09b84 AJ |
160 | const char *boot_device, |
161 | const char *kernel_filename, | |
162 | const char *kernel_cmdline, | |
163 | const char *initrd_filename, | |
164 | const char *cpu_model) | |
165 | { | |
166 | PCIBus *pci_bus; | |
167 | CPUState *env; | |
168 | uint64_t elf_entry; | |
169 | uint64_t elf_lowaddr; | |
c227f099 AL |
170 | target_phys_addr_t entry=0; |
171 | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 AJ |
172 | target_long kernel_size=0; |
173 | target_ulong dt_base=DTB_LOAD_BASE; | |
174 | target_ulong initrd_base=INITRD_LOAD_BASE; | |
175 | target_long initrd_size=0; | |
1db09b84 AJ |
176 | int i=0; |
177 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; | |
178 | qemu_irq *irqs, *mpic, *pci_irqs; | |
179 | SerialState * serial[2]; | |
180 | ||
181 | /* Setup CPU */ | |
182 | env = cpu_ppc_init("e500v2_v30"); | |
183 | if (!env) { | |
184 | fprintf(stderr, "Unable to initialize CPU!\n"); | |
185 | exit(1); | |
186 | } | |
187 | ||
188 | /* Fixup Memory size on a alignment boundary */ | |
189 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
190 | ||
191 | /* Register Memory */ | |
d7585251 | 192 | cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size)); |
1db09b84 AJ |
193 | |
194 | /* MPIC */ | |
195 | irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); | |
196 | irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; | |
197 | irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; | |
198 | mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); | |
199 | ||
200 | /* Serial */ | |
201 | if (serial_hds[0]) | |
202 | serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE, | |
203 | 0, mpic[12+26], 399193, | |
204 | serial_hds[0], 1); | |
205 | ||
206 | if (serial_hds[1]) | |
207 | serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE, | |
208 | 0, mpic[12+26], 399193, | |
209 | serial_hds[0], 1); | |
210 | ||
211 | /* PCI */ | |
212 | pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4); | |
213 | pci_irqs[0] = mpic[pci_irq_nrs[0]]; | |
214 | pci_irqs[1] = mpic[pci_irq_nrs[1]]; | |
215 | pci_irqs[2] = mpic[pci_irq_nrs[2]]; | |
216 | pci_irqs[3] = mpic[pci_irq_nrs[3]]; | |
217 | pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE); | |
218 | if (!pci_bus) | |
219 | printf("couldn't create PCI controller!\n"); | |
220 | ||
221 | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); | |
222 | ||
223 | if (pci_bus) { | |
1db09b84 AJ |
224 | /* Register network interfaces. */ |
225 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 226 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
227 | } |
228 | } | |
229 | ||
230 | /* Load kernel. */ | |
231 | if (kernel_filename) { | |
232 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL); | |
233 | if (kernel_size < 0) { | |
234 | kernel_size = load_elf(kernel_filename, 0, &elf_entry, &elf_lowaddr, | |
ca20cf32 | 235 | NULL, 1, ELF_MACHINE, 0); |
1db09b84 AJ |
236 | entry = elf_entry; |
237 | loadaddr = elf_lowaddr; | |
238 | } | |
239 | /* XXX try again as binary */ | |
240 | if (kernel_size < 0) { | |
241 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
242 | kernel_filename); | |
243 | exit(1); | |
244 | } | |
245 | } | |
246 | ||
247 | /* Load initrd. */ | |
248 | if (initrd_filename) { | |
d7585251 PB |
249 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
250 | ram_size - initrd_base); | |
1db09b84 AJ |
251 | |
252 | if (initrd_size < 0) { | |
253 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
254 | initrd_filename); | |
255 | exit(1); | |
256 | } | |
257 | } | |
258 | ||
259 | /* If we're loading a kernel directly, we must load the device tree too. */ | |
260 | if (kernel_filename) { | |
04088adb LY |
261 | if (mpc8544_load_device_tree(dt_base, ram_size, |
262 | initrd_base, initrd_size, kernel_cmdline) < 0) { | |
1db09b84 AJ |
263 | fprintf(stderr, "couldn't load device tree\n"); |
264 | exit(1); | |
265 | } | |
266 | ||
c4963817 LY |
267 | cpu_synchronize_state(env); |
268 | ||
1db09b84 AJ |
269 | /* Set initial guest state. */ |
270 | env->gpr[1] = (16<<20) - 8; | |
271 | env->gpr[3] = dt_base; | |
272 | env->nip = entry; | |
273 | /* XXX we currently depend on KVM to create some initial TLB entries. */ | |
274 | } | |
275 | ||
276 | if (kvm_enabled()) | |
277 | kvmppc_init(); | |
278 | ||
279 | return; | |
280 | } | |
281 | ||
f80f9ec9 | 282 | static QEMUMachine mpc8544ds_machine = { |
1db09b84 AJ |
283 | .name = "mpc8544ds", |
284 | .desc = "mpc8544ds", | |
285 | .init = mpc8544ds_init, | |
1db09b84 | 286 | }; |
f80f9ec9 AL |
287 | |
288 | static void mpc8544ds_machine_init(void) | |
289 | { | |
290 | qemu_register_machine(&mpc8544ds_machine); | |
291 | } | |
292 | ||
293 | machine_init(mpc8544ds_machine_init); |