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Commit | Line | Data |
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1db09b84 AJ |
1 | /* |
2 | * Qemu PowerPC MPC8544DS board emualtion | |
3 | * | |
4 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: Yu Liu, <yu.liu@freescale.com> | |
7 | * | |
8 | * This file is derived from hw/ppc440_bamboo.c, | |
9 | * the copyright for that material belongs to the original owners. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #include <dirent.h> | |
18 | ||
19 | #include "config.h" | |
20 | #include "qemu-common.h" | |
21 | #include "net.h" | |
22 | #include "hw.h" | |
23 | #include "pc.h" | |
24 | #include "pci.h" | |
1db09b84 AJ |
25 | #include "boards.h" |
26 | #include "sysemu.h" | |
27 | #include "kvm.h" | |
28 | #include "kvm_ppc.h" | |
29 | #include "device_tree.h" | |
30 | #include "openpic.h" | |
3b989d49 | 31 | #include "ppc.h" |
ca20cf32 BS |
32 | #include "loader.h" |
33 | #include "elf.h" | |
be13cc7a | 34 | #include "sysbus.h" |
39186d8a | 35 | #include "exec-memory.h" |
1db09b84 AJ |
36 | |
37 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" | |
38 | #define UIMAGE_LOAD_BASE 0 | |
75bb6589 LY |
39 | #define DTC_LOAD_PAD 0x500000 |
40 | #define DTC_PAD_MASK 0xFFFFF | |
41 | #define INITRD_LOAD_PAD 0x2000000 | |
42 | #define INITRD_PAD_MASK 0xFFFFFF | |
1db09b84 AJ |
43 | |
44 | #define RAM_SIZES_ALIGN (64UL << 20) | |
45 | ||
46 | #define MPC8544_CCSRBAR_BASE 0xE0000000 | |
47 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) | |
48 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) | |
49 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) | |
50 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) | |
51 | #define MPC8544_PCI_REGS_SIZE 0x1000 | |
52 | #define MPC8544_PCI_IO 0xE1000000 | |
53 | #define MPC8544_PCI_IOLEN 0x10000 | |
b0fb8423 | 54 | #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000) |
1db09b84 | 55 | |
3b989d49 AG |
56 | struct boot_info |
57 | { | |
58 | uint32_t dt_base; | |
59 | uint32_t entry; | |
60 | }; | |
61 | ||
3f0855b1 | 62 | #ifdef CONFIG_FDT |
1db09b84 AJ |
63 | static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop) |
64 | { | |
65 | uint32_t cell; | |
66 | int ret; | |
67 | ||
68 | ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell)); | |
69 | if (ret < 0) { | |
70 | fprintf(stderr, "couldn't read host %s/%s\n", node, prop); | |
71 | goto out; | |
72 | } | |
73 | ||
74 | ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0", | |
75 | prop, cell); | |
76 | if (ret < 0) { | |
77 | fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop); | |
78 | goto out; | |
79 | } | |
80 | ||
81 | out: | |
82 | return ret; | |
83 | } | |
511d2b14 | 84 | #endif |
1db09b84 | 85 | |
5de6b46d AG |
86 | static int mpc8544_load_device_tree(CPUState *env, |
87 | target_phys_addr_t addr, | |
88 | uint32_t ramsize, | |
89 | target_phys_addr_t initrd_base, | |
90 | target_phys_addr_t initrd_size, | |
91 | const char *kernel_cmdline) | |
1db09b84 | 92 | { |
dbf916d8 | 93 | int ret = -1; |
3f0855b1 | 94 | #ifdef CONFIG_FDT |
3b989d49 | 95 | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)}; |
5cea8590 | 96 | char *filename; |
7ec632b4 | 97 | int fdt_size; |
dbf916d8 | 98 | void *fdt; |
5de6b46d | 99 | uint8_t hypercall[16]; |
1db09b84 | 100 | |
5cea8590 PB |
101 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
102 | if (!filename) { | |
1db09b84 | 103 | goto out; |
5cea8590 PB |
104 | } |
105 | fdt = load_device_tree(filename, &fdt_size); | |
7267c094 | 106 | g_free(filename); |
5cea8590 PB |
107 | if (fdt == NULL) { |
108 | goto out; | |
109 | } | |
1db09b84 AJ |
110 | |
111 | /* Manipulate device tree in memory. */ | |
112 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, | |
113 | sizeof(mem_reg_property)); | |
114 | if (ret < 0) | |
115 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
116 | ||
3b989d49 AG |
117 | if (initrd_size) { |
118 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
119 | initrd_base); | |
120 | if (ret < 0) { | |
121 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
122 | } | |
1db09b84 | 123 | |
3b989d49 AG |
124 | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
125 | (initrd_base + initrd_size)); | |
126 | if (ret < 0) { | |
127 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
128 | } | |
129 | } | |
1db09b84 AJ |
130 | |
131 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
132 | kernel_cmdline); | |
133 | if (ret < 0) | |
134 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
135 | ||
136 | if (kvm_enabled()) { | |
137 | struct dirent *dirp; | |
138 | DIR *dp; | |
139 | char buf[128]; | |
140 | ||
141 | if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) { | |
142 | printf("Can't open directory /proc/device-tree/cpus/\n"); | |
04088adb | 143 | ret = -1; |
1db09b84 AJ |
144 | goto out; |
145 | } | |
146 | ||
147 | buf[0] = '\0'; | |
148 | while ((dirp = readdir(dp)) != NULL) { | |
149 | if (strncmp(dirp->d_name, "PowerPC", 7) == 0) { | |
150 | snprintf(buf, 128, "/cpus/%s", dirp->d_name); | |
151 | break; | |
152 | } | |
153 | } | |
154 | closedir(dp); | |
155 | if (buf[0] == '\0') { | |
156 | printf("Unknow host!\n"); | |
04088adb | 157 | ret = -1; |
1db09b84 AJ |
158 | goto out; |
159 | } | |
160 | ||
161 | mpc8544_copy_soc_cell(fdt, buf, "clock-frequency"); | |
162 | mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency"); | |
5de6b46d AG |
163 | |
164 | /* indicate KVM hypercall interface */ | |
165 | qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", | |
166 | "linux,kvm"); | |
167 | kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); | |
168 | qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", | |
169 | hypercall, sizeof(hypercall)); | |
3b989d49 AG |
170 | } else { |
171 | const uint32_t freq = 400000000; | |
172 | ||
173 | qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0", | |
174 | "clock-frequency", freq); | |
175 | qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0", | |
176 | "timebase-frequency", freq); | |
1db09b84 AJ |
177 | } |
178 | ||
04088adb | 179 | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
7267c094 | 180 | g_free(fdt); |
7ec632b4 | 181 | |
1db09b84 AJ |
182 | out: |
183 | #endif | |
184 | ||
04088adb | 185 | return ret; |
1db09b84 AJ |
186 | } |
187 | ||
3b989d49 | 188 | /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */ |
d1e256fe AG |
189 | static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) |
190 | { | |
191 | return (ffs(size >> 10) - 1) >> 1; | |
192 | } | |
193 | ||
3b989d49 AG |
194 | static void mmubooke_create_initial_mapping(CPUState *env, |
195 | target_ulong va, | |
196 | target_phys_addr_t pa) | |
197 | { | |
d1e256fe AG |
198 | ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); |
199 | target_phys_addr_t size; | |
200 | ||
201 | size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT); | |
202 | tlb->mas1 = MAS1_VALID | size; | |
203 | tlb->mas2 = va & TARGET_PAGE_MASK; | |
204 | tlb->mas7_3 = pa & TARGET_PAGE_MASK; | |
205 | tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; | |
3b989d49 AG |
206 | } |
207 | ||
208 | static void mpc8544ds_cpu_reset(void *opaque) | |
209 | { | |
210 | CPUState *env = opaque; | |
211 | struct boot_info *bi = env->load_info; | |
212 | ||
213 | cpu_reset(env); | |
214 | ||
215 | /* Set initial guest state. */ | |
216 | env->gpr[1] = (16<<20) - 8; | |
217 | env->gpr[3] = bi->dt_base; | |
218 | env->nip = bi->entry; | |
219 | mmubooke_create_initial_mapping(env, 0, 0); | |
220 | } | |
221 | ||
c227f099 | 222 | static void mpc8544ds_init(ram_addr_t ram_size, |
1db09b84 AJ |
223 | const char *boot_device, |
224 | const char *kernel_filename, | |
225 | const char *kernel_cmdline, | |
226 | const char *initrd_filename, | |
227 | const char *cpu_model) | |
228 | { | |
39186d8a | 229 | MemoryRegion *address_space_mem = get_system_memory(); |
1db09b84 AJ |
230 | PCIBus *pci_bus; |
231 | CPUState *env; | |
232 | uint64_t elf_entry; | |
233 | uint64_t elf_lowaddr; | |
c227f099 AL |
234 | target_phys_addr_t entry=0; |
235 | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; | |
1db09b84 | 236 | target_long kernel_size=0; |
75bb6589 LY |
237 | target_ulong dt_base = 0; |
238 | target_ulong initrd_base = 0; | |
1db09b84 | 239 | target_long initrd_size=0; |
1db09b84 AJ |
240 | int i=0; |
241 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; | |
be13cc7a AG |
242 | qemu_irq *irqs, *mpic; |
243 | DeviceState *dev; | |
3b989d49 | 244 | struct boot_info *boot_info; |
1db09b84 AJ |
245 | |
246 | /* Setup CPU */ | |
ef250db6 AG |
247 | if (cpu_model == NULL) { |
248 | cpu_model = "e500v2_v30"; | |
249 | } | |
250 | ||
251 | env = cpu_ppc_init(cpu_model); | |
1db09b84 AJ |
252 | if (!env) { |
253 | fprintf(stderr, "Unable to initialize CPU!\n"); | |
254 | exit(1); | |
255 | } | |
256 | ||
3b989d49 AG |
257 | /* XXX register timer? */ |
258 | ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR); | |
259 | ppc_dcr_init(env, NULL, NULL); | |
260 | ||
261 | /* Register reset handler */ | |
262 | qemu_register_reset(mpc8544ds_cpu_reset, env); | |
263 | ||
1db09b84 AJ |
264 | /* Fixup Memory size on a alignment boundary */ |
265 | ram_size &= ~(RAM_SIZES_ALIGN - 1); | |
266 | ||
267 | /* Register Memory */ | |
1724f049 AW |
268 | cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL, |
269 | "mpc8544ds.ram", ram_size)); | |
1db09b84 AJ |
270 | |
271 | /* MPIC */ | |
7267c094 | 272 | irqs = g_malloc0(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
1db09b84 AJ |
273 | irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; |
274 | irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; | |
71cf9e62 | 275 | mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); |
1db09b84 AJ |
276 | |
277 | /* Serial */ | |
2d48377a | 278 | if (serial_hds[0]) { |
39186d8a | 279 | serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, |
49a2942d | 280 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 281 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 282 | } |
1db09b84 | 283 | |
2d48377a | 284 | if (serial_hds[1]) { |
39186d8a | 285 | serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, |
49a2942d | 286 | 0, mpic[12+26], 399193, |
2ff0c7c3 | 287 | serial_hds[0], DEVICE_BIG_ENDIAN); |
2d48377a | 288 | } |
1db09b84 | 289 | |
b0fb8423 AG |
290 | /* General Utility device */ |
291 | sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); | |
292 | ||
1db09b84 | 293 | /* PCI */ |
be13cc7a AG |
294 | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, |
295 | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], | |
296 | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], | |
297 | NULL); | |
d461e3b9 | 298 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); |
1db09b84 AJ |
299 | if (!pci_bus) |
300 | printf("couldn't create PCI controller!\n"); | |
301 | ||
968d683c | 302 | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
1db09b84 AJ |
303 | |
304 | if (pci_bus) { | |
1db09b84 AJ |
305 | /* Register network interfaces. */ |
306 | for (i = 0; i < nb_nics; i++) { | |
07caea31 | 307 | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
1db09b84 AJ |
308 | } |
309 | } | |
310 | ||
311 | /* Load kernel. */ | |
312 | if (kernel_filename) { | |
313 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL); | |
314 | if (kernel_size < 0) { | |
409dbce5 AJ |
315 | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
316 | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); | |
1db09b84 AJ |
317 | entry = elf_entry; |
318 | loadaddr = elf_lowaddr; | |
319 | } | |
320 | /* XXX try again as binary */ | |
321 | if (kernel_size < 0) { | |
322 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
323 | kernel_filename); | |
324 | exit(1); | |
325 | } | |
326 | } | |
327 | ||
328 | /* Load initrd. */ | |
329 | if (initrd_filename) { | |
75bb6589 | 330 | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
d7585251 PB |
331 | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
332 | ram_size - initrd_base); | |
1db09b84 AJ |
333 | |
334 | if (initrd_size < 0) { | |
335 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
336 | initrd_filename); | |
337 | exit(1); | |
338 | } | |
339 | } | |
340 | ||
7267c094 | 341 | boot_info = g_malloc0(sizeof(struct boot_info)); |
3b989d49 | 342 | |
1db09b84 AJ |
343 | /* If we're loading a kernel directly, we must load the device tree too. */ |
344 | if (kernel_filename) { | |
3b989d49 AG |
345 | #ifndef CONFIG_FDT |
346 | cpu_abort(env, "Compiled without FDT support - can't load kernel\n"); | |
347 | #endif | |
75bb6589 | 348 | dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
5de6b46d | 349 | if (mpc8544_load_device_tree(env, dt_base, ram_size, |
04088adb | 350 | initrd_base, initrd_size, kernel_cmdline) < 0) { |
1db09b84 AJ |
351 | fprintf(stderr, "couldn't load device tree\n"); |
352 | exit(1); | |
353 | } | |
354 | ||
3b989d49 AG |
355 | boot_info->entry = entry; |
356 | boot_info->dt_base = dt_base; | |
1db09b84 | 357 | } |
3b989d49 | 358 | env->load_info = boot_info; |
1db09b84 | 359 | |
3b989d49 | 360 | if (kvm_enabled()) { |
1db09b84 | 361 | kvmppc_init(); |
3b989d49 | 362 | } |
1db09b84 AJ |
363 | } |
364 | ||
f80f9ec9 | 365 | static QEMUMachine mpc8544ds_machine = { |
1db09b84 AJ |
366 | .name = "mpc8544ds", |
367 | .desc = "mpc8544ds", | |
368 | .init = mpc8544ds_init, | |
1db09b84 | 369 | }; |
f80f9ec9 AL |
370 | |
371 | static void mpc8544ds_machine_init(void) | |
372 | { | |
373 | qemu_register_machine(&mpc8544ds_machine); | |
374 | } | |
375 | ||
376 | machine_init(mpc8544ds_machine_init); |