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1/*
2 * QEMU PowerPC E500 embedded processors pci controller emulation
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc4xx_pci.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include "hw.h"
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18#include "pci.h"
19#include "pci_host.h"
20#include "bswap.h"
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21
22#ifdef DEBUG_PCI
001faf32 23#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8 24#else
001faf32 25#define pci_debug(fmt, ...)
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26#endif
27
28#define PCIE500_CFGADDR 0x0
29#define PCIE500_CFGDATA 0x4
30#define PCIE500_REG_BASE 0xC00
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31#define PCIE500_ALL_SIZE 0x1000
32#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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33
34#define PPCE500_PCI_CONFIG_ADDR 0x0
35#define PPCE500_PCI_CONFIG_DATA 0x4
36#define PPCE500_PCI_INTACK 0x8
37
38#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
39#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
40#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
41#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
42#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
43#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
44#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
45
46#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
47
48#define PCI_POTAR 0x0
49#define PCI_POTEAR 0x4
50#define PCI_POWBAR 0x8
51#define PCI_POWAR 0x10
52
53#define PCI_PITAR 0x0
54#define PCI_PIWBAR 0x8
55#define PCI_PIWBEAR 0xC
56#define PCI_PIWAR 0x10
57
58#define PPCE500_PCI_NR_POBS 5
59#define PPCE500_PCI_NR_PIBS 3
60
61struct pci_outbound {
62 uint32_t potar;
63 uint32_t potear;
64 uint32_t powbar;
65 uint32_t powar;
66};
67
68struct pci_inbound {
69 uint32_t pitar;
70 uint32_t piwbar;
71 uint32_t piwbear;
72 uint32_t piwar;
73};
74
75struct PPCE500PCIState {
be13cc7a 76 PCIHostState pci_state;
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77 struct pci_outbound pob[PPCE500_PCI_NR_POBS];
78 struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
79 uint32_t gasket_time;
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80 qemu_irq irq[4];
81 /* mmio maps */
be13cc7a 82 int reg;
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83};
84
85typedef struct PPCE500PCIState PPCE500PCIState;
86
c227f099 87static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
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88{
89 PPCE500PCIState *pci = opaque;
90 unsigned long win;
91 uint32_t value = 0;
eeae2e7b 92 int idx;
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93
94 win = addr & 0xfe0;
95
96 switch (win) {
97 case PPCE500_PCI_OW1:
98 case PPCE500_PCI_OW2:
99 case PPCE500_PCI_OW3:
100 case PPCE500_PCI_OW4:
eeae2e7b 101 idx = (addr >> 5) & 0x7;
74c62ba8 102 switch (addr & 0xC) {
6875dc8e 103 case PCI_POTAR:
eeae2e7b 104 value = pci->pob[idx].potar;
6875dc8e
LYB
105 break;
106 case PCI_POTEAR:
eeae2e7b 107 value = pci->pob[idx].potear;
6875dc8e
LYB
108 break;
109 case PCI_POWBAR:
eeae2e7b 110 value = pci->pob[idx].powbar;
6875dc8e
LYB
111 break;
112 case PCI_POWAR:
eeae2e7b 113 value = pci->pob[idx].powar;
6875dc8e
LYB
114 break;
115 default:
116 break;
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117 }
118 break;
119
120 case PPCE500_PCI_IW3:
121 case PPCE500_PCI_IW2:
122 case PPCE500_PCI_IW1:
eeae2e7b 123 idx = ((addr >> 5) & 0x3) - 1;
74c62ba8 124 switch (addr & 0xC) {
6875dc8e 125 case PCI_PITAR:
eeae2e7b 126 value = pci->pib[idx].pitar;
6875dc8e
LYB
127 break;
128 case PCI_PIWBAR:
eeae2e7b 129 value = pci->pib[idx].piwbar;
6875dc8e
LYB
130 break;
131 case PCI_PIWBEAR:
eeae2e7b 132 value = pci->pib[idx].piwbear;
6875dc8e
LYB
133 break;
134 case PCI_PIWAR:
eeae2e7b 135 value = pci->pib[idx].piwar;
6875dc8e
LYB
136 break;
137 default:
138 break;
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139 };
140 break;
141
142 case PPCE500_PCI_GASKET_TIMR:
143 value = pci->gasket_time;
144 break;
145
146 default:
147 break;
148 }
149
c0a2a096
BS
150 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
151 win, addr, value);
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152 return value;
153}
154
d60efc6b 155static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
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156 &pci_reg_read4,
157 &pci_reg_read4,
158 &pci_reg_read4,
159};
160
c227f099 161static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
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162 uint32_t value)
163{
164 PPCE500PCIState *pci = opaque;
165 unsigned long win;
eeae2e7b 166 int idx;
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167
168 win = addr & 0xfe0;
169
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170 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
171 __func__, value, win, addr);
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172
173 switch (win) {
174 case PPCE500_PCI_OW1:
175 case PPCE500_PCI_OW2:
176 case PPCE500_PCI_OW3:
177 case PPCE500_PCI_OW4:
eeae2e7b 178 idx = (addr >> 5) & 0x7;
74c62ba8 179 switch (addr & 0xC) {
6875dc8e 180 case PCI_POTAR:
eeae2e7b 181 pci->pob[idx].potar = value;
6875dc8e
LYB
182 break;
183 case PCI_POTEAR:
eeae2e7b 184 pci->pob[idx].potear = value;
6875dc8e
LYB
185 break;
186 case PCI_POWBAR:
eeae2e7b 187 pci->pob[idx].powbar = value;
6875dc8e
LYB
188 break;
189 case PCI_POWAR:
eeae2e7b 190 pci->pob[idx].powar = value;
6875dc8e
LYB
191 break;
192 default:
193 break;
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194 };
195 break;
196
197 case PPCE500_PCI_IW3:
198 case PPCE500_PCI_IW2:
199 case PPCE500_PCI_IW1:
eeae2e7b 200 idx = ((addr >> 5) & 0x3) - 1;
74c62ba8 201 switch (addr & 0xC) {
6875dc8e 202 case PCI_PITAR:
eeae2e7b 203 pci->pib[idx].pitar = value;
6875dc8e
LYB
204 break;
205 case PCI_PIWBAR:
eeae2e7b 206 pci->pib[idx].piwbar = value;
6875dc8e
LYB
207 break;
208 case PCI_PIWBEAR:
eeae2e7b 209 pci->pib[idx].piwbear = value;
6875dc8e
LYB
210 break;
211 case PCI_PIWAR:
eeae2e7b 212 pci->pib[idx].piwar = value;
6875dc8e
LYB
213 break;
214 default:
215 break;
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216 };
217 break;
218
219 case PPCE500_PCI_GASKET_TIMR:
220 pci->gasket_time = value;
221 break;
222
223 default:
224 break;
225 };
226}
227
d60efc6b 228static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
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229 &pci_reg_write4,
230 &pci_reg_write4,
231 &pci_reg_write4,
232};
233
234static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
235{
236 int devno = pci_dev->devfn >> 3, ret = 0;
237
238 switch (devno) {
239 /* Two PCI slot */
240 case 0x11:
241 case 0x12:
242 ret = (irq_num + devno - 0x10) % 4;
243 break;
244 default:
72b310e9 245 printf("Error:%s:unknown dev number\n", __func__);
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246 }
247
248 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
249 pci_dev->devfn, irq_num, ret, devno);
250
251 return ret;
252}
253
5d4e84c8 254static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8 255{
5d4e84c8
JQ
256 qemu_irq *pic = opaque;
257
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258 pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
259
260 qemu_set_irq(pic[irq_num], level);
261}
262
e0433ecc
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263static const VMStateDescription vmstate_pci_outbound = {
264 .name = "pci_outbound",
265 .version_id = 0,
266 .minimum_version_id = 0,
267 .minimum_version_id_old = 0,
268 .fields = (VMStateField[]) {
269 VMSTATE_UINT32(potar, struct pci_outbound),
270 VMSTATE_UINT32(potear, struct pci_outbound),
271 VMSTATE_UINT32(powbar, struct pci_outbound),
272 VMSTATE_UINT32(powar, struct pci_outbound),
273 VMSTATE_END_OF_LIST()
74c62ba8 274 }
e0433ecc 275};
74c62ba8 276
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277static const VMStateDescription vmstate_pci_inbound = {
278 .name = "pci_inbound",
279 .version_id = 0,
280 .minimum_version_id = 0,
281 .minimum_version_id_old = 0,
282 .fields = (VMStateField[]) {
283 VMSTATE_UINT32(pitar, struct pci_inbound),
284 VMSTATE_UINT32(piwbar, struct pci_inbound),
285 VMSTATE_UINT32(piwbear, struct pci_inbound),
286 VMSTATE_UINT32(piwar, struct pci_inbound),
287 VMSTATE_END_OF_LIST()
74c62ba8 288 }
e0433ecc 289};
74c62ba8 290
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291static const VMStateDescription vmstate_ppce500_pci = {
292 .name = "ppce500_pci",
293 .version_id = 1,
294 .minimum_version_id = 1,
295 .minimum_version_id_old = 1,
296 .fields = (VMStateField[]) {
e0433ecc
JQ
297 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
298 vmstate_pci_outbound, struct pci_outbound),
299 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
300 vmstate_pci_outbound, struct pci_inbound),
301 VMSTATE_UINT32(gasket_time, PPCE500PCIState),
302 VMSTATE_END_OF_LIST()
74c62ba8 303 }
e0433ecc 304};
74c62ba8 305
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306static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
307{
308 PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
309 PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
310
d0ed8076
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311 sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
312 sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
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313 cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
314 s->reg);
315}
316
cd0fa1e6
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317static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
318{
d0ed8076
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319 PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
320
321 sysbus_del_memory(dev, &h->conf_mem);
322 sysbus_del_memory(dev, &h->data_mem);
cd0fa1e6
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323 cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
324 IO_MEM_UNASSIGNED);
325}
326
1e39101c
AK
327#include "exec-memory.h"
328
be13cc7a
AG
329static int e500_pcihost_initfn(SysBusDevice *dev)
330{
331 PCIHostState *h;
332 PPCE500PCIState *s;
333 PCIBus *b;
334 int i;
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335 MemoryRegion *address_space_mem = get_system_memory();
336 MemoryRegion *address_space_io = get_system_io();
be13cc7a
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337
338 h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
339 s = DO_UPCAST(PPCE500PCIState, pci_state, h);
340
341 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
342 sysbus_init_irq(dev, &s->irq[i]);
343 }
344
345 b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
aee97b84
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346 mpc85xx_pci_map_irq, s->irq, address_space_mem,
347 address_space_io, PCI_DEVFN(0x11, 0), 4);
be13cc7a
AG
348 s->pci_state.bus = b;
349
350 pci_create_simple(b, 0, "e500-host-bridge");
351
d0ed8076
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352 memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
353 "pci-conf-idx", 4);
354 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
355 "pci-conf-data", 4);
be13cc7a
AG
356 s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
357 DEVICE_BIG_ENDIAN);
cd0fa1e6 358 sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);
be13cc7a
AG
359
360 return 0;
361}
362
be13cc7a
AG
363static PCIDeviceInfo e500_host_bridge_info = {
364 .qdev.name = "e500-host-bridge",
365 .qdev.desc = "Host bridge",
366 .qdev.size = sizeof(PCIDevice),
cdfdec7f
MT
367 .vendor_id = PCI_VENDOR_ID_FREESCALE,
368 .device_id = PCI_DEVICE_ID_MPC8533E,
369 .class_id = PCI_CLASS_PROCESSOR_POWERPC,
be13cc7a
AG
370};
371
372static SysBusDeviceInfo e500_pcihost_info = {
373 .init = e500_pcihost_initfn,
374 .qdev.name = "e500-pcihost",
375 .qdev.size = sizeof(PPCE500PCIState),
376 .qdev.vmsd = &vmstate_ppce500_pci,
377};
378
379static void e500_pci_register(void)
74c62ba8 380{
be13cc7a
AG
381 sysbus_register_withprop(&e500_pcihost_info);
382 pci_qdev_register(&e500_host_bridge_info);
74c62ba8 383}
be13cc7a 384device_init(e500_pci_register);