[qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <yu.liu@freescale.com>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "ppc.h"
#include "ppce500.h"
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"
#include "qemu-log.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_REG_SIZE      (0x1000 - PCIE500_REG_BASE)

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

struct PPCE500PCIState {
    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    PCIHostState pci_state;
    PCIDevice *pci_dev;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
        case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
        case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
        case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
        default: break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
        case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
        case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
        case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
    &pci_reg_read4,
    &pci_reg_read4,
    &pci_reg_read4,
};

static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
                               uint32_t value)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        switch (addr & 0xC) {
        case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
        case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
        case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
        case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        switch (addr & 0xC) {
        case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
        case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
        case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
        case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
        default: break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
    &pci_reg_write4,
    &pci_reg_write4,
    &pci_reg_write4,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknow dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static void ppce500_pci_save(QEMUFile *f, void *opaque)
{
    PPCE500PCIState *controller = opaque;
    int i;

    pci_device_save(controller->pci_dev, f);

    for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
        qemu_put_be32s(f, &controller->pob[i].potar);
        qemu_put_be32s(f, &controller->pob[i].potear);
        qemu_put_be32s(f, &controller->pob[i].powbar);
        qemu_put_be32s(f, &controller->pob[i].powar);
    }

    for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
        qemu_put_be32s(f, &controller->pib[i].pitar);
        qemu_put_be32s(f, &controller->pib[i].piwbar);
        qemu_put_be32s(f, &controller->pib[i].piwbear);
        qemu_put_be32s(f, &controller->pib[i].piwar);
    }
    qemu_put_be32s(f, &controller->gasket_time);
}

static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
{
    PPCE500PCIState *controller = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    pci_device_load(controller->pci_dev, f);

    for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
        qemu_get_be32s(f, &controller->pob[i].potar);
        qemu_get_be32s(f, &controller->pob[i].potear);
        qemu_get_be32s(f, &controller->pob[i].powbar);
        qemu_get_be32s(f, &controller->pob[i].powar);
    }

    for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
        qemu_get_be32s(f, &controller->pib[i].pitar);
        qemu_get_be32s(f, &controller->pib[i].piwbar);
        qemu_get_be32s(f, &controller->pib[i].piwbear);
        qemu_get_be32s(f, &controller->pib[i].piwar);
    }
    qemu_get_be32s(f, &controller->gasket_time);

    return 0;
}

PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
    PPCE500PCIState *controller;
    PCIDevice *d;
    int index;
    static int ppce500_pci_id;

    controller = qemu_mallocz(sizeof(PPCE500PCIState));

    controller->pci_state.bus = pci_register_bus(NULL, "pci",
                                                 mpc85xx_pci_set_irq,
                                                 mpc85xx_pci_map_irq,
                                                 pci_irqs, 0x88, 4);
    d = pci_register_device(controller->pci_state.bus,
                            "host bridge", sizeof(PCIDevice),
                            0, NULL, NULL);

    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
    pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);

    controller->pci_dev = d;

    /* CFGADDR */
    index = pci_host_conf_register_mmio_noswap(&controller->pci_state);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);

    /* CFGDATA */
    index = pci_host_data_register_mmio(&controller->pci_state);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);

    index = cpu_register_io_memory(e500_pci_reg_read,
                                   e500_pci_reg_write, controller);
    if (index < 0)
        goto free;
    cpu_register_physical_memory(registers + PCIE500_REG_BASE,
                                   PCIE500_REG_SIZE, index);

    /* XXX load/save code not tested. */
    register_savevm("ppce500_pci", ppce500_pci_id++, 1,
                    ppce500_pci_save, ppce500_pci_load, controller);

    return controller->pci_state.bus;

free:
    printf("%s error\n", __func__);
    qemu_free(controller);
    return NULL;
}
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <yu.liu@freescale.com>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
	18	#include "ppc.h"
	19	#include "ppce500.h"
74c62ba8 AJ	20	#include "pci.h"
	21	#include "pci_host.h"
	22	#include "bswap.h"
	23	#include "qemu-log.h"
	24
	25	#ifdef DEBUG_PCI
001faf32	26	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	27	#else
001faf32	28	#define pci_debug(fmt, ...)
74c62ba8 AJ	29	#endif
	30
	31	#define PCIE500_CFGADDR 0x0
	32	#define PCIE500_CFGDATA 0x4
	33	#define PCIE500_REG_BASE 0xC00
	34	#define PCIE500_REG_SIZE (0x1000 - PCIE500_REG_BASE)
	35
	36	#define PPCE500_PCI_CONFIG_ADDR 0x0
	37	#define PPCE500_PCI_CONFIG_DATA 0x4
	38	#define PPCE500_PCI_INTACK 0x8
	39
	40	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	45	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	46	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	47
	48	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	49
	50	#define PCI_POTAR 0x0
	51	#define PCI_POTEAR 0x4
	52	#define PCI_POWBAR 0x8
	53	#define PCI_POWAR 0x10
	54
	55	#define PCI_PITAR 0x0
	56	#define PCI_PIWBAR 0x8
	57	#define PCI_PIWBEAR 0xC
	58	#define PCI_PIWAR 0x10
	59
	60	#define PPCE500_PCI_NR_POBS 5
	61	#define PPCE500_PCI_NR_PIBS 3
	62
	63	struct pci_outbound {
	64	uint32_t potar;
	65	uint32_t potear;
	66	uint32_t powbar;
	67	uint32_t powar;
	68	};
	69
	70	struct pci_inbound {
	71	uint32_t pitar;
	72	uint32_t piwbar;
	73	uint32_t piwbear;
	74	uint32_t piwar;
	75	};
	76
	77	struct PPCE500PCIState {
	78	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	79	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	80	uint32_t gasket_time;
	81	PCIHostState pci_state;
	82	PCIDevice *pci_dev;
	83	};
	84
	85	typedef struct PPCE500PCIState PPCE500PCIState;
	86
c227f099	87	static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr)
74c62ba8 AJ	88	{
	89	PPCE500PCIState *pci = opaque;
	90	unsigned long win;
	91	uint32_t value = 0;
	92
	93	win = addr & 0xfe0;
	94
	95	switch (win) {
	96	case PPCE500_PCI_OW1:
	97	case PPCE500_PCI_OW2:
	98	case PPCE500_PCI_OW3:
	99	case PPCE500_PCI_OW4:
	100	switch (addr & 0xC) {
	101	case PCI_POTAR: value = pci->pob[(addr >> 5) & 0x7].potar; break;
	102	case PCI_POTEAR: value = pci->pob[(addr >> 5) & 0x7].potear; break;
	103	case PCI_POWBAR: value = pci->pob[(addr >> 5) & 0x7].powbar; break;
	104	case PCI_POWAR: value = pci->pob[(addr >> 5) & 0x7].powar; break;
	105	default: break;
	106	}
	107	break;
	108
	109	case PPCE500_PCI_IW3:
	110	case PPCE500_PCI_IW2:
	111	case PPCE500_PCI_IW1:
	112	switch (addr & 0xC) {
	113	case PCI_PITAR: value = pci->pib[(addr >> 5) & 0x3].pitar; break;
	114	case PCI_PIWBAR: value = pci->pib[(addr >> 5) & 0x3].piwbar; break;
	115	case PCI_PIWBEAR: value = pci->pib[(addr >> 5) & 0x3].piwbear; break;
	116	case PCI_PIWAR: value = pci->pib[(addr >> 5) & 0x3].piwar; break;
	117	default: break;
	118	};
	119	break;
	120
	121	case PPCE500_PCI_GASKET_TIMR:
	122	value = pci->gasket_time;
	123	break;
	124
	125	default:
	126	break;
	127	}
	128
c0a2a096 BS	129	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	130	win, addr, value);
74c62ba8 AJ	131	return value;
	132	}
	133
d60efc6b	134	static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
74c62ba8 AJ	135	&pci_reg_read4,
	136	&pci_reg_read4,
	137	&pci_reg_read4,
	138	};
	139
c227f099	140	static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
74c62ba8 AJ	141	uint32_t value)
	142	{
	143	PPCE500PCIState *pci = opaque;
	144	unsigned long win;
	145
	146	win = addr & 0xfe0;
	147
c0a2a096 BS	148	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
c0a2a096 BS	149	__func__, value, win, addr);
74c62ba8 AJ	150
	151	switch (win) {
	152	case PPCE500_PCI_OW1:
	153	case PPCE500_PCI_OW2:
	154	case PPCE500_PCI_OW3:
	155	case PPCE500_PCI_OW4:
	156	switch (addr & 0xC) {
	157	case PCI_POTAR: pci->pob[(addr >> 5) & 0x7].potar = value; break;
	158	case PCI_POTEAR: pci->pob[(addr >> 5) & 0x7].potear = value; break;
	159	case PCI_POWBAR: pci->pob[(addr >> 5) & 0x7].powbar = value; break;
	160	case PCI_POWAR: pci->pob[(addr >> 5) & 0x7].powar = value; break;
	161	default: break;
	162	};
	163	break;
	164
	165	case PPCE500_PCI_IW3:
	166	case PPCE500_PCI_IW2:
	167	case PPCE500_PCI_IW1:
	168	switch (addr & 0xC) {
	169	case PCI_PITAR: pci->pib[(addr >> 5) & 0x3].pitar = value; break;
	170	case PCI_PIWBAR: pci->pib[(addr >> 5) & 0x3].piwbar = value; break;
	171	case PCI_PIWBEAR: pci->pib[(addr >> 5) & 0x3].piwbear = value; break;
	172	case PCI_PIWAR: pci->pib[(addr >> 5) & 0x3].piwar = value; break;
	173	default: break;
	174	};
	175	break;
	176
	177	case PPCE500_PCI_GASKET_TIMR:
	178	pci->gasket_time = value;
	179	break;
	180
	181	default:
	182	break;
	183	};
	184	}
	185
d60efc6b	186	static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
74c62ba8 AJ	187	&pci_reg_write4,
	188	&pci_reg_write4,
	189	&pci_reg_write4,
	190	};
	191
	192	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	193	{
	194	int devno = pci_dev->devfn >> 3, ret = 0;
	195
	196	switch (devno) {
	197	/* Two PCI slot */
	198	case 0x11:
	199	case 0x12:
	200	ret = (irq_num + devno - 0x10) % 4;
	201	break;
	202	default:
	203	printf("Error:%s:unknow dev number\n", __func__);
	204	}
	205
	206	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	207	pci_dev->devfn, irq_num, ret, devno);
	208
	209	return ret;
	210	}
	211
5d4e84c8	212	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	213	{
5d4e84c8 JQ	214	qemu_irq *pic = opaque;
5d4e84c8 JQ	215
74c62ba8 AJ	216	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	217
	218	qemu_set_irq(pic[irq_num], level);
	219	}
	220
	221	static void ppce500_pci_save(QEMUFile f, void opaque)
	222	{
	223	PPCE500PCIState *controller = opaque;
	224	int i;
	225
	226	pci_device_save(controller->pci_dev, f);
	227
	228	for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
	229	qemu_put_be32s(f, &controller->pob[i].potar);
	230	qemu_put_be32s(f, &controller->pob[i].potear);
	231	qemu_put_be32s(f, &controller->pob[i].powbar);
	232	qemu_put_be32s(f, &controller->pob[i].powar);
	233	}
	234
	235	for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
	236	qemu_put_be32s(f, &controller->pib[i].pitar);
	237	qemu_put_be32s(f, &controller->pib[i].piwbar);
	238	qemu_put_be32s(f, &controller->pib[i].piwbear);
	239	qemu_put_be32s(f, &controller->pib[i].piwar);
	240	}
	241	qemu_put_be32s(f, &controller->gasket_time);
	242	}
	243
	244	static int ppce500_pci_load(QEMUFile f, void opaque, int version_id)
	245	{
	246	PPCE500PCIState *controller = opaque;
	247	int i;
	248
	249	if (version_id != 1)
	250	return -EINVAL;
	251
	252	pci_device_load(controller->pci_dev, f);
	253
	254	for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
	255	qemu_get_be32s(f, &controller->pob[i].potar);
	256	qemu_get_be32s(f, &controller->pob[i].potear);
	257	qemu_get_be32s(f, &controller->pob[i].powbar);
	258	qemu_get_be32s(f, &controller->pob[i].powar);
	259	}
	260
	261	for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
	262	qemu_get_be32s(f, &controller->pib[i].pitar);
	263	qemu_get_be32s(f, &controller->pib[i].piwbar);
	264	qemu_get_be32s(f, &controller->pib[i].piwbear);
	265	qemu_get_be32s(f, &controller->pib[i].piwar);
	266	}
	267	qemu_get_be32s(f, &controller->gasket_time);
	268
	269	return 0;
	270	}
	271
c227f099	272	PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
74c62ba8 AJ	273	{
	274	PPCE500PCIState *controller;
	275	PCIDevice *d;
	276	int index;
	277	static int ppce500_pci_id;
	278
	279	controller = qemu_mallocz(sizeof(PPCE500PCIState));
	280
02e2da45 PB	281	controller->pci_state.bus = pci_register_bus(NULL, "pci",
02e2da45 PB	282	mpc85xx_pci_set_irq,
74c62ba8 AJ	283	mpc85xx_pci_map_irq,
	284	pci_irqs, 0x88, 4);
	285	d = pci_register_device(controller->pci_state.bus,
	286	"host bridge", sizeof(PCIDevice),
	287	0, NULL, NULL);
	288
a770dc7e AL	289	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
a770dc7e AL	290	pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
74c62ba8 AJ	291	pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
	292
	293	controller->pci_dev = d;
	294
	295	/* CFGADDR */
f08b32fe	296	index = pci_host_conf_register_mmio_noswap(&controller->pci_state);
74c62ba8 AJ	297	if (index < 0)
	298	goto free;
	299	cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
	300
	301	/* CFGDATA */
f08b32fe	302	index = pci_host_data_register_mmio(&controller->pci_state);
74c62ba8 AJ	303	if (index < 0)
	304	goto free;
	305	cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
	306
1eed09cb	307	index = cpu_register_io_memory(e500_pci_reg_read,
74c62ba8 AJ	308	e500_pci_reg_write, controller);
	309	if (index < 0)
	310	goto free;
	311	cpu_register_physical_memory(registers + PCIE500_REG_BASE,
	312	PCIE500_REG_SIZE, index);
	313
	314	/* XXX load/save code not tested. */
	315	register_savevm("ppce500_pci", ppce500_pci_id++, 1,
	316	ppce500_pci_save, ppce500_pci_load, controller);
	317
	318	return controller->pci_state.bus;
	319
	320	free:
	321	printf("%s error\n", __func__);
	322	qemu_free(controller);
	323	return NULL;
	324	}