[qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <yu.liu@freescale.com>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "pci/pci.h"
#include "pci/pci_host.h"
#include "bswap.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_ALL_SIZE      0x1000
#define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)

#define PCIE500_PCI_IOLEN     0x10000ULL

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"

#define PPC_E500_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)

struct PPCE500PCIState {
    PCIHostState parent_obj;

    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    qemu_irq irq[4];
    /* mmio maps */
    MemoryRegion container;
    MemoryRegion iomem;
    MemoryRegion pio;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
                              unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;
    int idx;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            value = pci->pob[idx].potar;
            break;
        case PCI_POTEAR:
            value = pci->pob[idx].potear;
            break;
        case PCI_POWBAR:
            value = pci->pob[idx].powbar;
            break;
        case PCI_POWAR:
            value = pci->pob[idx].powar;
            break;
        default:
            break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            value = pci->pib[idx].pitar;
            break;
        case PCI_PIWBAR:
            value = pci->pib[idx].piwbar;
            break;
        case PCI_PIWBEAR:
            value = pci->pib[idx].piwbear;
            break;
        case PCI_PIWAR:
            value = pci->pib[idx].piwar;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static void pci_reg_write4(void *opaque, hwaddr addr,
                           uint64_t value, unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    int idx;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, (unsigned)value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            pci->pob[idx].potar = value;
            break;
        case PCI_POTEAR:
            pci->pob[idx].potear = value;
            break;
        case PCI_POWBAR:
            pci->pob[idx].powbar = value;
            break;
        case PCI_POWAR:
            pci->pob[idx].powar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            pci->pib[idx].pitar = value;
            break;
        case PCI_PIWBAR:
            pci->pib[idx].piwbar = value;
            break;
        case PCI_PIWBEAR:
            pci->pib[idx].piwbear = value;
            break;
        case PCI_PIWAR:
            pci->pib[idx].piwar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static const MemoryRegionOps e500_pci_reg_ops = {
    .read = pci_reg_read4,
    .write = pci_reg_write4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknown dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_outbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

#include "exec-memory.h"

static int e500_pcihost_initfn(SysBusDevice *dev)
{
    PCIHostState *h;
    PPCE500PCIState *s;
    PCIBus *b;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();

    h = PCI_HOST_BRIDGE(dev);
    s = PPC_E500_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);

    b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
                         mpc85xx_pci_map_irq, s->irq, address_space_mem,
                         &s->pio, PCI_DEVFN(0x11, 0), 4);
    h->bus = b;

    pci_create_simple(b, 0, "e500-host-bridge");

    memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
                          "pci.reg", PCIE500_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);
    sysbus_init_mmio(dev, &s->pio);

    return 0;
}

static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_FREESCALE;
    k->device_id = PCI_DEVICE_ID_MPC8533E;
    k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
    dc->desc = "Host bridge";
}

static const TypeInfo e500_host_bridge_info = {
    .name          = "e500-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = e500_host_bridge_class_init,
};

static void e500_pcihost_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = e500_pcihost_initfn;
    dc->vmsd = &vmstate_ppce500_pci;
}

static const TypeInfo e500_pcihost_info = {
    .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPCE500PCIState),
    .class_init    = e500_pcihost_class_init,
};

static void e500_pci_register_types(void)
{
    type_register_static(&e500_pcihost_info);
    type_register_static(&e500_host_bridge_info);
}

type_init(e500_pci_register_types)
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <yu.liu@freescale.com>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
a2cb15b0 MT	18	#include "pci/pci.h"
a2cb15b0 MT	19	#include "pci/pci_host.h"
74c62ba8	20	#include "bswap.h"
74c62ba8 AJ	21
74c62ba8 AJ	22	#ifdef DEBUG_PCI
001faf32	23	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	24	#else
001faf32	25	#define pci_debug(fmt, ...)
74c62ba8 AJ	26	#endif
	27
	28	#define PCIE500_CFGADDR 0x0
	29	#define PCIE500_CFGDATA 0x4
	30	#define PCIE500_REG_BASE 0xC00
be13cc7a AG	31	#define PCIE500_ALL_SIZE 0x1000
be13cc7a AG	32	#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
74c62ba8	33
a1bc20df AG	34	#define PCIE500_PCI_IOLEN 0x10000ULL
a1bc20df AG	35
74c62ba8 AJ	36	#define PPCE500_PCI_CONFIG_ADDR 0x0
	37	#define PPCE500_PCI_CONFIG_DATA 0x4
	38	#define PPCE500_PCI_INTACK 0x8
	39
	40	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	45	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	46	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	47
	48	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	49
	50	#define PCI_POTAR 0x0
	51	#define PCI_POTEAR 0x4
	52	#define PCI_POWBAR 0x8
	53	#define PCI_POWAR 0x10
	54
	55	#define PCI_PITAR 0x0
	56	#define PCI_PIWBAR 0x8
	57	#define PCI_PIWBEAR 0xC
	58	#define PCI_PIWAR 0x10
	59
	60	#define PPCE500_PCI_NR_POBS 5
	61	#define PPCE500_PCI_NR_PIBS 3
	62
	63	struct pci_outbound {
	64	uint32_t potar;
	65	uint32_t potear;
	66	uint32_t powbar;
	67	uint32_t powar;
	68	};
	69
	70	struct pci_inbound {
	71	uint32_t pitar;
	72	uint32_t piwbar;
	73	uint32_t piwbear;
	74	uint32_t piwar;
	75	};
	76
9c1a61f0 AF	77	#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
	78
	79	#define PPC_E500_PCI_HOST_BRIDGE(obj) \
	80	OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
	81
74c62ba8	82	struct PPCE500PCIState {
67c332fd	83	PCIHostState parent_obj;
9c1a61f0	84
74c62ba8 AJ	85	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	86	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	87	uint32_t gasket_time;
be13cc7a AG	88	qemu_irq irq[4];
be13cc7a AG	89	/* mmio maps */
cb4e15c7	90	MemoryRegion container;
cd5cba79	91	MemoryRegion iomem;
a1bc20df	92	MemoryRegion pio;
74c62ba8 AJ	93	};
	94
	95	typedef struct PPCE500PCIState PPCE500PCIState;
	96
a8170e5e	97	static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
cd5cba79	98	unsigned size)
74c62ba8 AJ	99	{
	100	PPCE500PCIState *pci = opaque;
	101	unsigned long win;
	102	uint32_t value = 0;
eeae2e7b	103	int idx;
74c62ba8 AJ	104
	105	win = addr & 0xfe0;
	106
	107	switch (win) {
	108	case PPCE500_PCI_OW1:
	109	case PPCE500_PCI_OW2:
	110	case PPCE500_PCI_OW3:
	111	case PPCE500_PCI_OW4:
eeae2e7b	112	idx = (addr >> 5) & 0x7;
74c62ba8	113	switch (addr & 0xC) {
6875dc8e	114	case PCI_POTAR:
eeae2e7b	115	value = pci->pob[idx].potar;
6875dc8e LYB	116	break;
6875dc8e LYB	117	case PCI_POTEAR:
eeae2e7b	118	value = pci->pob[idx].potear;
6875dc8e LYB	119	break;
6875dc8e LYB	120	case PCI_POWBAR:
eeae2e7b	121	value = pci->pob[idx].powbar;
6875dc8e LYB	122	break;
6875dc8e LYB	123	case PCI_POWAR:
eeae2e7b	124	value = pci->pob[idx].powar;
6875dc8e LYB	125	break;
	126	default:
	127	break;
74c62ba8 AJ	128	}
	129	break;
	130
	131	case PPCE500_PCI_IW3:
	132	case PPCE500_PCI_IW2:
	133	case PPCE500_PCI_IW1:
eeae2e7b	134	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	135	switch (addr & 0xC) {
6875dc8e	136	case PCI_PITAR:
eeae2e7b	137	value = pci->pib[idx].pitar;
6875dc8e LYB	138	break;
6875dc8e LYB	139	case PCI_PIWBAR:
eeae2e7b	140	value = pci->pib[idx].piwbar;
6875dc8e LYB	141	break;
6875dc8e LYB	142	case PCI_PIWBEAR:
eeae2e7b	143	value = pci->pib[idx].piwbear;
6875dc8e LYB	144	break;
6875dc8e LYB	145	case PCI_PIWAR:
eeae2e7b	146	value = pci->pib[idx].piwar;
6875dc8e LYB	147	break;
	148	default:
	149	break;
74c62ba8 AJ	150	};
	151	break;
	152
	153	case PPCE500_PCI_GASKET_TIMR:
	154	value = pci->gasket_time;
	155	break;
	156
	157	default:
	158	break;
	159	}
	160
c0a2a096 BS	161	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	162	win, addr, value);
74c62ba8 AJ	163	return value;
	164	}
	165
a8170e5e	166	static void pci_reg_write4(void *opaque, hwaddr addr,
cd5cba79	167	uint64_t value, unsigned size)
74c62ba8 AJ	168	{
	169	PPCE500PCIState *pci = opaque;
	170	unsigned long win;
eeae2e7b	171	int idx;
74c62ba8 AJ	172
	173	win = addr & 0xfe0;
	174
c0a2a096	175	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
cd5cba79	176	__func__, (unsigned)value, win, addr);
74c62ba8 AJ	177
	178	switch (win) {
	179	case PPCE500_PCI_OW1:
	180	case PPCE500_PCI_OW2:
	181	case PPCE500_PCI_OW3:
	182	case PPCE500_PCI_OW4:
eeae2e7b	183	idx = (addr >> 5) & 0x7;
74c62ba8	184	switch (addr & 0xC) {
6875dc8e	185	case PCI_POTAR:
eeae2e7b	186	pci->pob[idx].potar = value;
6875dc8e LYB	187	break;
6875dc8e LYB	188	case PCI_POTEAR:
eeae2e7b	189	pci->pob[idx].potear = value;
6875dc8e LYB	190	break;
6875dc8e LYB	191	case PCI_POWBAR:
eeae2e7b	192	pci->pob[idx].powbar = value;
6875dc8e LYB	193	break;
6875dc8e LYB	194	case PCI_POWAR:
eeae2e7b	195	pci->pob[idx].powar = value;
6875dc8e LYB	196	break;
	197	default:
	198	break;
74c62ba8 AJ	199	};
	200	break;
	201
	202	case PPCE500_PCI_IW3:
	203	case PPCE500_PCI_IW2:
	204	case PPCE500_PCI_IW1:
eeae2e7b	205	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	206	switch (addr & 0xC) {
6875dc8e	207	case PCI_PITAR:
eeae2e7b	208	pci->pib[idx].pitar = value;
6875dc8e LYB	209	break;
6875dc8e LYB	210	case PCI_PIWBAR:
eeae2e7b	211	pci->pib[idx].piwbar = value;
6875dc8e LYB	212	break;
6875dc8e LYB	213	case PCI_PIWBEAR:
eeae2e7b	214	pci->pib[idx].piwbear = value;
6875dc8e LYB	215	break;
6875dc8e LYB	216	case PCI_PIWAR:
eeae2e7b	217	pci->pib[idx].piwar = value;
6875dc8e LYB	218	break;
	219	default:
	220	break;
74c62ba8 AJ	221	};
	222	break;
	223
	224	case PPCE500_PCI_GASKET_TIMR:
	225	pci->gasket_time = value;
	226	break;
	227
	228	default:
	229	break;
	230	};
	231	}
	232
cd5cba79 AK	233	static const MemoryRegionOps e500_pci_reg_ops = {
	234	.read = pci_reg_read4,
	235	.write = pci_reg_write4,
	236	.endianness = DEVICE_BIG_ENDIAN,
74c62ba8 AJ	237	};
	238
	239	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	240	{
	241	int devno = pci_dev->devfn >> 3, ret = 0;
	242
	243	switch (devno) {
	244	/* Two PCI slot */
	245	case 0x11:
	246	case 0x12:
	247	ret = (irq_num + devno - 0x10) % 4;
	248	break;
	249	default:
72b310e9	250	printf("Error:%s:unknown dev number\n", __func__);
74c62ba8 AJ	251	}
	252
	253	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	254	pci_dev->devfn, irq_num, ret, devno);
	255
	256	return ret;
	257	}
	258
5d4e84c8	259	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	260	{
5d4e84c8 JQ	261	qemu_irq *pic = opaque;
5d4e84c8 JQ	262
74c62ba8 AJ	263	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	264
	265	qemu_set_irq(pic[irq_num], level);
	266	}
	267
e0433ecc JQ	268	static const VMStateDescription vmstate_pci_outbound = {
	269	.name = "pci_outbound",
	270	.version_id = 0,
	271	.minimum_version_id = 0,
	272	.minimum_version_id_old = 0,
	273	.fields = (VMStateField[]) {
	274	VMSTATE_UINT32(potar, struct pci_outbound),
	275	VMSTATE_UINT32(potear, struct pci_outbound),
	276	VMSTATE_UINT32(powbar, struct pci_outbound),
	277	VMSTATE_UINT32(powar, struct pci_outbound),
	278	VMSTATE_END_OF_LIST()
74c62ba8	279	}
e0433ecc	280	};
74c62ba8	281
e0433ecc JQ	282	static const VMStateDescription vmstate_pci_inbound = {
	283	.name = "pci_inbound",
	284	.version_id = 0,
	285	.minimum_version_id = 0,
	286	.minimum_version_id_old = 0,
	287	.fields = (VMStateField[]) {
	288	VMSTATE_UINT32(pitar, struct pci_inbound),
	289	VMSTATE_UINT32(piwbar, struct pci_inbound),
	290	VMSTATE_UINT32(piwbear, struct pci_inbound),
	291	VMSTATE_UINT32(piwar, struct pci_inbound),
	292	VMSTATE_END_OF_LIST()
74c62ba8	293	}
e0433ecc	294	};
74c62ba8	295
e0433ecc JQ	296	static const VMStateDescription vmstate_ppce500_pci = {
	297	.name = "ppce500_pci",
	298	.version_id = 1,
	299	.minimum_version_id = 1,
	300	.minimum_version_id_old = 1,
	301	.fields = (VMStateField[]) {
e0433ecc JQ	302	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	303	vmstate_pci_outbound, struct pci_outbound),
	304	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
	305	vmstate_pci_outbound, struct pci_inbound),
	306	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
	307	VMSTATE_END_OF_LIST()
74c62ba8	308	}
e0433ecc	309	};
74c62ba8	310
1e39101c AK	311	#include "exec-memory.h"
1e39101c AK	312
be13cc7a AG	313	static int e500_pcihost_initfn(SysBusDevice *dev)
	314	{
	315	PCIHostState *h;
	316	PPCE500PCIState *s;
	317	PCIBus *b;
	318	int i;
aee97b84	319	MemoryRegion *address_space_mem = get_system_memory();
be13cc7a	320
8558d942	321	h = PCI_HOST_BRIDGE(dev);
9c1a61f0	322	s = PPC_E500_PCI_HOST_BRIDGE(dev);
be13cc7a AG	323
	324	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	325	sysbus_init_irq(dev, &s->irq[i]);
	326	}
	327
a1bc20df AG	328	memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
a1bc20df AG	329
9c1a61f0	330	b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
aee97b84	331	mpc85xx_pci_map_irq, s->irq, address_space_mem,
a1bc20df	332	&s->pio, PCI_DEVFN(0x11, 0), 4);
9c1a61f0	333	h->bus = b;
be13cc7a AG	334
	335	pci_create_simple(b, 0, "e500-host-bridge");
	336
cb4e15c7	337	memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
d0ed8076 AK	338	memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
	339	"pci-conf-idx", 4);
	340	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
	341	"pci-conf-data", 4);
cd5cba79 AK	342	memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
cd5cba79 AK	343	"pci.reg", PCIE500_REG_SIZE);
cb4e15c7 BC	344	memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
	345	memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
	346	memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
	347	sysbus_init_mmio(dev, &s->container);
a1bc20df	348	sysbus_init_mmio(dev, &s->pio);
be13cc7a AG	349
	350	return 0;
	351	}
	352
40021f08 AL	353	static void e500_host_bridge_class_init(ObjectClass klass, void data)
40021f08 AL	354	{
39bffca2	355	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	356	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	357
	358	k->vendor_id = PCI_VENDOR_ID_FREESCALE;
	359	k->device_id = PCI_DEVICE_ID_MPC8533E;
	360	k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
39bffca2	361	dc->desc = "Host bridge";
40021f08 AL	362	}
40021f08 AL	363
4240abff	364	static const TypeInfo e500_host_bridge_info = {
39bffca2 AL	365	.name = "e500-host-bridge",
	366	.parent = TYPE_PCI_DEVICE,
	367	.instance_size = sizeof(PCIDevice),
	368	.class_init = e500_host_bridge_class_init,
be13cc7a AG	369	};
be13cc7a AG	370
999e12bb AL	371	static void e500_pcihost_class_init(ObjectClass klass, void data)
999e12bb AL	372	{
39bffca2	373	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	374	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	375
	376	k->init = e500_pcihost_initfn;
39bffca2	377	dc->vmsd = &vmstate_ppce500_pci;
999e12bb AL	378	}
999e12bb AL	379
4240abff	380	static const TypeInfo e500_pcihost_info = {
9c1a61f0	381	.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
8558d942	382	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	383	.instance_size = sizeof(PPCE500PCIState),
39bffca2 AL	384	.class_init = e500_pcihost_class_init,
be13cc7a AG	385	};
be13cc7a AG	386
83f7d43a	387	static void e500_pci_register_types(void)
74c62ba8	388	{
39bffca2 AL	389	type_register_static(&e500_pcihost_info);
39bffca2 AL	390	type_register_static(&e500_host_bridge_info);
74c62ba8	391	}
83f7d43a AF	392
83f7d43a AF	393	type_init(e500_pci_register_types)