[qemu.git] / hw / ppce500_pci.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <yu.liu@freescale.com>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw.h"
#include "pci.h"
#include "pci_host.h"
#include "bswap.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_ALL_SIZE      0x1000
#define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"

#define PPC_E500_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)

struct PPCE500PCIState {
    PCIHostState pci_state;

    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    qemu_irq irq[4];
    /* mmio maps */
    MemoryRegion container;
    MemoryRegion iomem;
};

typedef struct PPCE500PCIState PPCE500PCIState;

static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;
    int idx;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            value = pci->pob[idx].potar;
            break;
        case PCI_POTEAR:
            value = pci->pob[idx].potear;
            break;
        case PCI_POWBAR:
            value = pci->pob[idx].powbar;
            break;
        case PCI_POWAR:
            value = pci->pob[idx].powar;
            break;
        default:
            break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            value = pci->pib[idx].pitar;
            break;
        case PCI_PIWBAR:
            value = pci->pib[idx].piwbar;
            break;
        case PCI_PIWBEAR:
            value = pci->pib[idx].piwbear;
            break;
        case PCI_PIWAR:
            value = pci->pib[idx].piwar;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
                           uint64_t value, unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    int idx;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, (unsigned)value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            pci->pob[idx].potar = value;
            break;
        case PCI_POTEAR:
            pci->pob[idx].potear = value;
            break;
        case PCI_POWBAR:
            pci->pob[idx].powbar = value;
            break;
        case PCI_POWAR:
            pci->pob[idx].powar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            pci->pib[idx].pitar = value;
            break;
        case PCI_PIWBAR:
            pci->pib[idx].piwbar = value;
            break;
        case PCI_PIWBEAR:
            pci->pib[idx].piwbear = value;
            break;
        case PCI_PIWAR:
            pci->pib[idx].piwar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static const MemoryRegionOps e500_pci_reg_ops = {
    .read = pci_reg_read4,
    .write = pci_reg_write4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int devno = pci_dev->devfn >> 3, ret = 0;

    switch (devno) {
        /* Two PCI slot */
        case 0x11:
        case 0x12:
            ret = (irq_num + devno - 0x10) % 4;
            break;
        default:
            printf("Error:%s:unknown dev number\n", __func__);
    }

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, irq_num, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);

    qemu_set_irq(pic[irq_num], level);
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_outbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

#include "exec-memory.h"

static int e500_pcihost_initfn(SysBusDevice *dev)
{
    PCIHostState *h;
    PPCE500PCIState *s;
    PCIBus *b;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *address_space_io = get_system_io();

    h = FROM_SYSBUS(PCIHostState, dev);
    s = PPC_E500_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
                         mpc85xx_pci_map_irq, s->irq, address_space_mem,
                         address_space_io, PCI_DEVFN(0x11, 0), 4);
    h->bus = b;

    pci_create_simple(b, 0, "e500-host-bridge");

    memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
                          "pci.reg", PCIE500_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);

    return 0;
}

static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->vendor_id = PCI_VENDOR_ID_FREESCALE;
    k->device_id = PCI_DEVICE_ID_MPC8533E;
    k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
    dc->desc = "Host bridge";
}

static const TypeInfo e500_host_bridge_info = {
    .name          = "e500-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = e500_host_bridge_class_init,
};

static void e500_pcihost_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = e500_pcihost_initfn;
    dc->vmsd = &vmstate_ppce500_pci;
}

static const TypeInfo e500_pcihost_info = {
    .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PPCE500PCIState),
    .class_init    = e500_pcihost_class_init,
};

static void e500_pci_register_types(void)
{
    type_register_static(&e500_pcihost_info);
    type_register_static(&e500_host_bridge_info);
}

type_init(e500_pci_register_types)
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <yu.liu@freescale.com>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "hw.h"
74c62ba8 AJ	18	#include "pci.h"
	19	#include "pci_host.h"
	20	#include "bswap.h"
74c62ba8 AJ	21
74c62ba8 AJ	22	#ifdef DEBUG_PCI
001faf32	23	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	24	#else
001faf32	25	#define pci_debug(fmt, ...)
74c62ba8 AJ	26	#endif
	27
	28	#define PCIE500_CFGADDR 0x0
	29	#define PCIE500_CFGDATA 0x4
	30	#define PCIE500_REG_BASE 0xC00
be13cc7a AG	31	#define PCIE500_ALL_SIZE 0x1000
be13cc7a AG	32	#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
74c62ba8 AJ	33
	34	#define PPCE500_PCI_CONFIG_ADDR 0x0
	35	#define PPCE500_PCI_CONFIG_DATA 0x4
	36	#define PPCE500_PCI_INTACK 0x8
	37
	38	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	39	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	40	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	41	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	42	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	45
	46	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	47
	48	#define PCI_POTAR 0x0
	49	#define PCI_POTEAR 0x4
	50	#define PCI_POWBAR 0x8
	51	#define PCI_POWAR 0x10
	52
	53	#define PCI_PITAR 0x0
	54	#define PCI_PIWBAR 0x8
	55	#define PCI_PIWBEAR 0xC
	56	#define PCI_PIWAR 0x10
	57
	58	#define PPCE500_PCI_NR_POBS 5
	59	#define PPCE500_PCI_NR_PIBS 3
	60
	61	struct pci_outbound {
	62	uint32_t potar;
	63	uint32_t potear;
	64	uint32_t powbar;
	65	uint32_t powar;
	66	};
	67
	68	struct pci_inbound {
	69	uint32_t pitar;
	70	uint32_t piwbar;
	71	uint32_t piwbear;
	72	uint32_t piwar;
	73	};
	74
9c1a61f0 AF	75	#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
	76
	77	#define PPC_E500_PCI_HOST_BRIDGE(obj) \
	78	OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
	79
74c62ba8	80	struct PPCE500PCIState {
be13cc7a	81	PCIHostState pci_state;
9c1a61f0	82
74c62ba8 AJ	83	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	84	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	85	uint32_t gasket_time;
be13cc7a AG	86	qemu_irq irq[4];
be13cc7a AG	87	/* mmio maps */
cb4e15c7	88	MemoryRegion container;
cd5cba79	89	MemoryRegion iomem;
74c62ba8 AJ	90	};
	91
	92	typedef struct PPCE500PCIState PPCE500PCIState;
	93
cd5cba79 AK	94	static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
cd5cba79 AK	95	unsigned size)
74c62ba8 AJ	96	{
	97	PPCE500PCIState *pci = opaque;
	98	unsigned long win;
	99	uint32_t value = 0;
eeae2e7b	100	int idx;
74c62ba8 AJ	101
	102	win = addr & 0xfe0;
	103
	104	switch (win) {
	105	case PPCE500_PCI_OW1:
	106	case PPCE500_PCI_OW2:
	107	case PPCE500_PCI_OW3:
	108	case PPCE500_PCI_OW4:
eeae2e7b	109	idx = (addr >> 5) & 0x7;
74c62ba8	110	switch (addr & 0xC) {
6875dc8e	111	case PCI_POTAR:
eeae2e7b	112	value = pci->pob[idx].potar;
6875dc8e LYB	113	break;
6875dc8e LYB	114	case PCI_POTEAR:
eeae2e7b	115	value = pci->pob[idx].potear;
6875dc8e LYB	116	break;
6875dc8e LYB	117	case PCI_POWBAR:
eeae2e7b	118	value = pci->pob[idx].powbar;
6875dc8e LYB	119	break;
6875dc8e LYB	120	case PCI_POWAR:
eeae2e7b	121	value = pci->pob[idx].powar;
6875dc8e LYB	122	break;
	123	default:
	124	break;
74c62ba8 AJ	125	}
	126	break;
	127
	128	case PPCE500_PCI_IW3:
	129	case PPCE500_PCI_IW2:
	130	case PPCE500_PCI_IW1:
eeae2e7b	131	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	132	switch (addr & 0xC) {
6875dc8e	133	case PCI_PITAR:
eeae2e7b	134	value = pci->pib[idx].pitar;
6875dc8e LYB	135	break;
6875dc8e LYB	136	case PCI_PIWBAR:
eeae2e7b	137	value = pci->pib[idx].piwbar;
6875dc8e LYB	138	break;
6875dc8e LYB	139	case PCI_PIWBEAR:
eeae2e7b	140	value = pci->pib[idx].piwbear;
6875dc8e LYB	141	break;
6875dc8e LYB	142	case PCI_PIWAR:
eeae2e7b	143	value = pci->pib[idx].piwar;
6875dc8e LYB	144	break;
	145	default:
	146	break;
74c62ba8 AJ	147	};
	148	break;
	149
	150	case PPCE500_PCI_GASKET_TIMR:
	151	value = pci->gasket_time;
	152	break;
	153
	154	default:
	155	break;
	156	}
	157
c0a2a096 BS	158	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	159	win, addr, value);
74c62ba8 AJ	160	return value;
	161	}
	162
c227f099	163	static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
cd5cba79	164	uint64_t value, unsigned size)
74c62ba8 AJ	165	{
	166	PPCE500PCIState *pci = opaque;
	167	unsigned long win;
eeae2e7b	168	int idx;
74c62ba8 AJ	169
	170	win = addr & 0xfe0;
	171
c0a2a096	172	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
cd5cba79	173	__func__, (unsigned)value, win, addr);
74c62ba8 AJ	174
	175	switch (win) {
	176	case PPCE500_PCI_OW1:
	177	case PPCE500_PCI_OW2:
	178	case PPCE500_PCI_OW3:
	179	case PPCE500_PCI_OW4:
eeae2e7b	180	idx = (addr >> 5) & 0x7;
74c62ba8	181	switch (addr & 0xC) {
6875dc8e	182	case PCI_POTAR:
eeae2e7b	183	pci->pob[idx].potar = value;
6875dc8e LYB	184	break;
6875dc8e LYB	185	case PCI_POTEAR:
eeae2e7b	186	pci->pob[idx].potear = value;
6875dc8e LYB	187	break;
6875dc8e LYB	188	case PCI_POWBAR:
eeae2e7b	189	pci->pob[idx].powbar = value;
6875dc8e LYB	190	break;
6875dc8e LYB	191	case PCI_POWAR:
eeae2e7b	192	pci->pob[idx].powar = value;
6875dc8e LYB	193	break;
	194	default:
	195	break;
74c62ba8 AJ	196	};
	197	break;
	198
	199	case PPCE500_PCI_IW3:
	200	case PPCE500_PCI_IW2:
	201	case PPCE500_PCI_IW1:
eeae2e7b	202	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	203	switch (addr & 0xC) {
6875dc8e	204	case PCI_PITAR:
eeae2e7b	205	pci->pib[idx].pitar = value;
6875dc8e LYB	206	break;
6875dc8e LYB	207	case PCI_PIWBAR:
eeae2e7b	208	pci->pib[idx].piwbar = value;
6875dc8e LYB	209	break;
6875dc8e LYB	210	case PCI_PIWBEAR:
eeae2e7b	211	pci->pib[idx].piwbear = value;
6875dc8e LYB	212	break;
6875dc8e LYB	213	case PCI_PIWAR:
eeae2e7b	214	pci->pib[idx].piwar = value;
6875dc8e LYB	215	break;
	216	default:
	217	break;
74c62ba8 AJ	218	};
	219	break;
	220
	221	case PPCE500_PCI_GASKET_TIMR:
	222	pci->gasket_time = value;
	223	break;
	224
	225	default:
	226	break;
	227	};
	228	}
	229
cd5cba79 AK	230	static const MemoryRegionOps e500_pci_reg_ops = {
	231	.read = pci_reg_read4,
	232	.write = pci_reg_write4,
	233	.endianness = DEVICE_BIG_ENDIAN,
74c62ba8 AJ	234	};
	235
	236	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	237	{
	238	int devno = pci_dev->devfn >> 3, ret = 0;
	239
	240	switch (devno) {
	241	/* Two PCI slot */
	242	case 0x11:
	243	case 0x12:
	244	ret = (irq_num + devno - 0x10) % 4;
	245	break;
	246	default:
72b310e9	247	printf("Error:%s:unknown dev number\n", __func__);
74c62ba8 AJ	248	}
	249
	250	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
	251	pci_dev->devfn, irq_num, ret, devno);
	252
	253	return ret;
	254	}
	255
5d4e84c8	256	static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
74c62ba8	257	{
5d4e84c8 JQ	258	qemu_irq *pic = opaque;
5d4e84c8 JQ	259
74c62ba8 AJ	260	pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
	261
	262	qemu_set_irq(pic[irq_num], level);
	263	}
	264
e0433ecc JQ	265	static const VMStateDescription vmstate_pci_outbound = {
	266	.name = "pci_outbound",
	267	.version_id = 0,
	268	.minimum_version_id = 0,
	269	.minimum_version_id_old = 0,
	270	.fields = (VMStateField[]) {
	271	VMSTATE_UINT32(potar, struct pci_outbound),
	272	VMSTATE_UINT32(potear, struct pci_outbound),
	273	VMSTATE_UINT32(powbar, struct pci_outbound),
	274	VMSTATE_UINT32(powar, struct pci_outbound),
	275	VMSTATE_END_OF_LIST()
74c62ba8	276	}
e0433ecc	277	};
74c62ba8	278
e0433ecc JQ	279	static const VMStateDescription vmstate_pci_inbound = {
	280	.name = "pci_inbound",
	281	.version_id = 0,
	282	.minimum_version_id = 0,
	283	.minimum_version_id_old = 0,
	284	.fields = (VMStateField[]) {
	285	VMSTATE_UINT32(pitar, struct pci_inbound),
	286	VMSTATE_UINT32(piwbar, struct pci_inbound),
	287	VMSTATE_UINT32(piwbear, struct pci_inbound),
	288	VMSTATE_UINT32(piwar, struct pci_inbound),
	289	VMSTATE_END_OF_LIST()
74c62ba8	290	}
e0433ecc	291	};
74c62ba8	292
e0433ecc JQ	293	static const VMStateDescription vmstate_ppce500_pci = {
	294	.name = "ppce500_pci",
	295	.version_id = 1,
	296	.minimum_version_id = 1,
	297	.minimum_version_id_old = 1,
	298	.fields = (VMStateField[]) {
e0433ecc JQ	299	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	300	vmstate_pci_outbound, struct pci_outbound),
	301	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
	302	vmstate_pci_outbound, struct pci_inbound),
	303	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
	304	VMSTATE_END_OF_LIST()
74c62ba8	305	}
e0433ecc	306	};
74c62ba8	307
1e39101c AK	308	#include "exec-memory.h"
1e39101c AK	309
be13cc7a AG	310	static int e500_pcihost_initfn(SysBusDevice *dev)
	311	{
	312	PCIHostState *h;
	313	PPCE500PCIState *s;
	314	PCIBus *b;
	315	int i;
aee97b84 AK	316	MemoryRegion *address_space_mem = get_system_memory();
aee97b84 AK	317	MemoryRegion *address_space_io = get_system_io();
be13cc7a	318
9c1a61f0 AF	319	h = FROM_SYSBUS(PCIHostState, dev);
9c1a61f0 AF	320	s = PPC_E500_PCI_HOST_BRIDGE(dev);
be13cc7a AG	321
	322	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	323	sysbus_init_irq(dev, &s->irq[i]);
	324	}
	325
9c1a61f0	326	b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
aee97b84 AK	327	mpc85xx_pci_map_irq, s->irq, address_space_mem,
aee97b84 AK	328	address_space_io, PCI_DEVFN(0x11, 0), 4);
9c1a61f0	329	h->bus = b;
be13cc7a AG	330
	331	pci_create_simple(b, 0, "e500-host-bridge");
	332
cb4e15c7	333	memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
d0ed8076 AK	334	memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
	335	"pci-conf-idx", 4);
	336	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
	337	"pci-conf-data", 4);
cd5cba79 AK	338	memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
cd5cba79 AK	339	"pci.reg", PCIE500_REG_SIZE);
cb4e15c7 BC	340	memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
	341	memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
	342	memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
	343	sysbus_init_mmio(dev, &s->container);
be13cc7a AG	344
	345	return 0;
	346	}
	347
40021f08 AL	348	static void e500_host_bridge_class_init(ObjectClass klass, void data)
40021f08 AL	349	{
39bffca2	350	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	351	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	352
	353	k->vendor_id = PCI_VENDOR_ID_FREESCALE;
	354	k->device_id = PCI_DEVICE_ID_MPC8533E;
	355	k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
39bffca2	356	dc->desc = "Host bridge";
40021f08 AL	357	}
40021f08 AL	358
4240abff	359	static const TypeInfo e500_host_bridge_info = {
39bffca2 AL	360	.name = "e500-host-bridge",
	361	.parent = TYPE_PCI_DEVICE,
	362	.instance_size = sizeof(PCIDevice),
	363	.class_init = e500_host_bridge_class_init,
be13cc7a AG	364	};
be13cc7a AG	365
999e12bb AL	366	static void e500_pcihost_class_init(ObjectClass klass, void data)
999e12bb AL	367	{
39bffca2	368	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	369	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	370
	371	k->init = e500_pcihost_initfn;
39bffca2	372	dc->vmsd = &vmstate_ppce500_pci;
999e12bb AL	373	}
999e12bb AL	374
4240abff	375	static const TypeInfo e500_pcihost_info = {
9c1a61f0	376	.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
39bffca2 AL	377	.parent = TYPE_SYS_BUS_DEVICE,
	378	.instance_size = sizeof(PPCE500PCIState),
	379	.class_init = e500_pcihost_class_init,
be13cc7a AG	380	};
be13cc7a AG	381
83f7d43a	382	static void e500_pci_register_types(void)
74c62ba8	383	{
39bffca2 AL	384	type_register_static(&e500_pcihost_info);
39bffca2 AL	385	type_register_static(&e500_host_bridge_info);
74c62ba8	386	}
83f7d43a AF	387
83f7d43a AF	388	type_init(e500_pci_register_types)