[qemu.git] / hw / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licenced under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_KEYPAD	4
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);

/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);

/* pxa2xx_dma.c */
DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);

/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
                BlockDriverState *bd, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                qemu_irq coverswitch);

/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx_keypad.c */
struct  keymap {
    int column;
    int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
                int size);

/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);

typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;

typedef struct {
    CPUState *env;
    DeviceState *pic;
    qemu_irq reset;
    DeviceState *dma;
    DeviceState *gpio;
    PXA2xxLCDState *lcd;
    SSIBus **ssp;
    PXA2xxI2CState *i2c[2];
    PXA2xxMMCIState *mmc;
    PXA2xxPCMCIAState *pcmcia[2];
    PXA2xxI2SState *i2s;
    PXA2xxFIrState *fir;
    PXA2xxKeyPadState *kp;

    /* Power management */
    target_phys_addr_t pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    target_phys_addr_t cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    target_phys_addr_t mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;
} PXA2xxState;

struct PXA2xxI2SState {
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
PXA2xxState *pxa255_init(unsigned int sdram_size);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
3efda49d	7	* This code is licenced under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
	12	/* Interrupt numbers */
	13	# define PXA2XX_PIC_SSP3 0
	14	# define PXA2XX_PIC_USBH2 2
	15	# define PXA2XX_PIC_USBH1 3
31b87f2e	16	# define PXA2XX_PIC_KEYPAD 4
c1713132 AZ	17	# define PXA2XX_PIC_PWRI2C 6
	18	# define PXA25X_PIC_HWUART 7
	19	# define PXA27X_PIC_OST_4_11 7
	20	# define PXA2XX_PIC_GPIO_0 8
	21	# define PXA2XX_PIC_GPIO_1 9
	22	# define PXA2XX_PIC_GPIO_X 10
	23	# define PXA2XX_PIC_I2S 13
	24	# define PXA26X_PIC_ASSP 15
	25	# define PXA25X_PIC_NSSP 16
	26	# define PXA27X_PIC_SSP2 16
	27	# define PXA2XX_PIC_LCD 17
	28	# define PXA2XX_PIC_I2C 18
	29	# define PXA2XX_PIC_ICP 19
	30	# define PXA2XX_PIC_STUART 20
	31	# define PXA2XX_PIC_BTUART 21
	32	# define PXA2XX_PIC_FFUART 22
	33	# define PXA2XX_PIC_MMC 23
	34	# define PXA2XX_PIC_SSP 24
	35	# define PXA2XX_PIC_DMA 25
	36	# define PXA2XX_PIC_OST_0 26
	37	# define PXA2XX_PIC_RTC1HZ 30
	38	# define PXA2XX_PIC_RTCALARM 31
	39
	40	/* DMA requests */
	41	# define PXA2XX_RX_RQ_I2S 2
	42	# define PXA2XX_TX_RQ_I2S 3
	43	# define PXA2XX_RX_RQ_BTUART 4
	44	# define PXA2XX_TX_RQ_BTUART 5
	45	# define PXA2XX_RX_RQ_FFUART 6
	46	# define PXA2XX_TX_RQ_FFUART 7
	47	# define PXA2XX_RX_RQ_SSP1 13
	48	# define PXA2XX_TX_RQ_SSP1 14
	49	# define PXA2XX_RX_RQ_SSP2 15
	50	# define PXA2XX_TX_RQ_SSP2 16
	51	# define PXA2XX_RX_RQ_ICP 17
	52	# define PXA2XX_TX_RQ_ICP 18
	53	# define PXA2XX_RX_RQ_STUART 19
	54	# define PXA2XX_TX_RQ_STUART 20
	55	# define PXA2XX_RX_RQ_MMCI 21
	56	# define PXA2XX_TX_RQ_MMCI 22
	57	# define PXA2XX_USB_RQ(x) ((x) + 24)
	58	# define PXA2XX_RX_RQ_SSP3 66
	59	# define PXA2XX_TX_RQ_SSP3 67
	60
d95b2f8d AZ	61	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	62	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	63	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	64
c1713132 AZ	65	/* pxa2xx_pic.c */
e1f8c729	66	DeviceState pxa2xx_pic_init(target_phys_addr_t base, CPUState env);
c1713132 AZ	67
c1713132 AZ	68	/* pxa2xx_gpio.c */
0bb53337	69	DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
e1f8c729	70	CPUState env, DeviceState pic, int lines);
0bb53337	71	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
c1713132 AZ	72
c1713132 AZ	73	/* pxa2xx_dma.c */
2115c019 AZ	74	DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
2115c019 AZ	75	DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
c1713132	76
a171fe39	77	/* pxa2xx_lcd.c */
bc24a225	78	typedef struct PXA2xxLCDState PXA2xxLCDState;
c227f099	79	PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
3023f332	80	qemu_irq irq);
bc24a225	81	void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
a171fe39 AZ	82	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	83
	84	/* pxa2xx_mmci.c */
bc24a225	85	typedef struct PXA2xxMMCIState PXA2xxMMCIState;
c227f099	86	PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
2115c019 AZ	87	BlockDriverState *bd, qemu_irq irq,
2115c019 AZ	88	qemu_irq rx_dma, qemu_irq tx_dma);
bc24a225	89	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
02ce600c	90	qemu_irq coverswitch);
a171fe39 AZ	91
a171fe39 AZ	92	/* pxa2xx_pcmcia.c */
bc24a225	93	typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
c227f099	94	PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
bc24a225	95	int pxa2xx_pcmcia_attach(void opaque, PCMCIACardState card);
a171fe39 AZ	96	int pxa2xx_pcmcia_dettach(void *opaque);
	97	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
	98
31b87f2e AZ	99	/* pxa2xx_keypad.c */
	100	struct keymap {
	101	int column;
	102	int row;
	103	};
bc24a225	104	typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
c227f099	105	PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
31b87f2e	106	qemu_irq irq);
bc24a225	107	void pxa27x_register_keypad(PXA2xxKeyPadState kp, struct keymap map,
31b87f2e AZ	108	int size);
31b87f2e AZ	109
c1713132	110	/* pxa2xx.c */
bc24a225	111	typedef struct PXA2xxI2CState PXA2xxI2CState;
c227f099	112	PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929	113	qemu_irq irq, uint32_t page_size);
bc24a225	114	i2c_bus pxa2xx_i2c_bus(PXA2xxI2CState s);
3f582262	115
bc24a225 PB	116	typedef struct PXA2xxI2SState PXA2xxI2SState;
bc24a225 PB	117	typedef struct PXA2xxFIrState PXA2xxFIrState;
c1713132	118
bc24a225	119	typedef struct {
c1713132	120	CPUState *env;
e1f8c729	121	DeviceState *pic;
38641a52	122	qemu_irq reset;
2115c019	123	DeviceState *dma;
0bb53337	124	DeviceState *gpio;
bc24a225	125	PXA2xxLCDState *lcd;
a984a69e	126	SSIBus **ssp;
bc24a225 PB	127	PXA2xxI2CState *i2c[2];
	128	PXA2xxMMCIState *mmc;
	129	PXA2xxPCMCIAState *pcmcia[2];
	130	PXA2xxI2SState *i2s;
	131	PXA2xxFIrState *fir;
	132	PXA2xxKeyPadState *kp;
c1713132 AZ	133
c1713132 AZ	134	/* Power management */
c227f099	135	target_phys_addr_t pm_base;
c1713132 AZ	136	uint32_t pm_regs[0x40];
	137
	138	/* Clock management */
c227f099	139	target_phys_addr_t cm_base;
c1713132 AZ	140	uint32_t cm_regs[4];
	141	uint32_t clkcfg;
	142
	143	/* Memory management */
c227f099	144	target_phys_addr_t mm_base;
c1713132 AZ	145	uint32_t mm_regs[0x1a];
	146
	147	/* Performance monitoring */
	148	uint32_t pmnc;
bc24a225	149	} PXA2xxState;
c1713132	150
bc24a225	151	struct PXA2xxI2SState {
c1713132	152	qemu_irq irq;
2115c019 AZ	153	qemu_irq rx_dma;
2115c019 AZ	154	qemu_irq tx_dma;
c1713132 AZ	155	void (data_req)(void , int, int);
	156
	157	uint32_t control[2];
	158	uint32_t status;
	159	uint32_t mask;
	160	uint32_t clk;
	161
	162	int enable;
	163	int rx_len;
	164	int tx_len;
	165	void (codec_out)(void , uint32_t);
	166	uint32_t (codec_in)(void );
	167	void *opaque;
	168
	169	int fifo_len;
	170	uint32_t fifo[16];
	171	};
	172
	173	# define PA_FMT "0x%08lx"
444ce241	174	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	175
bc24a225 PB	176	PXA2xxState pxa270_init(unsigned int sdram_size, const char revision);
bc24a225 PB	177	PXA2xxState *pxa255_init(unsigned int sdram_size);
c1713132	178
c1713132	179	#endif /* PXA_H */