[qemu.git] / hw / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licenced under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);

/* pxa2xx_timer.c */
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);

/* pxa2xx_gpio.c */
struct pxa2xx_gpio_info_s;
struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, qemu_irq *pic, int lines);
void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
                gpio_handler_t handler, void *opaque);
void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
                void (*handler)(void *opaque), void *opaque);

/* pxa2xx_dma.c */
struct pxa2xx_dma_state_s;
struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
                qemu_irq irq);
struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);

/* pxa2xx_lcd.c */
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
                qemu_irq irq, DisplayState *ds);
void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
                void (*cb)(void *opaque), void *opaque);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
struct pxa2xx_mmci_s;
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
                qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, void *opaque,
                void (*readonly_cb)(void *, int),
                void (*coverswitch_cb)(void *, int));

/* pxa2xx_pcmcia.c */
struct pxa2xx_pcmcia_s;
struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx.c */
struct pxa2xx_ssp_s;
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
                uint32_t (*readfn)(void *opaque),
                void (*writefn)(void *opaque, uint32_t value), void *opaque);

struct pxa2xx_i2c_s;
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);

struct pxa2xx_i2s_s;
struct pxa2xx_fir_s;

struct pxa2xx_state_s {
    CPUState *env;
    qemu_irq *pic;
    struct pxa2xx_dma_state_s *dma;
    struct pxa2xx_gpio_info_s *gpio;
    struct pxa2xx_lcdc_s *lcd;
    struct pxa2xx_ssp_s **ssp;
    struct pxa2xx_i2c_s *i2c[2];
    struct pxa2xx_mmci_s *mmc;
    struct pxa2xx_pcmcia_s *pcmcia[2];
    struct pxa2xx_i2s_s *i2s;
    struct pxa2xx_fir_s *fir;

    /* Power management */
    target_phys_addr_t pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    target_phys_addr_t cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    target_phys_addr_t mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;

    /* Real-Time clock */
    target_phys_addr_t rtc_base;
    uint32_t rttr;
    uint32_t rtsr;
    uint32_t rtar;
    uint32_t rdar1;
    uint32_t rdar2;
    uint32_t ryar1;
    uint32_t ryar2;
    uint32_t swar1;
    uint32_t swar2;
    uint32_t piar;
    uint32_t last_rcnr;
    uint32_t last_rdcr;
    uint32_t last_rycr;
    uint32_t last_swcr;
    uint32_t last_rtcpicr;
    int64_t last_hz;
    int64_t last_sw;
    int64_t last_pi;
    QEMUTimer *rtc_hz;
    QEMUTimer *rtc_rdal1;
    QEMUTimer *rtc_rdal2;
    QEMUTimer *rtc_swal1;
    QEMUTimer *rtc_swal2;
    QEMUTimer *rtc_pi;
};

struct pxa2xx_i2s_s {
    target_phys_addr_t base;
    qemu_irq irq;
    struct pxa2xx_dma_state_s *dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
                const char *revision);
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);

void pxa2xx_reset(int line, int level, void *opaque);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
3efda49d	7	* This code is licenced under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
	12	/* Interrupt numbers */
	13	# define PXA2XX_PIC_SSP3 0
	14	# define PXA2XX_PIC_USBH2 2
	15	# define PXA2XX_PIC_USBH1 3
	16	# define PXA2XX_PIC_PWRI2C 6
	17	# define PXA25X_PIC_HWUART 7
	18	# define PXA27X_PIC_OST_4_11 7
	19	# define PXA2XX_PIC_GPIO_0 8
	20	# define PXA2XX_PIC_GPIO_1 9
	21	# define PXA2XX_PIC_GPIO_X 10
	22	# define PXA2XX_PIC_I2S 13
	23	# define PXA26X_PIC_ASSP 15
	24	# define PXA25X_PIC_NSSP 16
	25	# define PXA27X_PIC_SSP2 16
	26	# define PXA2XX_PIC_LCD 17
	27	# define PXA2XX_PIC_I2C 18
	28	# define PXA2XX_PIC_ICP 19
	29	# define PXA2XX_PIC_STUART 20
	30	# define PXA2XX_PIC_BTUART 21
	31	# define PXA2XX_PIC_FFUART 22
	32	# define PXA2XX_PIC_MMC 23
	33	# define PXA2XX_PIC_SSP 24
	34	# define PXA2XX_PIC_DMA 25
	35	# define PXA2XX_PIC_OST_0 26
	36	# define PXA2XX_PIC_RTC1HZ 30
	37	# define PXA2XX_PIC_RTCALARM 31
	38
	39	/* DMA requests */
	40	# define PXA2XX_RX_RQ_I2S 2
	41	# define PXA2XX_TX_RQ_I2S 3
	42	# define PXA2XX_RX_RQ_BTUART 4
	43	# define PXA2XX_TX_RQ_BTUART 5
	44	# define PXA2XX_RX_RQ_FFUART 6
	45	# define PXA2XX_TX_RQ_FFUART 7
	46	# define PXA2XX_RX_RQ_SSP1 13
	47	# define PXA2XX_TX_RQ_SSP1 14
	48	# define PXA2XX_RX_RQ_SSP2 15
	49	# define PXA2XX_TX_RQ_SSP2 16
	50	# define PXA2XX_RX_RQ_ICP 17
	51	# define PXA2XX_TX_RQ_ICP 18
	52	# define PXA2XX_RX_RQ_STUART 19
	53	# define PXA2XX_TX_RQ_STUART 20
	54	# define PXA2XX_RX_RQ_MMCI 21
	55	# define PXA2XX_TX_RQ_MMCI 22
	56	# define PXA2XX_USB_RQ(x) ((x) + 24)
	57	# define PXA2XX_RX_RQ_SSP3 66
	58	# define PXA2XX_TX_RQ_SSP3 67
	59
d95b2f8d AZ	60	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	61	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	62	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	63
c1713132 AZ	64	/* pxa2xx_pic.c */
c1713132 AZ	65	qemu_irq pxa2xx_pic_init(target_phys_addr_t base, CPUState env);
c1713132 AZ	66
a171fe39	67	/* pxa2xx_timer.c */
3f582262 AZ	68	void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
3f582262 AZ	69	void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
a171fe39	70
c1713132 AZ	71	/* pxa2xx_gpio.c */
	72	struct pxa2xx_gpio_info_s;
	73	struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
	74	CPUState env, qemu_irq pic, int lines);
	75	void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level);
	76	void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
	77	gpio_handler_t handler, void *opaque);
	78	void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
	79	void (handler)(void opaque), void *opaque);
	80
	81	/* pxa2xx_dma.c */
	82	struct pxa2xx_dma_state_s;
	83	struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
	84	qemu_irq irq);
	85	struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
	86	qemu_irq irq);
	87	void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
	88
a171fe39 AZ	89	/* pxa2xx_lcd.c */
	90	struct pxa2xx_lcdc_s;
	91	struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
	92	qemu_irq irq, DisplayState *ds);
	93	void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s,
	94	void (cb)(void opaque), void *opaque);
	95	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	96
	97	/* pxa2xx_mmci.c */
	98	struct pxa2xx_mmci_s;
	99	struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
	100	qemu_irq irq, void *dma);
	101	void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s s, void opaque,
	102	void (readonly_cb)(void , int),
	103	void (coverswitch_cb)(void , int));
	104
	105	/* pxa2xx_pcmcia.c */
	106	struct pxa2xx_pcmcia_s;
	107	struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
	108	int pxa2xx_pcmcia_attach(void opaque, struct pcmcia_card_s card);
	109	int pxa2xx_pcmcia_dettach(void *opaque);
	110	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
	111
c1713132 AZ	112	/* pxa2xx.c */
	113	struct pxa2xx_ssp_s;
	114	void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
	115	uint32_t (readfn)(void opaque),
	116	void (writefn)(void opaque, uint32_t value), void *opaque);
	117
3f582262 AZ	118	struct pxa2xx_i2c_s;
3f582262 AZ	119	struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929	120	qemu_irq irq, uint32_t page_size);
3f582262 AZ	121	i2c_bus pxa2xx_i2c_bus(struct pxa2xx_i2c_s s);
3f582262 AZ	122
c1713132 AZ	123	struct pxa2xx_i2s_s;
	124	struct pxa2xx_fir_s;
	125
	126	struct pxa2xx_state_s {
	127	CPUState *env;
	128	qemu_irq *pic;
	129	struct pxa2xx_dma_state_s *dma;
	130	struct pxa2xx_gpio_info_s *gpio;
a171fe39	131	struct pxa2xx_lcdc_s *lcd;
c1713132	132	struct pxa2xx_ssp_s **ssp;
3f582262	133	struct pxa2xx_i2c_s *i2c[2];
a171fe39 AZ	134	struct pxa2xx_mmci_s *mmc;
a171fe39 AZ	135	struct pxa2xx_pcmcia_s *pcmcia[2];
c1713132 AZ	136	struct pxa2xx_i2s_s *i2s;
	137	struct pxa2xx_fir_s *fir;
	138
	139	/* Power management */
	140	target_phys_addr_t pm_base;
	141	uint32_t pm_regs[0x40];
	142
	143	/* Clock management */
	144	target_phys_addr_t cm_base;
	145	uint32_t cm_regs[4];
	146	uint32_t clkcfg;
	147
	148	/* Memory management */
	149	target_phys_addr_t mm_base;
	150	uint32_t mm_regs[0x1a];
	151
	152	/* Performance monitoring */
	153	uint32_t pmnc;
	154
	155	/* Real-Time clock */
	156	target_phys_addr_t rtc_base;
	157	uint32_t rttr;
	158	uint32_t rtsr;
	159	uint32_t rtar;
	160	uint32_t rdar1;
	161	uint32_t rdar2;
	162	uint32_t ryar1;
	163	uint32_t ryar2;
	164	uint32_t swar1;
	165	uint32_t swar2;
	166	uint32_t piar;
	167	uint32_t last_rcnr;
	168	uint32_t last_rdcr;
	169	uint32_t last_rycr;
	170	uint32_t last_swcr;
	171	uint32_t last_rtcpicr;
	172	int64_t last_hz;
	173	int64_t last_sw;
	174	int64_t last_pi;
	175	QEMUTimer *rtc_hz;
	176	QEMUTimer *rtc_rdal1;
	177	QEMUTimer *rtc_rdal2;
	178	QEMUTimer *rtc_swal1;
	179	QEMUTimer *rtc_swal2;
	180	QEMUTimer *rtc_pi;
	181	};
	182
	183	struct pxa2xx_i2s_s {
	184	target_phys_addr_t base;
	185	qemu_irq irq;
	186	struct pxa2xx_dma_state_s *dma;
	187	void (data_req)(void , int, int);
	188
	189	uint32_t control[2];
	190	uint32_t status;
	191	uint32_t mask;
	192	uint32_t clk;
	193
	194	int enable;
	195	int rx_len;
	196	int tx_len;
	197	void (codec_out)(void , uint32_t);
	198	uint32_t (codec_in)(void );
	199	void *opaque;
200
201	int fifo_len;
202	uint32_t fifo[16];
203	};
204
205	# define PA_FMT "0x%08lx"
444ce241	206	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	207
d95b2f8d AZ	208	struct pxa2xx_state_s pxa270_init(unsigned int sdram_size, DisplayState ds,
	209	const char *revision);
	210	struct pxa2xx_state_s pxa255_init(unsigned int sdram_size, DisplayState ds);
c1713132 AZ	211
	212	void pxa2xx_reset(int line, int level, void *opaque);
	213
	214	#endif /* PXA_H */