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[qemu.git] / hw / pxa2xx.c
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c1713132
AZ		 1/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10# include "vl.h"
11
12static struct {
13 target_phys_addr_t io_base;
14 int irqn;
15} pxa255_serial[] = {
16 { 0x40100000, PXA2XX_PIC_FFUART },
17 { 0x40200000, PXA2XX_PIC_BTUART },
18 { 0x40700000, PXA2XX_PIC_STUART },
19 { 0x41600000, PXA25X_PIC_HWUART },
20 { 0, 0 }
21}, pxa270_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0, 0 }
26};
27
28static struct {
29 target_phys_addr_t io_base;
30 int irqn;
31} pxa250_ssp[] = {
32 { 0x41000000, PXA2XX_PIC_SSP },
33 { 0, 0 }
34}, pxa255_ssp[] = {
35 { 0x41000000, PXA2XX_PIC_SSP },
36 { 0x41400000, PXA25X_PIC_NSSP },
37 { 0, 0 }
38}, pxa26x_ssp[] = {
39 { 0x41000000, PXA2XX_PIC_SSP },
40 { 0x41400000, PXA25X_PIC_NSSP },
41 { 0x41500000, PXA26X_PIC_ASSP },
42 { 0, 0 }
43}, pxa27x_ssp[] = {
44 { 0x41000000, PXA2XX_PIC_SSP },
45 { 0x41700000, PXA27X_PIC_SSP2 },
46 { 0x41900000, PXA2XX_PIC_SSP3 },
47 { 0, 0 }
48};
49
50#define PMCR 0x00 /* Power Manager Control register */
51#define PSSR 0x04 /* Power Manager Sleep Status register */
52#define PSPR 0x08 /* Power Manager Scratch-Pad register */
53#define PWER 0x0c /* Power Manager Wake-Up Enable register */
54#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56#define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57#define PCFR 0x1c /* Power Manager General Configuration register */
58#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62#define RCSR 0x30 /* Reset Controller Status register */
63#define PSLR 0x34 /* Power Manager Sleep Configuration register */
64#define PTSR 0x38 /* Power Manager Standby Configuration register */
65#define PVCR 0x40 /* Power Manager Voltage Change Control register */
66#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
71
3f582262
AZ		 72static uint32_t pxa2xx_i2c_read(void *, target_phys_addr_t);
73static void pxa2xx_i2c_write(void *, target_phys_addr_t, uint32_t);
74
c1713132
AZ		 75static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
76{
77 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
3f582262
AZ		 78 if (addr > s->pm_base + PCMD31) {
79 /* Special case: PWRI2C registers appear in the same range. */
80 return pxa2xx_i2c_read(s->i2c[1], addr);
81 }
c1713132
AZ		 82 addr -= s->pm_base;
83
84 switch (addr) {
85 case PMCR ... PCMD31:
86 if (addr & 3)
87 goto fail;
88
89 return s->pm_regs[addr >> 2];
90 default:
91 fail:
92 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
93 break;
94 }
95 return 0;
96}
97
98static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
99 uint32_t value)
100{
101 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
3f582262
AZ		 102 if (addr > s->pm_base + PCMD31) {
103 /* Special case: PWRI2C registers appear in the same range. */
104 pxa2xx_i2c_write(s->i2c[1], addr, value);
105 return;
106 }
c1713132
AZ		 107 addr -= s->pm_base;
108
109 switch (addr) {
110 case PMCR:
111 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
112 s->pm_regs[addr >> 2] |= value & 0x15;
113 break;
114
115 case PSSR: /* Read-clean registers */
116 case RCSR:
117 case PKSR:
118 s->pm_regs[addr >> 2] &= ~value;
119 break;
120
121 default: /* Read-write registers */
122 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
123 s->pm_regs[addr >> 2] = value;
124 break;
125 }
126
127 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
128 break;
129 }
130}
131
132static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
133 pxa2xx_pm_read,
134 pxa2xx_pm_read,
135 pxa2xx_pm_read,
136};
137
138static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
139 pxa2xx_pm_write,
140 pxa2xx_pm_write,
141 pxa2xx_pm_write,
142};
143
144#define CCCR 0x00 /* Core Clock Configuration register */
145#define CKEN 0x04 /* Clock Enable register */
146#define OSCC 0x08 /* Oscillator Configuration register */
147#define CCSR 0x0c /* Core Clock Status register */
148
149static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
150{
151 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
152 addr -= s->cm_base;
153
154 switch (addr) {
155 case CCCR:
156 case CKEN:
157 case OSCC:
158 return s->cm_regs[addr >> 2];
159
160 case CCSR:
161 return s->cm_regs[CCCR >> 2] | (3 << 28);
162
163 default:
164 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
165 break;
166 }
167 return 0;
168}
169
170static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
171 uint32_t value)
172{
173 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
174 addr -= s->cm_base;
175
176 switch (addr) {
177 case CCCR:
178 case CKEN:
179 s->cm_regs[addr >> 2] = value;
180 break;
181
182 case OSCC:
565d2895 183 s->cm_regs[addr >> 2] &= ~0x6c;
c1713132 184 s->cm_regs[addr >> 2] |= value & 0x6e;
565d2895
AZ		 185 if ((value >> 1) & 1) /* OON */
186 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
c1713132
AZ		 187 break;
188
189 default:
190 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
191 break;
192 }
193}
194
195static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
196 pxa2xx_cm_read,
197 pxa2xx_cm_read,
198 pxa2xx_cm_read,
199};
200
201static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
202 pxa2xx_cm_write,
203 pxa2xx_cm_write,
204 pxa2xx_cm_write,
205};
206
207static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
208{
209 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
210
211 switch (reg) {
212 case 6: /* Clock Configuration register */
213 return s->clkcfg;
214
215 case 7: /* Power Mode register */
216 return 0;
217
218 default:
219 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
220 break;
221 }
222 return 0;
223}
224
225static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
226 uint32_t value)
227{
228 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
229 static const char *pwrmode[8] = {
230 "Normal", "Idle", "Deep-idle", "Standby",
231 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
232 };
233
234 switch (reg) {
235 case 6: /* Clock Configuration register */
236 s->clkcfg = value & 0xf;
237 if (value & 2)
238 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
239 break;
240
241 case 7: /* Power Mode register */
242 if (value & 8)
243 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
244 switch (value & 7) {
245 case 0:
246 /* Do nothing */
247 break;
248
249 case 1:
250 /* Idle */
251 if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */
252 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
253 break;
254 }
255 /* Fall through. */
256
257 case 2:
258 /* Deep-Idle */
259 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
260 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
261 goto message;
262
263 case 3:
a90b7318
AZ		 264 s->env->uncached_cpsr =
265 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
c1713132
AZ		 266 s->env->cp15.c1_sys = 0;
267 s->env->cp15.c1_coproc = 0;
ce819861 268 s->env->cp15.c2_base = 0;
c1713132
AZ		 269 s->env->cp15.c3 = 0;
270 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
271 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
272
273 /*
274 * The scratch-pad register is almost universally used
275 * for storing the return address on suspend. For the
276 * lack of a resuming bootloader, perform a jump
277 * directly to that address.
278 */
279 memset(s->env->regs, 0, 4 * 15);
280 s->env->regs[15] = s->pm_regs[PSPR >> 2];
281
282#if 0
283 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
284 cpu_physical_memory_write(0, &buffer, 4);
285 buffer = s->pm_regs[PSPR >> 2];
286 cpu_physical_memory_write(8, &buffer, 4);
287#endif
288
289 /* Suspend */
290 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
291
292 goto message;
293
294 default:
295 message:
296 printf("%s: machine entered %s mode\n", __FUNCTION__,
297 pwrmode[value & 7]);
298 }
299 break;
300
301 default:
302 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
303 break;
304 }
305}
306
307/* Performace Monitoring Registers */
308#define CPPMNC 0 /* Performance Monitor Control register */
309#define CPCCNT 1 /* Clock Counter register */
310#define CPINTEN 4 /* Interrupt Enable register */
311#define CPFLAG 5 /* Overflow Flag register */
312#define CPEVTSEL 8 /* Event Selection register */
313
314#define CPPMN0 0 /* Performance Count register 0 */
315#define CPPMN1 1 /* Performance Count register 1 */
316#define CPPMN2 2 /* Performance Count register 2 */
317#define CPPMN3 3 /* Performance Count register 3 */
318
319static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
320{
321 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
322
323 switch (reg) {
324 case CPPMNC:
325 return s->pmnc;
326 case CPCCNT:
327 if (s->pmnc & 1)
328 return qemu_get_clock(vm_clock);
329 else
330 return 0;
331 case CPINTEN:
332 case CPFLAG:
333 case CPEVTSEL:
334 return 0;
335
336 default:
337 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
338 break;
339 }
340 return 0;
341}
342
343static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
344 uint32_t value)
345{
346 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
347
348 switch (reg) {
349 case CPPMNC:
350 s->pmnc = value;
351 break;
352
353 case CPCCNT:
354 case CPINTEN:
355 case CPFLAG:
356 case CPEVTSEL:
357 break;
358
359 default:
360 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
361 break;
362 }
363}
364
365static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
366{
367 switch (crm) {
368 case 0:
369 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
370 case 1:
371 return pxa2xx_perf_read(opaque, op2, reg, crm);
372 case 2:
373 switch (reg) {
374 case CPPMN0:
375 case CPPMN1:
376 case CPPMN2:
377 case CPPMN3:
378 return 0;
379 }
380 /* Fall through */
381 default:
382 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
383 break;
384 }
385 return 0;
386}
387
388static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
389 uint32_t value)
390{
391 switch (crm) {
392 case 0:
393 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
394 break;
395 case 1:
396 pxa2xx_perf_write(opaque, op2, reg, crm, value);
397 break;
398 case 2:
399 switch (reg) {
400 case CPPMN0:
401 case CPPMN1:
402 case CPPMN2:
403 case CPPMN3:
404 return;
405 }
406 /* Fall through */
407 default:
408 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
409 break;
410 }
411}
412
413#define MDCNFG 0x00 /* SDRAM Configuration register */
414#define MDREFR 0x04 /* SDRAM Refresh Control register */
415#define MSC0 0x08 /* Static Memory Control register 0 */
416#define MSC1 0x0c /* Static Memory Control register 1 */
417#define MSC2 0x10 /* Static Memory Control register 2 */
418#define MECR 0x14 /* Expansion Memory Bus Config register */
419#define SXCNFG 0x1c /* Synchronous Static Memory Config register */
420#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
421#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
422#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
423#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
424#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
425#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
426#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
427#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
428#define ARB_CNTL 0x48 /* Arbiter Control register */
429#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
430#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
431#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
432#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
433#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
434#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
435#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
436
437static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
438{
439 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
440 addr -= s->mm_base;
441
442 switch (addr) {
443 case MDCNFG ... SA1110:
444 if ((addr & 3) == 0)
445 return s->mm_regs[addr >> 2];
446
447 default:
448 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
449 break;
450 }
451 return 0;
452}
453
454static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
455 uint32_t value)
456{
457 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
458 addr -= s->mm_base;
459
460 switch (addr) {
461 case MDCNFG ... SA1110:
462 if ((addr & 3) == 0) {
463 s->mm_regs[addr >> 2] = value;
464 break;
465 }
466
467 default:
468 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
469 break;
470 }
471}
472
473static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
474 pxa2xx_mm_read,
475 pxa2xx_mm_read,
476 pxa2xx_mm_read,
477};
478
479static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
480 pxa2xx_mm_write,
481 pxa2xx_mm_write,
482 pxa2xx_mm_write,
483};
484
485/* Synchronous Serial Ports */
486struct pxa2xx_ssp_s {
487 target_phys_addr_t base;
488 qemu_irq irq;
489 int enable;
490
491 uint32_t sscr[2];
492 uint32_t sspsp;
493 uint32_t ssto;
494 uint32_t ssitr;
495 uint32_t sssr;
496 uint8_t sstsa;
497 uint8_t ssrsa;
498 uint8_t ssacd;
499
500 uint32_t rx_fifo[16];
501 int rx_level;
502 int rx_start;
503
504 uint32_t (*readfn)(void *opaque);
505 void (*writefn)(void *opaque, uint32_t value);
506 void *opaque;
507};
508
509#define SSCR0 0x00 /* SSP Control register 0 */
510#define SSCR1 0x04 /* SSP Control register 1 */
511#define SSSR 0x08 /* SSP Status register */
512#define SSITR 0x0c /* SSP Interrupt Test register */
513#define SSDR 0x10 /* SSP Data register */
514#define SSTO 0x28 /* SSP Time-Out register */
515#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
516#define SSTSA 0x30 /* SSP TX Time Slot Active register */
517#define SSRSA 0x34 /* SSP RX Time Slot Active register */
518#define SSTSS 0x38 /* SSP Time Slot Status register */
519#define SSACD 0x3c /* SSP Audio Clock Divider register */
520
521/* Bitfields for above registers */
522#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
523#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
524#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
525#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
526#define SSCR0_SSE (1 << 7)
527#define SSCR0_RIM (1 << 22)
528#define SSCR0_TIM (1 << 23)
529#define SSCR0_MOD (1 << 31)
530#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
531#define SSCR1_RIE (1 << 0)
532#define SSCR1_TIE (1 << 1)
533#define SSCR1_LBM (1 << 2)
534#define SSCR1_MWDS (1 << 5)
535#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
536#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
537#define SSCR1_EFWR (1 << 14)
538#define SSCR1_PINTE (1 << 18)
539#define SSCR1_TINTE (1 << 19)
540#define SSCR1_RSRE (1 << 20)
541#define SSCR1_TSRE (1 << 21)
542#define SSCR1_EBCEI (1 << 29)
543#define SSITR_INT (7 << 5)
544#define SSSR_TNF (1 << 2)
545#define SSSR_RNE (1 << 3)
546#define SSSR_TFS (1 << 5)
547#define SSSR_RFS (1 << 6)
548#define SSSR_ROR (1 << 7)
549#define SSSR_PINT (1 << 18)
550#define SSSR_TINT (1 << 19)
551#define SSSR_EOC (1 << 20)
552#define SSSR_TUR (1 << 21)
553#define SSSR_BCE (1 << 23)
554#define SSSR_RW 0x00bc0080
555
556static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
557{
558 int level = 0;
559
560 level |= s->ssitr & SSITR_INT;
561 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
562 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
563 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
564 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
565 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
566 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
567 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
568 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
569 qemu_set_irq(s->irq, !!level);
570}
571
572static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
573{
574 s->sssr &= ~(0xf << 12); /* Clear RFL */
575 s->sssr &= ~(0xf << 8); /* Clear TFL */
576 s->sssr &= ~SSSR_TNF;
577 if (s->enable) {
578 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
579 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
580 s->sssr |= SSSR_RFS;
581 else
582 s->sssr &= ~SSSR_RFS;
583 if (0 <= SSCR1_TFT(s->sscr[1]))
584 s->sssr |= SSSR_TFS;
585 else
586 s->sssr &= ~SSSR_TFS;
587 if (s->rx_level)
588 s->sssr |= SSSR_RNE;
589 else
590 s->sssr &= ~SSSR_RNE;
591 s->sssr |= SSSR_TNF;
592 }
593
594 pxa2xx_ssp_int_update(s);
595}
596
597static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
598{
599 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
600 uint32_t retval;
601 addr -= s->base;
602
603 switch (addr) {
604 case SSCR0:
605 return s->sscr[0];
606 case SSCR1:
607 return s->sscr[1];
608 case SSPSP:
609 return s->sspsp;
610 case SSTO:
611 return s->ssto;
612 case SSITR:
613 return s->ssitr;
614 case SSSR:
615 return s->sssr | s->ssitr;
616 case SSDR:
617 if (!s->enable)
618 return 0xffffffff;
619 if (s->rx_level < 1) {
620 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
621 return 0xffffffff;
622 }
623 s->rx_level --;
624 retval = s->rx_fifo[s->rx_start ++];
625 s->rx_start &= 0xf;
626 pxa2xx_ssp_fifo_update(s);
627 return retval;
628 case SSTSA:
629 return s->sstsa;
630 case SSRSA:
631 return s->ssrsa;
632 case SSTSS:
633 return 0;
634 case SSACD:
635 return s->ssacd;
636 default:
637 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
638 break;
639 }
640 return 0;
641}
642
643static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
644 uint32_t value)
645{
646 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
647 addr -= s->base;
648
649 switch (addr) {
650 case SSCR0:
651 s->sscr[0] = value & 0xc7ffffff;
652 s->enable = value & SSCR0_SSE;
653 if (value & SSCR0_MOD)
654 printf("%s: Attempt to use network mode\n", __FUNCTION__);
655 if (s->enable && SSCR0_DSS(value) < 4)
656 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
657 SSCR0_DSS(value));
658 if (!(value & SSCR0_SSE)) {
659 s->sssr = 0;
660 s->ssitr = 0;
661 s->rx_level = 0;
662 }
663 pxa2xx_ssp_fifo_update(s);
664 break;
665
666 case SSCR1:
667 s->sscr[1] = value;
668 if (value & (SSCR1_LBM | SSCR1_EFWR))
669 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
670 pxa2xx_ssp_fifo_update(s);
671 break;
672
673 case SSPSP:
674 s->sspsp = value;
675 break;
676
677 case SSTO:
678 s->ssto = value;
679 break;
680
681 case SSITR:
682 s->ssitr = value & SSITR_INT;
683 pxa2xx_ssp_int_update(s);
684 break;
685
686 case SSSR:
687 s->sssr &= ~(value & SSSR_RW);
688 pxa2xx_ssp_int_update(s);
689 break;
690
691 case SSDR:
692 if (SSCR0_UWIRE(s->sscr[0])) {
693 if (s->sscr[1] & SSCR1_MWDS)
694 value &= 0xffff;
695 else
696 value &= 0xff;
697 } else
698 /* Note how 32bits overflow does no harm here */
699 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
700
701 /* Data goes from here to the Tx FIFO and is shifted out from
702 * there directly to the slave, no need to buffer it.
703 */
704 if (s->enable) {
705 if (s->writefn)
706 s->writefn(s->opaque, value);
707
708 if (s->rx_level < 0x10) {
709 if (s->readfn)
710 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
711 s->readfn(s->opaque);
712 else
713 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
714 } else
715 s->sssr |= SSSR_ROR;
716 }
717 pxa2xx_ssp_fifo_update(s);
718 break;
719
720 case SSTSA:
721 s->sstsa = value;
722 break;
723
724 case SSRSA:
725 s->ssrsa = value;
726 break;
727
728 case SSACD:
729 s->ssacd = value;
730 break;
731
732 default:
733 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
734 break;
735 }
736}
737
738void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
739 uint32_t (*readfn)(void *opaque),
740 void (*writefn)(void *opaque, uint32_t value), void *opaque)
741{
742 if (!port) {
743 printf("%s: no such SSP\n", __FUNCTION__);
744 exit(-1);
745 }
746
747 port->opaque = opaque;
748 port->readfn = readfn;
749 port->writefn = writefn;
750}
751
752static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
753 pxa2xx_ssp_read,
754 pxa2xx_ssp_read,
755 pxa2xx_ssp_read,
756};
757
758static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
759 pxa2xx_ssp_write,
760 pxa2xx_ssp_write,
761 pxa2xx_ssp_write,
762};
763
764/* Real-Time Clock */
765#define RCNR 0x00 /* RTC Counter register */
766#define RTAR 0x04 /* RTC Alarm register */
767#define RTSR 0x08 /* RTC Status register */
768#define RTTR 0x0c /* RTC Timer Trim register */
769#define RDCR 0x10 /* RTC Day Counter register */
770#define RYCR 0x14 /* RTC Year Counter register */
771#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
772#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
773#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
774#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
775#define SWCR 0x28 /* RTC Stopwatch Counter register */
776#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
777#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
778#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
779#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
780
781static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
782{
783 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
784}
785
786static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
787{
788 int64_t rt = qemu_get_clock(rt_clock);
789 s->last_rcnr += ((rt - s->last_hz) << 15) /
790 (1000 * ((s->rttr & 0xffff) + 1));
791 s->last_rdcr += ((rt - s->last_hz) << 15) /
792 (1000 * ((s->rttr & 0xffff) + 1));
793 s->last_hz = rt;
794}
795
796static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
797{
798 int64_t rt = qemu_get_clock(rt_clock);
799 if (s->rtsr & (1 << 12))
800 s->last_swcr += (rt - s->last_sw) / 10;
801 s->last_sw = rt;
802}
803
804static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
805{
806 int64_t rt = qemu_get_clock(rt_clock);
807 if (s->rtsr & (1 << 15))
808 s->last_swcr += rt - s->last_pi;
809 s->last_pi = rt;
810}
811
812static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
813 uint32_t rtsr)
814{
815 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
816 qemu_mod_timer(s->rtc_hz, s->last_hz +
817 (((s->rtar - s->last_rcnr) * 1000 *
818 ((s->rttr & 0xffff) + 1)) >> 15));
819 else
820 qemu_del_timer(s->rtc_hz);
821
822 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
823 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
824 (((s->rdar1 - s->last_rdcr) * 1000 *
825 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
826 else
827 qemu_del_timer(s->rtc_rdal1);
828
829 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
830 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
831 (((s->rdar2 - s->last_rdcr) * 1000 *
832 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
833 else
834 qemu_del_timer(s->rtc_rdal2);
835
836 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
837 qemu_mod_timer(s->rtc_swal1, s->last_sw +
838 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
839 else
840 qemu_del_timer(s->rtc_swal1);
841
842 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
843 qemu_mod_timer(s->rtc_swal2, s->last_sw +
844 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
845 else
846 qemu_del_timer(s->rtc_swal2);
847
848 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
849 qemu_mod_timer(s->rtc_pi, s->last_pi +
850 (s->piar & 0xffff) - s->last_rtcpicr);
851 else
852 qemu_del_timer(s->rtc_pi);
853}
854
855static inline void pxa2xx_rtc_hz_tick(void *opaque)
856{
857 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
858 s->rtsr |= (1 << 0);
859 pxa2xx_rtc_alarm_update(s, s->rtsr);
860 pxa2xx_rtc_int_update(s);
861}
862
863static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
864{
865 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
866 s->rtsr |= (1 << 4);
867 pxa2xx_rtc_alarm_update(s, s->rtsr);
868 pxa2xx_rtc_int_update(s);
869}
870
871static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
872{
873 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
874 s->rtsr |= (1 << 6);
875 pxa2xx_rtc_alarm_update(s, s->rtsr);
876 pxa2xx_rtc_int_update(s);
877}
878
879static inline void pxa2xx_rtc_swal1_tick(void *opaque)
880{
881 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
882 s->rtsr |= (1 << 8);
883 pxa2xx_rtc_alarm_update(s, s->rtsr);
884 pxa2xx_rtc_int_update(s);
885}
886
887static inline void pxa2xx_rtc_swal2_tick(void *opaque)
888{
889 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
890 s->rtsr |= (1 << 10);
891 pxa2xx_rtc_alarm_update(s, s->rtsr);
892 pxa2xx_rtc_int_update(s);
893}
894
895static inline void pxa2xx_rtc_pi_tick(void *opaque)
896{
897 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
898 s->rtsr |= (1 << 13);
899 pxa2xx_rtc_piupdate(s);
900 s->last_rtcpicr = 0;
901 pxa2xx_rtc_alarm_update(s, s->rtsr);
902 pxa2xx_rtc_int_update(s);
903}
904
905static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
906{
907 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
908 addr -= s->rtc_base;
909
910 switch (addr) {
911 case RTTR:
912 return s->rttr;
913 case RTSR:
914 return s->rtsr;
915 case RTAR:
916 return s->rtar;
917 case RDAR1:
918 return s->rdar1;
919 case RDAR2:
920 return s->rdar2;
921 case RYAR1:
922 return s->ryar1;
923 case RYAR2:
924 return s->ryar2;
925 case SWAR1:
926 return s->swar1;
927 case SWAR2:
928 return s->swar2;
929 case PIAR:
930 return s->piar;
931 case RCNR:
932 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
933 (1000 * ((s->rttr & 0xffff) + 1));
934 case RDCR:
935 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
936 (1000 * ((s->rttr & 0xffff) + 1));
937 case RYCR:
938 return s->last_rycr;
939 case SWCR:
940 if (s->rtsr & (1 << 12))
941 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
942 else
943 return s->last_swcr;
944 default:
945 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
946 break;
947 }
948 return 0;
949}
950
951static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
952 uint32_t value)
953{
954 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
955 addr -= s->rtc_base;
956
957 switch (addr) {
958 case RTTR:
959 if (!(s->rttr & (1 << 31))) {
960 pxa2xx_rtc_hzupdate(s);
961 s->rttr = value;
962 pxa2xx_rtc_alarm_update(s, s->rtsr);
963 }
964 break;
965
966 case RTSR:
967 if ((s->rtsr ^ value) & (1 << 15))
968 pxa2xx_rtc_piupdate(s);
969
970 if ((s->rtsr ^ value) & (1 << 12))
971 pxa2xx_rtc_swupdate(s);
972
973 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
974 pxa2xx_rtc_alarm_update(s, value);
975
976 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
977 pxa2xx_rtc_int_update(s);
978 break;
979
980 case RTAR:
981 s->rtar = value;
982 pxa2xx_rtc_alarm_update(s, s->rtsr);
983 break;
984
985 case RDAR1:
986 s->rdar1 = value;
987 pxa2xx_rtc_alarm_update(s, s->rtsr);
988 break;
989
990 case RDAR2:
991 s->rdar2 = value;
992 pxa2xx_rtc_alarm_update(s, s->rtsr);
993 break;
994
995 case RYAR1:
996 s->ryar1 = value;
997 pxa2xx_rtc_alarm_update(s, s->rtsr);
998 break;
999
1000 case RYAR2:
1001 s->ryar2 = value;
1002 pxa2xx_rtc_alarm_update(s, s->rtsr);
1003 break;
1004
1005 case SWAR1:
1006 pxa2xx_rtc_swupdate(s);
1007 s->swar1 = value;
1008 s->last_swcr = 0;
1009 pxa2xx_rtc_alarm_update(s, s->rtsr);
1010 break;
1011
1012 case SWAR2:
1013 s->swar2 = value;
1014 pxa2xx_rtc_alarm_update(s, s->rtsr);
1015 break;
1016
1017 case PIAR:
1018 s->piar = value;
1019 pxa2xx_rtc_alarm_update(s, s->rtsr);
1020 break;
1021
1022 case RCNR:
1023 pxa2xx_rtc_hzupdate(s);
1024 s->last_rcnr = value;
1025 pxa2xx_rtc_alarm_update(s, s->rtsr);
1026 break;
1027
1028 case RDCR:
1029 pxa2xx_rtc_hzupdate(s);
1030 s->last_rdcr = value;
1031 pxa2xx_rtc_alarm_update(s, s->rtsr);
1032 break;
1033
1034 case RYCR:
1035 s->last_rycr = value;
1036 break;
1037
1038 case SWCR:
1039 pxa2xx_rtc_swupdate(s);
1040 s->last_swcr = value;
1041 pxa2xx_rtc_alarm_update(s, s->rtsr);
1042 break;
1043
1044 case RTCPICR:
1045 pxa2xx_rtc_piupdate(s);
1046 s->last_rtcpicr = value & 0xffff;
1047 pxa2xx_rtc_alarm_update(s, s->rtsr);
1048 break;
1049
1050 default:
1051 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1052 }
1053}
1054
1055static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s)
1056{
1057 struct tm *tm;
1058 time_t ti;
1059 int wom;
1060
1061 s->rttr = 0x7fff;
1062 s->rtsr = 0;
1063
1064 time(&ti);
1065 if (rtc_utc)
1066 tm = gmtime(&ti);
1067 else
1068 tm = localtime(&ti);
1069 wom = ((tm->tm_mday - 1) / 7) + 1;
1070
1071 s->last_rcnr = (uint32_t) ti;
1072 s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1073 (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1074 s->last_rycr = ((tm->tm_year + 1900) << 9) |
1075 ((tm->tm_mon + 1) << 5) | tm->tm_mday;
1076 s->last_swcr = (tm->tm_hour << 19) |
1077 (tm->tm_min << 13) | (tm->tm_sec << 7);
1078 s->last_rtcpicr = 0;
1079 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1080
1081 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1082 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1083 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1084 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1085 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1086 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1087}
1088
1089static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1090 pxa2xx_rtc_read,
1091 pxa2xx_rtc_read,
1092 pxa2xx_rtc_read,
1093};
1094
1095static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1096 pxa2xx_rtc_write,
1097 pxa2xx_rtc_write,
1098 pxa2xx_rtc_write,
1099};
1100
3f582262
AZ		 1101/* I2C Interface */
1102struct pxa2xx_i2c_s {
1103 i2c_slave slave;
1104 i2c_bus *bus;
1105 target_phys_addr_t base;
1106 qemu_irq irq;
1107
1108 uint16_t control;
1109 uint16_t status;
1110 uint8_t ibmr;
1111 uint8_t data;
1112};
1113
1114#define IBMR 0x80 /* I2C Bus Monitor register */
1115#define IDBR 0x88 /* I2C Data Buffer register */
1116#define ICR 0x90 /* I2C Control register */
1117#define ISR 0x98 /* I2C Status register */
1118#define ISAR 0xa0 /* I2C Slave Address register */
1119
1120static void pxa2xx_i2c_update(struct pxa2xx_i2c_s *s)
1121{
1122 uint16_t level = 0;
1123 level |= s->status & s->control & (1 << 10); /* BED */
1124 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1125 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1126 level |= s->status & (1 << 9); /* SAD */
1127 qemu_set_irq(s->irq, !!level);
1128}
1129
1130/* These are only stubs now. */
1131static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1132{
1133 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1134
1135 switch (event) {
1136 case I2C_START_SEND:
1137 s->status |= (1 << 9); /* set SAD */
1138 s->status &= ~(1 << 0); /* clear RWM */
1139 break;
1140 case I2C_START_RECV:
1141 s->status |= (1 << 9); /* set SAD */
1142 s->status |= 1 << 0; /* set RWM */
1143 break;
1144 case I2C_FINISH:
1145 s->status |= (1 << 4); /* set SSD */
1146 break;
1147 case I2C_NACK:
1148 s->status |= 1 << 1; /* set ACKNAK */
1149 break;
1150 }
1151 pxa2xx_i2c_update(s);
1152}
1153
1154static int pxa2xx_i2c_rx(i2c_slave *i2c)
1155{
1156 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1157 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1158 return 0;
1159
1160 if (s->status & (1 << 0)) { /* RWM */
1161 s->status |= 1 << 6; /* set ITE */
1162 }
1163 pxa2xx_i2c_update(s);
1164
1165 return s->data;
1166}
1167
1168static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1169{
1170 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) i2c;
1171 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1172 return 1;
1173
1174 if (!(s->status & (1 << 0))) { /* RWM */
1175 s->status |= 1 << 7; /* set IRF */
1176 s->data = data;
1177 }
1178 pxa2xx_i2c_update(s);
1179
1180 return 1;
1181}
1182
1183static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1184{
1185 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1186 addr -= s->base;
1187
1188 switch (addr) {
1189 case ICR:
1190 return s->control;
1191 case ISR:
1192 return s->status | (i2c_bus_busy(s->bus) << 2);
1193 case ISAR:
1194 return s->slave.address;
1195 case IDBR:
1196 return s->data;
1197 case IBMR:
1198 if (s->status & (1 << 2))
1199 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1200 else
1201 s->ibmr = 0;
1202 return s->ibmr;
1203 default:
1204 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1205 break;
1206 }
1207 return 0;
1208}
1209
1210static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1211 uint32_t value)
1212{
1213 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
1214 int ack;
1215 addr -= s->base;
1216
1217 switch (addr) {
1218 case ICR:
1219 s->control = value & 0xfff7;
1220 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1221 /* TODO: slave mode */
1222 if (value & (1 << 0)) { /* START condition */
1223 if (s->data & 1)
1224 s->status |= 1 << 0; /* set RWM */
1225 else
1226 s->status &= ~(1 << 0); /* clear RWM */
1227 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1228 } else {
1229 if (s->status & (1 << 0)) { /* RWM */
1230 s->data = i2c_recv(s->bus);
1231 if (value & (1 << 2)) /* ACKNAK */
1232 i2c_nack(s->bus);
1233 ack = 1;
1234 } else
1235 ack = !i2c_send(s->bus, s->data);
1236 }
1237
1238 if (value & (1 << 1)) /* STOP condition */
1239 i2c_end_transfer(s->bus);
1240
1241 if (ack) {
1242 if (value & (1 << 0)) /* START condition */
1243 s->status |= 1 << 6; /* set ITE */
1244 else
1245 if (s->status & (1 << 0)) /* RWM */
1246 s->status |= 1 << 7; /* set IRF */
1247 else
1248 s->status |= 1 << 6; /* set ITE */
1249 s->status &= ~(1 << 1); /* clear ACKNAK */
1250 } else {
1251 s->status |= 1 << 6; /* set ITE */
1252 s->status |= 1 << 10; /* set BED */
1253 s->status |= 1 << 1; /* set ACKNAK */
1254 }
1255 }
1256 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1257 if (value & (1 << 4)) /* MA */
1258 i2c_end_transfer(s->bus);
1259 pxa2xx_i2c_update(s);
1260 break;
1261
1262 case ISR:
1263 s->status &= ~(value & 0x07f0);
1264 pxa2xx_i2c_update(s);
1265 break;
1266
1267 case ISAR:
1268 i2c_set_slave_address(&s->slave, value & 0x7f);
1269 break;
1270
1271 case IDBR:
1272 s->data = value & 0xff;
1273 break;
1274
1275 default:
1276 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1277 }
1278}
1279
1280static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
1281 pxa2xx_i2c_read,
1282 pxa2xx_i2c_read,
1283 pxa2xx_i2c_read,
1284};
1285
1286static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
1287 pxa2xx_i2c_write,
1288 pxa2xx_i2c_write,
1289 pxa2xx_i2c_write,
1290};
1291
1292struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
1293 qemu_irq irq, int ioregister)
1294{
1295 int iomemtype;
1296 struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
1297 qemu_mallocz(sizeof(struct pxa2xx_i2c_s));
1298
1299 s->base = base;
1300 s->irq = irq;
1301 s->slave.event = pxa2xx_i2c_event;
1302 s->slave.recv = pxa2xx_i2c_rx;
1303 s->slave.send = pxa2xx_i2c_tx;
1304 s->bus = i2c_init_bus();
1305
1306 if (ioregister) {
1307 iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
1308 pxa2xx_i2c_writefn, s);
1309 cpu_register_physical_memory(s->base & 0xfffff000, 0xfff, iomemtype);
1310 }
1311
1312 return s;
1313}
1314
1315i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s)
1316{
1317 return s->bus;
1318}
1319
c1713132
AZ		 1320/* PXA Inter-IC Sound Controller */
1321static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1322{
1323 i2s->rx_len = 0;
1324 i2s->tx_len = 0;
1325 i2s->fifo_len = 0;
1326 i2s->clk = 0x1a;
1327 i2s->control[0] = 0x00;
1328 i2s->control[1] = 0x00;
1329 i2s->status = 0x00;
1330 i2s->mask = 0x00;
1331}
1332
1333#define SACR_TFTH(val) ((val >> 8) & 0xf)
1334#define SACR_RFTH(val) ((val >> 12) & 0xf)
1335#define SACR_DREC(val) (val & (1 << 3))
1336#define SACR_DPRL(val) (val & (1 << 4))
1337
1338static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1339{
1340 int rfs, tfs;
1341 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1342 !SACR_DREC(i2s->control[1]);
1343 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1344 i2s->enable && !SACR_DPRL(i2s->control[1]);
1345
1346 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1347 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1348
1349 i2s->status &= 0xe0;
1350 if (i2s->rx_len)
1351 i2s->status |= 1 << 1; /* RNE */
1352 if (i2s->enable)
1353 i2s->status |= 1 << 2; /* BSY */
1354 if (tfs)
1355 i2s->status |= 1 << 3; /* TFS */
1356 if (rfs)
1357 i2s->status |= 1 << 4; /* RFS */
1358 if (!(i2s->tx_len && i2s->enable))
1359 i2s->status |= i2s->fifo_len << 8; /* TFL */
1360 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1361
1362 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1363}
1364
1365#define SACR0 0x00 /* Serial Audio Global Control register */
1366#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1367#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1368#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1369#define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1370#define SADIV 0x60 /* Serial Audio Clock Divider register */
1371#define SADR 0x80 /* Serial Audio Data register */
1372
1373static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1374{
1375 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1376 addr -= s->base;
1377
1378 switch (addr) {
1379 case SACR0:
1380 return s->control[0];
1381 case SACR1:
1382 return s->control[1];
1383 case SASR0:
1384 return s->status;
1385 case SAIMR:
1386 return s->mask;
1387 case SAICR:
1388 return 0;
1389 case SADIV:
1390 return s->clk;
1391 case SADR:
1392 if (s->rx_len > 0) {
1393 s->rx_len --;
1394 pxa2xx_i2s_update(s);
1395 return s->codec_in(s->opaque);
1396 }
1397 return 0;
1398 default:
1399 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1400 break;
1401 }
1402 return 0;
1403}
1404
1405static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1406 uint32_t value)
1407{
1408 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1409 uint32_t *sample;
1410 addr -= s->base;
1411
1412 switch (addr) {
1413 case SACR0:
1414 if (value & (1 << 3)) /* RST */
1415 pxa2xx_i2s_reset(s);
1416 s->control[0] = value & 0xff3d;
1417 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1418 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1419 s->codec_out(s->opaque, *sample);
1420 s->status &= ~(1 << 7); /* I2SOFF */
1421 }
1422 if (value & (1 << 4)) /* EFWR */
1423 printf("%s: Attempt to use special function\n", __FUNCTION__);
1424 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1425 pxa2xx_i2s_update(s);
1426 break;
1427 case SACR1:
1428 s->control[1] = value & 0x0039;
1429 if (value & (1 << 5)) /* ENLBF */
1430 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1431 if (value & (1 << 4)) /* DPRL */
1432 s->fifo_len = 0;
1433 pxa2xx_i2s_update(s);
1434 break;
1435 case SAIMR:
1436 s->mask = value & 0x0078;
1437 pxa2xx_i2s_update(s);
1438 break;
1439 case SAICR:
1440 s->status &= ~(value & (3 << 5));
1441 pxa2xx_i2s_update(s);
1442 break;
1443 case SADIV:
1444 s->clk = value & 0x007f;
1445 break;
1446 case SADR:
1447 if (s->tx_len && s->enable) {
1448 s->tx_len --;
1449 pxa2xx_i2s_update(s);
1450 s->codec_out(s->opaque, value);
1451 } else if (s->fifo_len < 16) {
1452 s->fifo[s->fifo_len ++] = value;
1453 pxa2xx_i2s_update(s);
1454 }
1455 break;
1456 default:
1457 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1458 }
1459}
1460
1461static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1462 pxa2xx_i2s_read,
1463 pxa2xx_i2s_read,
1464 pxa2xx_i2s_read,
1465};
1466
1467static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1468 pxa2xx_i2s_write,
1469 pxa2xx_i2s_write,
1470 pxa2xx_i2s_write,
1471};
1472
1473static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1474{
1475 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1476 uint32_t *sample;
1477
1478 /* Signal FIFO errors */
1479 if (s->enable && s->tx_len)
1480 s->status |= 1 << 5; /* TUR */
1481 if (s->enable && s->rx_len)
1482 s->status |= 1 << 6; /* ROR */
1483
1484 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1485 * handle the cases where it makes a difference. */
1486 s->tx_len = tx - s->fifo_len;
1487 s->rx_len = rx;
1488 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1489 if (s->enable)
1490 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1491 s->codec_out(s->opaque, *sample);
1492 pxa2xx_i2s_update(s);
1493}
1494
1495static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1496 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1497{
1498 int iomemtype;
1499 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1500 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1501
1502 s->base = base;
1503 s->irq = irq;
1504 s->dma = dma;
1505 s->data_req = pxa2xx_i2s_data_req;
1506
1507 pxa2xx_i2s_reset(s);
1508
1509 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1510 pxa2xx_i2s_writefn, s);
1511 cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype);
1512
1513 return s;
1514}
1515
1516/* PXA Fast Infra-red Communications Port */
1517struct pxa2xx_fir_s {
1518 target_phys_addr_t base;
1519 qemu_irq irq;
1520 struct pxa2xx_dma_state_s *dma;
1521 int enable;
1522 CharDriverState *chr;
1523
1524 uint8_t control[3];
1525 uint8_t status[2];
1526
1527 int rx_len;
1528 int rx_start;
1529 uint8_t rx_fifo[64];
1530};
1531
1532static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1533{
1534 s->control[0] = 0x00;
1535 s->control[1] = 0x00;
1536 s->control[2] = 0x00;
1537 s->status[0] = 0x00;
1538 s->status[1] = 0x00;
1539 s->enable = 0;
1540}
1541
1542static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1543{
1544 static const int tresh[4] = { 8, 16, 32, 0 };
1545 int intr = 0;
1546 if ((s->control[0] & (1 << 4)) && /* RXE */
1547 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1548 s->status[0] |= 1 << 4; /* RFS */
1549 else
1550 s->status[0] &= ~(1 << 4); /* RFS */
1551 if (s->control[0] & (1 << 3)) /* TXE */
1552 s->status[0] |= 1 << 3; /* TFS */
1553 else
1554 s->status[0] &= ~(1 << 3); /* TFS */
1555 if (s->rx_len)
1556 s->status[1] |= 1 << 2; /* RNE */
1557 else
1558 s->status[1] &= ~(1 << 2); /* RNE */
1559 if (s->control[0] & (1 << 4)) /* RXE */
1560 s->status[1] |= 1 << 0; /* RSY */
1561 else
1562 s->status[1] &= ~(1 << 0); /* RSY */
1563
1564 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1565 (s->status[0] & (1 << 4)); /* RFS */
1566 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1567 (s->status[0] & (1 << 3)); /* TFS */
1568 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1569 (s->status[0] & (1 << 6)); /* EOC */
1570 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1571 (s->status[0] & (1 << 1)); /* TUR */
1572 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1573
1574 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1575 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1576
1577 qemu_set_irq(s->irq, intr && s->enable);
1578}
1579
1580#define ICCR0 0x00 /* FICP Control register 0 */
1581#define ICCR1 0x04 /* FICP Control register 1 */
1582#define ICCR2 0x08 /* FICP Control register 2 */
1583#define ICDR 0x0c /* FICP Data register */
1584#define ICSR0 0x14 /* FICP Status register 0 */
1585#define ICSR1 0x18 /* FICP Status register 1 */
1586#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1587
1588static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1589{
1590 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1591 uint8_t ret;
1592 addr -= s->base;
1593
1594 switch (addr) {
1595 case ICCR0:
1596 return s->control[0];
1597 case ICCR1:
1598 return s->control[1];
1599 case ICCR2:
1600 return s->control[2];
1601 case ICDR:
1602 s->status[0] &= ~0x01;
1603 s->status[1] &= ~0x72;
1604 if (s->rx_len) {
1605 s->rx_len --;
1606 ret = s->rx_fifo[s->rx_start ++];
1607 s->rx_start &= 63;
1608 pxa2xx_fir_update(s);
1609 return ret;
1610 }
1611 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1612 break;
1613 case ICSR0:
1614 return s->status[0];
1615 case ICSR1:
1616 return s->status[1] | (1 << 3); /* TNF */
1617 case ICFOR:
1618 return s->rx_len;
1619 default:
1620 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1621 break;
1622 }
1623 return 0;
1624}
1625
1626static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1627 uint32_t value)
1628{
1629 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1630 uint8_t ch;
1631 addr -= s->base;
1632
1633 switch (addr) {
1634 case ICCR0:
1635 s->control[0] = value;
1636 if (!(value & (1 << 4))) /* RXE */
1637 s->rx_len = s->rx_start = 0;
1638 if (!(value & (1 << 3))) /* TXE */
1639 /* Nop */;
1640 s->enable = value & 1; /* ITR */
1641 if (!s->enable)
1642 s->status[0] = 0;
1643 pxa2xx_fir_update(s);
1644 break;
1645 case ICCR1:
1646 s->control[1] = value;
1647 break;
1648 case ICCR2:
1649 s->control[2] = value & 0x3f;
1650 pxa2xx_fir_update(s);
1651 break;
1652 case ICDR:
1653 if (s->control[2] & (1 << 2)) /* TXP */
1654 ch = value;
1655 else
1656 ch = ~value;
1657 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1658 qemu_chr_write(s->chr, &ch, 1);
1659 break;
1660 case ICSR0:
1661 s->status[0] &= ~(value & 0x66);
1662 pxa2xx_fir_update(s);
1663 break;
1664 case ICFOR:
1665 break;
1666 default:
1667 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1668 }
1669}
1670
1671static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1672 pxa2xx_fir_read,
1673 pxa2xx_fir_read,
1674 pxa2xx_fir_read,
1675};
1676
1677static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1678 pxa2xx_fir_write,
1679 pxa2xx_fir_write,
1680 pxa2xx_fir_write,
1681};
1682
1683static int pxa2xx_fir_is_empty(void *opaque)
1684{
1685 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1686 return (s->rx_len < 64);
1687}
1688
1689static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1690{
1691 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1692 if (!(s->control[0] & (1 << 4))) /* RXE */
1693 return;
1694
1695 while (size --) {
1696 s->status[1] |= 1 << 4; /* EOF */
1697 if (s->rx_len >= 64) {
1698 s->status[1] |= 1 << 6; /* ROR */
1699 break;
1700 }
1701
1702 if (s->control[2] & (1 << 3)) /* RXP */
1703 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1704 else
1705 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1706 }
1707
1708 pxa2xx_fir_update(s);
1709}
1710
1711static void pxa2xx_fir_event(void *opaque, int event)
1712{
1713}
1714
1715static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1716 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1717 CharDriverState *chr)
1718{
1719 int iomemtype;
1720 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1721 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1722
1723 s->base = base;
1724 s->irq = irq;
1725 s->dma = dma;
1726 s->chr = chr;
1727
1728 pxa2xx_fir_reset(s);
1729
1730 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1731 pxa2xx_fir_writefn, s);
1732 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1733
1734 if (chr)
1735 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1736 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1737
1738 return s;
1739}
1740
1741void pxa2xx_reset(int line, int level, void *opaque)
1742{
1743 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1744 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
1745 cpu_reset(s->env);
1746 /* TODO: reset peripherals */
1747 }
1748}
1749
1750/* Initialise a PXA270 integrated chip (ARM based core). */
d95b2f8d
AZ		 1751struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
1752 DisplayState *ds, const char *revision)
c1713132
AZ		 1753{
1754 struct pxa2xx_state_s *s;
1755 struct pxa2xx_ssp_s *ssp;
c1713132
AZ		 1756 int iomemtype, i;
1757 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1758
4207117c
AZ		 1759 if (revision && strncmp(revision, "pxa27", 5)) {
1760 fprintf(stderr, "Machine requires a PXA27x processor.\n");
1761 exit(1);
1762 }
1763
c1713132 1764 s->env = cpu_init();
4207117c 1765 cpu_arm_set_model(s->env, revision ?: "pxa270");
c1713132 1766
d95b2f8d
AZ		 1767 /* SDRAM & Internal Memory Storage */
1768 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
1769 sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
1770 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
1771 0x40000, qemu_ram_alloc(0x40000) | IO_MEM_RAM);
1772
c1713132
AZ		 1773 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1774
1775 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1776
a171fe39 1777 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
3f582262 1778 s->pic[PXA27X_PIC_OST_4_11]);
a171fe39 1779
c1713132
AZ		 1780 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
1781
a171fe39
AZ		 1782 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1783
c1713132
AZ		 1784 for (i = 0; pxa270_serial[i].io_base; i ++)
1785 if (serial_hds[i])
1786 serial_mm_init(pxa270_serial[i].io_base, 2,
1787 s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
1788 else
1789 break;
1790 if (serial_hds[i])
1791 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1792 s->dma, serial_hds[i]);
1793
a171fe39
AZ		 1794 if (ds)
1795 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1796
c1713132
AZ		 1797 s->cm_base = 0x41300000;
1798 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1799 s->clkcfg = 0x00000009; /* Turbo mode active */
1800 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1801 pxa2xx_cm_writefn, s);
1802 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1803
1804 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1805
1806 s->mm_base = 0x48000000;
1807 s->mm_regs[MDMRS >> 2] = 0x00020002;
1808 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1809 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1810 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1811 pxa2xx_mm_writefn, s);
1812 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1813
1814 for (i = 0; pxa27x_ssp[i].io_base; i ++);
1815 s->ssp = (struct pxa2xx_ssp_s **)
1816 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1817 ssp = (struct pxa2xx_ssp_s *)
1818 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1819 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
1820 s->ssp[i] = &ssp[i];
1821 ssp[i].base = pxa27x_ssp[i].io_base;
1822 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
1823
1824 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1825 pxa2xx_ssp_writefn, &ssp[i]);
1826 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1827 }
1828
a171fe39
AZ		 1829 if (usb_enabled) {
1830 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1831 }
1832
1833 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1834 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1835
c1713132
AZ		 1836 s->rtc_base = 0x40900000;
1837 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1838 pxa2xx_rtc_writefn, s);
1839 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1840 pxa2xx_rtc_reset(s);
1841
3f582262
AZ		 1842 /* Note that PM registers are in the same page with PWRI2C registers.
1843 * As a workaround we don't map PWRI2C into memory and we expect
1844 * PM handlers to call PWRI2C handlers when appropriate. */
1845 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
1846 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
1847
c1713132
AZ		 1848 s->pm_base = 0x40f00000;
1849 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1850 pxa2xx_pm_writefn, s);
1851 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1852
1853 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1854
1855 /* GPIO1 resets the processor */
1856 /* The handler can be overriden by board-specific code */
1857 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1858 return s;
1859}
1860
1861/* Initialise a PXA255 integrated chip (ARM based core). */
d95b2f8d
AZ		 1862struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
1863 DisplayState *ds)
c1713132
AZ		 1864{
1865 struct pxa2xx_state_s *s;
1866 struct pxa2xx_ssp_s *ssp;
1867 int iomemtype, i;
1868 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1869
1870 s->env = cpu_init();
1871 cpu_arm_set_model(s->env, "pxa255");
1872
d95b2f8d 1873 /* SDRAM & Internal Memory Storage */
a07dec22
AZ		 1874 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
1875 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
1876 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
1877 qemu_ram_alloc(PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
d95b2f8d 1878
c1713132
AZ		 1879 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1880
1881 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1882
3f582262 1883 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
a171fe39 1884
3bdd58a4 1885 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
c1713132 1886
a171fe39
AZ		 1887 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1888
c1713132
AZ		 1889 for (i = 0; pxa255_serial[i].io_base; i ++)
1890 if (serial_hds[i])
1891 serial_mm_init(pxa255_serial[i].io_base, 2,
1892 s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
1893 else
1894 break;
1895 if (serial_hds[i])
1896 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1897 s->dma, serial_hds[i]);
1898
a171fe39
AZ		 1899 if (ds)
1900 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1901
c1713132
AZ		 1902 s->cm_base = 0x41300000;
1903 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1904 s->clkcfg = 0x00000009; /* Turbo mode active */
1905 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1906 pxa2xx_cm_writefn, s);
1907 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1908
1909 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1910
1911 s->mm_base = 0x48000000;
1912 s->mm_regs[MDMRS >> 2] = 0x00020002;
1913 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1914 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1915 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1916 pxa2xx_mm_writefn, s);
1917 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1918
1919 for (i = 0; pxa255_ssp[i].io_base; i ++);
1920 s->ssp = (struct pxa2xx_ssp_s **)
1921 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1922 ssp = (struct pxa2xx_ssp_s *)
1923 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1924 for (i = 0; pxa255_ssp[i].io_base; i ++) {
1925 s->ssp[i] = &ssp[i];
1926 ssp[i].base = pxa255_ssp[i].io_base;
1927 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
1928
1929 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1930 pxa2xx_ssp_writefn, &ssp[i]);
1931 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1932 }
1933
a171fe39
AZ		 1934 if (usb_enabled) {
1935 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1936 }
1937
1938 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1939 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1940
c1713132
AZ		 1941 s->rtc_base = 0x40900000;
1942 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1943 pxa2xx_rtc_writefn, s);
1944 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1945 pxa2xx_rtc_reset(s);
1946
3f582262
AZ		 1947 /* Note that PM registers are in the same page with PWRI2C registers.
1948 * As a workaround we don't map PWRI2C into memory and we expect
1949 * PM handlers to call PWRI2C handlers when appropriate. */
1950 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 1);
1951 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0);
1952
c1713132
AZ		 1953 s->pm_base = 0x40f00000;
1954 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1955 pxa2xx_pm_writefn, s);
1956 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1957
1958 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1959
1960 /* GPIO1 resets the processor */
1961 /* The handler can be overriden by board-specific code */
1962 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1963 return s;
1964}
Qemu copy for testing