[qemu.git] / hw / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "sysbus.h"
#include "pxa.h"

#define PXA2XX_GPIO_BANKS	4

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    SysBusDevice busdev;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    CPUState *cpu_env;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gpsr[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    bank = line >> 5;
    mask = 1 << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ffs(diff) - 1;
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        printf("%s: Read from a write-only register " REG_FMT "\n",
                        __FUNCTION__, offset);
        return s->gpsr[bank];	/* Return last written value.  */

    case GPCR:		/* GPIO Pin-Output Clear registers */
        printf("%s: Read from a write-only register " REG_FMT "\n",
                        __FUNCTION__, offset);
        return 31337;		/* Specified as unpredictable in the docs.  */

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        s->gpsr[bank] = value;
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
    pxa2xx_gpio_read,
    pxa2xx_gpio_read,
    pxa2xx_gpio_read
};

static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
    pxa2xx_gpio_write,
    pxa2xx_gpio_write,
    pxa2xx_gpio_write
};

DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, DeviceState *pic, int lines)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-gpio");
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
    sysbus_connect_irq(sysbus_from_qdev(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(sysbus_from_qdev(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(sysbus_from_qdev(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static int pxa2xx_gpio_initfn(SysBusDevice *dev)
{
    int iomemtype;
    PXA2xxGPIOInfo *s;

    s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);

    s->cpu_env = qemu_get_cpu(s->ncpu);

    qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);

    iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
                    pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq0);
    sysbus_init_irq(dev, &s->irq1);
    sysbus_init_irq(dev, &s->irqX);

    return 0;
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev));
    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField []) {
        VMSTATE_INT32(lines, PXA2xxGPIOInfo),
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_END_OF_LIST(),
    },
};

static SysBusDeviceInfo pxa2xx_gpio_info = {
    .init       = pxa2xx_gpio_initfn,
    .qdev.name  = "pxa2xx-gpio",
    .qdev.desc  = "PXA2xx GPIO controller",
    .qdev.size  = sizeof(PXA2xxGPIOInfo),
    .qdev.props = (Property []) {
        DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
        DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void pxa2xx_gpio_register(void)
{
    sysbus_register_withprop(&pxa2xx_gpio_info);
}
device_init(pxa2xx_gpio_register);
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
87ecb68b	10	#include "hw.h"
0bb53337	11	#include "sysbus.h"
87ecb68b	12	#include "pxa.h"
c1713132 AZ	13
	14	#define PXA2XX_GPIO_BANKS 4
	15
0bb53337	16	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	17	struct PXA2xxGPIOInfo {
0bb53337 DES	18	SysBusDevice busdev;
0bb53337 DES	19	qemu_irq irq0, irq1, irqX;
c1713132	20	int lines;
0bb53337	21	int ncpu;
c1713132 AZ	22	CPUState *cpu_env;
	23
	24	/* XXX: GNU C vectors are more suitable */
	25	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	26	uint32_t olevel[PXA2XX_GPIO_BANKS];
	27	uint32_t dir[PXA2XX_GPIO_BANKS];
	28	uint32_t rising[PXA2XX_GPIO_BANKS];
	29	uint32_t falling[PXA2XX_GPIO_BANKS];
	30	uint32_t status[PXA2XX_GPIO_BANKS];
2b76bdc9	31	uint32_t gpsr[PXA2XX_GPIO_BANKS];
c1713132 AZ	32	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	33
	34	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	35	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	36	qemu_irq read_notify;
c1713132 AZ	37	};
	38
	39	static struct {
	40	enum {
	41	GPIO_NONE,
	42	GPLR,
	43	GPSR,
	44	GPCR,
	45	GPDR,
	46	GRER,
	47	GFER,
	48	GEDR,
	49	GAFR_L,
	50	GAFR_U,
	51	} reg;
	52	int bank;
	53	} pxa2xx_gpio_regs[0x200] = {
	54	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	55	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	56	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	57
	58	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	59	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	60	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	61	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	62	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	63	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	64	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	65	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	66	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	67	};
	68
bc24a225	69	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	70	{
c1713132 AZ	71	if (s->status[0] & (1 << 0))
0bb53337	72	qemu_irq_raise(s->irq0);
c1713132	73	else
0bb53337	74	qemu_irq_lower(s->irq0);
c1713132 AZ	75
c1713132 AZ	76	if (s->status[0] & (1 << 1))
0bb53337	77	qemu_irq_raise(s->irq1);
c1713132	78	else
0bb53337	79	qemu_irq_lower(s->irq1);
c1713132 AZ	80
c1713132 AZ	81	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	82	qemu_irq_raise(s->irqX);
c1713132	83	else
0bb53337	84	qemu_irq_lower(s->irqX);
c1713132 AZ	85	}
	86
	87	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	88	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	89	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	90	};
	91
38641a52	92	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	93	{
bc24a225	94	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	95	int bank;
	96	uint32_t mask;
	97
	98	if (line >= s->lines) {
	99	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	100	return;
	101	}
	102
	103	bank = line >> 5;
	104	mask = 1 << (line & 31);
	105
	106	if (level) {
	107	s->status[bank] \|= s->rising[bank] & mask &
	108	~s->ilevel[bank] & ~s->dir[bank];
	109	s->ilevel[bank] \|= mask;
	110	} else {
	111	s->status[bank] \|= s->falling[bank] & mask &
	112	s->ilevel[bank] & ~s->dir[bank];
	113	s->ilevel[bank] &= ~mask;
	114	}
	115
	116	if (s->status[bank] & mask)
	117	pxa2xx_gpio_irq_update(s);
	118
	119	/* Wake-up GPIOs */
	120	if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
	121	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
	122	}
	123
bc24a225	124	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	125	uint32_t level, diff;
	126	int i, bit, line;
	127	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	128	level = s->olevel[i] & s->dir[i];
	129
	130	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
	131	bit = ffs(diff) - 1;
	132	line = bit + 32 * i;
38641a52	133	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	134	}
	135
	136	s->prev_level[i] = level;
	137	}
	138	}
	139
c227f099	140	static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
c1713132	141	{
bc24a225	142	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	143	uint32_t ret;
c1713132 AZ	144	int bank;
c1713132 AZ	145	if (offset >= 0x200)
	146	return 0;
	147
	148	bank = pxa2xx_gpio_regs[offset].bank;
	149	switch (pxa2xx_gpio_regs[offset].reg) {
	150	case GPDR: /* GPIO Pin-Direction registers */
	151	return s->dir[bank];
	152
2b76bdc9 AZ	153	case GPSR: /* GPIO Pin-Output Set registers */
	154	printf("%s: Read from a write-only register " REG_FMT "\n",
	155	__FUNCTION__, offset);
	156	return s->gpsr[bank]; /* Return last written value. */
	157
e1dad5a6 AZ	158	case GPCR: /* GPIO Pin-Output Clear registers */
	159	printf("%s: Read from a write-only register " REG_FMT "\n",
	160	__FUNCTION__, offset);
	161	return 31337; /* Specified as unpredictable in the docs. */
	162
c1713132 AZ	163	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	164	return s->rising[bank];
	165
	166	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	167	return s->falling[bank];
	168
	169	case GAFR_L: /* GPIO Alternate Function registers */
	170	return s->gafr[bank * 2];
	171
	172	case GAFR_U: /* GPIO Alternate Function registers */
	173	return s->gafr[bank * 2 + 1];
	174
	175	case GPLR: /* GPIO Pin-Level registers */
	176	ret = (s->olevel[bank] & s->dir[bank]) \|
	177	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	178	qemu_irq_raise(s->read_notify);
c1713132 AZ	179	return ret;
	180
	181	case GEDR: /* GPIO Edge Detect Status registers */
	182	return s->status[bank];
	183
	184	default:
2ac71179	185	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	186	}
	187
	188	return 0;
	189	}
	190
	191	static void pxa2xx_gpio_write(void *opaque,
c227f099	192	target_phys_addr_t offset, uint32_t value)
c1713132	193	{
bc24a225	194	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	195	int bank;
c1713132 AZ	196	if (offset >= 0x200)
	197	return;
	198
	199	bank = pxa2xx_gpio_regs[offset].bank;
	200	switch (pxa2xx_gpio_regs[offset].reg) {
	201	case GPDR: /* GPIO Pin-Direction registers */
	202	s->dir[bank] = value;
	203	pxa2xx_gpio_handler_update(s);
	204	break;
	205
	206	case GPSR: /* GPIO Pin-Output Set registers */
	207	s->olevel[bank] \|= value;
	208	pxa2xx_gpio_handler_update(s);
2b76bdc9	209	s->gpsr[bank] = value;
c1713132 AZ	210	break;
	211
	212	case GPCR: /* GPIO Pin-Output Clear registers */
	213	s->olevel[bank] &= ~value;
	214	pxa2xx_gpio_handler_update(s);
	215	break;
	216
	217	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	218	s->rising[bank] = value;
	219	break;
	220
	221	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	222	s->falling[bank] = value;
	223	break;
	224
	225	case GAFR_L: /* GPIO Alternate Function registers */
	226	s->gafr[bank * 2] = value;
	227	break;
	228
	229	case GAFR_U: /* GPIO Alternate Function registers */
	230	s->gafr[bank * 2 + 1] = value;
	231	break;
	232
	233	case GEDR: /* GPIO Edge Detect Status registers */
	234	s->status[bank] &= ~value;
	235	pxa2xx_gpio_irq_update(s);
	236	break;
	237
	238	default:
2ac71179	239	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
c1713132 AZ	240	}
	241	}
	242
d60efc6b	243	static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
c1713132 AZ	244	pxa2xx_gpio_read,
	245	pxa2xx_gpio_read,
	246	pxa2xx_gpio_read
	247	};
	248
d60efc6b	249	static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
c1713132 AZ	250	pxa2xx_gpio_write,
	251	pxa2xx_gpio_write,
	252	pxa2xx_gpio_write
	253	};
	254
0bb53337	255	DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
e1f8c729	256	CPUState env, DeviceState pic, int lines)
aa941b94	257	{
0bb53337	258	DeviceState *dev;
aa941b94	259
0bb53337 DES	260	dev = qdev_create(NULL, "pxa2xx-gpio");
	261	qdev_prop_set_int32(dev, "lines", lines);
	262	qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
	263	qdev_init_nofail(dev);
aa941b94	264
0bb53337	265	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
e1f8c729 DES	266	sysbus_connect_irq(sysbus_from_qdev(dev), 0,
	267	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
	268	sysbus_connect_irq(sysbus_from_qdev(dev), 1,
	269	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
	270	sysbus_connect_irq(sysbus_from_qdev(dev), 2,
	271	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	272
0bb53337	273	return dev;
aa941b94 AZ	274	}
aa941b94 AZ	275
0bb53337	276	static int pxa2xx_gpio_initfn(SysBusDevice *dev)
c1713132 AZ	277	{
c1713132 AZ	278	int iomemtype;
bc24a225	279	PXA2xxGPIOInfo *s;
c1713132	280
0bb53337	281	s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
c1713132	282
0bb53337	283	s->cpu_env = qemu_get_cpu(s->ncpu);
c1713132	284
0bb53337 DES	285	qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
0bb53337 DES	286	qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
c1713132	287
0bb53337 DES	288	iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
0bb53337 DES	289	pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
38641a52	290
0bb53337 DES	291	sysbus_init_mmio(dev, 0x1000, iomemtype);
	292	sysbus_init_irq(dev, &s->irq0);
	293	sysbus_init_irq(dev, &s->irq1);
	294	sysbus_init_irq(dev, &s->irqX);
c1713132	295
0bb53337	296	return 0;
c1713132 AZ	297	}
	298
	299	/*
	300	* Registers a callback to notify on GPLR reads. This normally
	301	* shouldn't be needed but it is used for the hack on Spitz machines.
	302	*/
0bb53337	303	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	304	{
0bb53337	305	PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev));
c1713132	306	s->read_notify = handler;
c1713132	307	}
0bb53337 DES	308
	309	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	310	.name = "pxa2xx-gpio",
	311	.version_id = 1,
	312	.minimum_version_id = 1,
	313	.minimum_version_id_old = 1,
	314	.fields = (VMStateField []) {
	315	VMSTATE_INT32(lines, PXA2xxGPIOInfo),
	316	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	317	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	318	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	319	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	320	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	321	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	322	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
	323	VMSTATE_END_OF_LIST(),
	324	},
	325	};
	326
	327	static SysBusDeviceInfo pxa2xx_gpio_info = {
	328	.init = pxa2xx_gpio_initfn,
	329	.qdev.name = "pxa2xx-gpio",
	330	.qdev.desc = "PXA2xx GPIO controller",
	331	.qdev.size = sizeof(PXA2xxGPIOInfo),
	332	.qdev.props = (Property []) {
	333	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	334	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	335	DEFINE_PROP_END_OF_LIST(),
	336	}
	337	};
	338
	339	static void pxa2xx_gpio_register(void)
	340	{
	341	sysbus_register_withprop(&pxa2xx_gpio_info);
	342	}
	343	device_init(pxa2xx_gpio_register);