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c1713132 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 GPIO controller emulation. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
7 | * This code is licensed under the GPL. | |
8 | */ | |
9 | ||
10 | #include "vl.h" | |
11 | ||
12 | #define PXA2XX_GPIO_BANKS 4 | |
13 | ||
14 | struct pxa2xx_gpio_info_s { | |
15 | target_phys_addr_t base; | |
16 | qemu_irq *pic; | |
17 | int lines; | |
18 | CPUState *cpu_env; | |
19 | ||
20 | /* XXX: GNU C vectors are more suitable */ | |
21 | uint32_t ilevel[PXA2XX_GPIO_BANKS]; | |
22 | uint32_t olevel[PXA2XX_GPIO_BANKS]; | |
23 | uint32_t dir[PXA2XX_GPIO_BANKS]; | |
24 | uint32_t rising[PXA2XX_GPIO_BANKS]; | |
25 | uint32_t falling[PXA2XX_GPIO_BANKS]; | |
26 | uint32_t status[PXA2XX_GPIO_BANKS]; | |
2b76bdc9 | 27 | uint32_t gpsr[PXA2XX_GPIO_BANKS]; |
c1713132 AZ |
28 | uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; |
29 | ||
30 | uint32_t prev_level[PXA2XX_GPIO_BANKS]; | |
31 | struct { | |
32 | gpio_handler_t fn; | |
33 | void *opaque; | |
34 | } handler[PXA2XX_GPIO_BANKS * 32]; | |
35 | ||
36 | void (*read_notify)(void *opaque); | |
37 | void *opaque; | |
38 | }; | |
39 | ||
40 | static struct { | |
41 | enum { | |
42 | GPIO_NONE, | |
43 | GPLR, | |
44 | GPSR, | |
45 | GPCR, | |
46 | GPDR, | |
47 | GRER, | |
48 | GFER, | |
49 | GEDR, | |
50 | GAFR_L, | |
51 | GAFR_U, | |
52 | } reg; | |
53 | int bank; | |
54 | } pxa2xx_gpio_regs[0x200] = { | |
55 | [0 ... 0x1ff] = { GPIO_NONE, 0 }, | |
56 | #define PXA2XX_REG(reg, a0, a1, a2, a3) \ | |
5fafdf24 | 57 | [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, |
c1713132 AZ |
58 | |
59 | PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) | |
60 | PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) | |
61 | PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) | |
62 | PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) | |
63 | PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) | |
64 | PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) | |
65 | PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) | |
66 | PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) | |
67 | PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) | |
68 | }; | |
69 | ||
70 | static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s) | |
71 | { | |
72 | if (s->status[0] & (1 << 0)) | |
73 | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]); | |
74 | else | |
75 | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]); | |
76 | ||
77 | if (s->status[0] & (1 << 1)) | |
78 | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]); | |
79 | else | |
80 | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]); | |
81 | ||
82 | if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) | |
83 | qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]); | |
84 | else | |
85 | qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]); | |
86 | } | |
87 | ||
88 | /* Bitmap of pins used as standby and sleep wake-up sources. */ | |
89 | const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { | |
90 | 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, | |
91 | }; | |
92 | ||
93 | void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level) | |
94 | { | |
95 | int bank; | |
96 | uint32_t mask; | |
97 | ||
98 | if (line >= s->lines) { | |
99 | printf("%s: No GPIO pin %i\n", __FUNCTION__, line); | |
100 | return; | |
101 | } | |
102 | ||
103 | bank = line >> 5; | |
104 | mask = 1 << (line & 31); | |
105 | ||
106 | if (level) { | |
107 | s->status[bank] |= s->rising[bank] & mask & | |
108 | ~s->ilevel[bank] & ~s->dir[bank]; | |
109 | s->ilevel[bank] |= mask; | |
110 | } else { | |
111 | s->status[bank] |= s->falling[bank] & mask & | |
112 | s->ilevel[bank] & ~s->dir[bank]; | |
113 | s->ilevel[bank] &= ~mask; | |
114 | } | |
115 | ||
116 | if (s->status[bank] & mask) | |
117 | pxa2xx_gpio_irq_update(s); | |
118 | ||
119 | /* Wake-up GPIOs */ | |
120 | if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) | |
121 | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB); | |
122 | } | |
123 | ||
124 | static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) { | |
125 | uint32_t level, diff; | |
126 | int i, bit, line; | |
127 | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { | |
128 | level = s->olevel[i] & s->dir[i]; | |
129 | ||
130 | for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { | |
131 | bit = ffs(diff) - 1; | |
132 | line = bit + 32 * i; | |
133 | if (s->handler[line].fn) | |
134 | s->handler[line].fn(line, (level >> bit) & 1, | |
135 | s->handler[line].opaque); | |
136 | } | |
137 | ||
138 | s->prev_level[i] = level; | |
139 | } | |
140 | } | |
141 | ||
142 | static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) | |
143 | { | |
144 | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; | |
145 | uint32_t ret; | |
146 | int bank; | |
147 | offset -= s->base; | |
148 | if (offset >= 0x200) | |
149 | return 0; | |
150 | ||
151 | bank = pxa2xx_gpio_regs[offset].bank; | |
152 | switch (pxa2xx_gpio_regs[offset].reg) { | |
153 | case GPDR: /* GPIO Pin-Direction registers */ | |
154 | return s->dir[bank]; | |
155 | ||
2b76bdc9 AZ |
156 | case GPSR: /* GPIO Pin-Output Set registers */ |
157 | printf("%s: Read from a write-only register " REG_FMT "\n", | |
158 | __FUNCTION__, offset); | |
159 | return s->gpsr[bank]; /* Return last written value. */ | |
160 | ||
c1713132 AZ |
161 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
162 | return s->rising[bank]; | |
163 | ||
164 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ | |
165 | return s->falling[bank]; | |
166 | ||
167 | case GAFR_L: /* GPIO Alternate Function registers */ | |
168 | return s->gafr[bank * 2]; | |
169 | ||
170 | case GAFR_U: /* GPIO Alternate Function registers */ | |
171 | return s->gafr[bank * 2 + 1]; | |
172 | ||
173 | case GPLR: /* GPIO Pin-Level registers */ | |
174 | ret = (s->olevel[bank] & s->dir[bank]) | | |
175 | (s->ilevel[bank] & ~s->dir[bank]); | |
176 | if (s->read_notify) | |
177 | s->read_notify(s->opaque); | |
178 | return ret; | |
179 | ||
180 | case GEDR: /* GPIO Edge Detect Status registers */ | |
181 | return s->status[bank]; | |
182 | ||
183 | default: | |
184 | cpu_abort(cpu_single_env, | |
185 | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); | |
186 | } | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static void pxa2xx_gpio_write(void *opaque, | |
192 | target_phys_addr_t offset, uint32_t value) | |
193 | { | |
194 | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; | |
195 | int bank; | |
196 | offset -= s->base; | |
197 | if (offset >= 0x200) | |
198 | return; | |
199 | ||
200 | bank = pxa2xx_gpio_regs[offset].bank; | |
201 | switch (pxa2xx_gpio_regs[offset].reg) { | |
202 | case GPDR: /* GPIO Pin-Direction registers */ | |
203 | s->dir[bank] = value; | |
204 | pxa2xx_gpio_handler_update(s); | |
205 | break; | |
206 | ||
207 | case GPSR: /* GPIO Pin-Output Set registers */ | |
208 | s->olevel[bank] |= value; | |
209 | pxa2xx_gpio_handler_update(s); | |
2b76bdc9 | 210 | s->gpsr[bank] = value; |
c1713132 AZ |
211 | break; |
212 | ||
213 | case GPCR: /* GPIO Pin-Output Clear registers */ | |
214 | s->olevel[bank] &= ~value; | |
215 | pxa2xx_gpio_handler_update(s); | |
216 | break; | |
217 | ||
218 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ | |
219 | s->rising[bank] = value; | |
220 | break; | |
221 | ||
222 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ | |
223 | s->falling[bank] = value; | |
224 | break; | |
225 | ||
226 | case GAFR_L: /* GPIO Alternate Function registers */ | |
227 | s->gafr[bank * 2] = value; | |
228 | break; | |
229 | ||
230 | case GAFR_U: /* GPIO Alternate Function registers */ | |
231 | s->gafr[bank * 2 + 1] = value; | |
232 | break; | |
233 | ||
234 | case GEDR: /* GPIO Edge Detect Status registers */ | |
235 | s->status[bank] &= ~value; | |
236 | pxa2xx_gpio_irq_update(s); | |
237 | break; | |
238 | ||
239 | default: | |
240 | cpu_abort(cpu_single_env, | |
241 | "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); | |
242 | } | |
243 | } | |
244 | ||
245 | static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = { | |
246 | pxa2xx_gpio_read, | |
247 | pxa2xx_gpio_read, | |
248 | pxa2xx_gpio_read | |
249 | }; | |
250 | ||
251 | static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = { | |
252 | pxa2xx_gpio_write, | |
253 | pxa2xx_gpio_write, | |
254 | pxa2xx_gpio_write | |
255 | }; | |
256 | ||
aa941b94 AZ |
257 | static void pxa2xx_gpio_save(QEMUFile *f, void *opaque) |
258 | { | |
259 | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; | |
260 | int i; | |
261 | ||
262 | qemu_put_be32(f, s->lines); | |
263 | ||
264 | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { | |
265 | qemu_put_be32s(f, &s->ilevel[i]); | |
266 | qemu_put_be32s(f, &s->olevel[i]); | |
267 | qemu_put_be32s(f, &s->dir[i]); | |
268 | qemu_put_be32s(f, &s->rising[i]); | |
269 | qemu_put_be32s(f, &s->falling[i]); | |
270 | qemu_put_be32s(f, &s->status[i]); | |
271 | qemu_put_be32s(f, &s->gafr[i * 2 + 0]); | |
272 | qemu_put_be32s(f, &s->gafr[i * 2 + 1]); | |
273 | ||
274 | qemu_put_be32s(f, &s->prev_level[i]); | |
275 | } | |
276 | } | |
277 | ||
278 | static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id) | |
279 | { | |
280 | struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; | |
281 | int i; | |
282 | ||
283 | if (qemu_get_be32(f) != s->lines) | |
284 | return -EINVAL; | |
285 | ||
286 | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { | |
287 | qemu_get_be32s(f, &s->ilevel[i]); | |
288 | qemu_get_be32s(f, &s->olevel[i]); | |
289 | qemu_get_be32s(f, &s->dir[i]); | |
290 | qemu_get_be32s(f, &s->rising[i]); | |
291 | qemu_get_be32s(f, &s->falling[i]); | |
292 | qemu_get_be32s(f, &s->status[i]); | |
293 | qemu_get_be32s(f, &s->gafr[i * 2 + 0]); | |
294 | qemu_get_be32s(f, &s->gafr[i * 2 + 1]); | |
295 | ||
296 | qemu_get_be32s(f, &s->prev_level[i]); | |
297 | } | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
c1713132 AZ |
302 | struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, |
303 | CPUState *env, qemu_irq *pic, int lines) | |
304 | { | |
305 | int iomemtype; | |
306 | struct pxa2xx_gpio_info_s *s; | |
307 | ||
308 | s = (struct pxa2xx_gpio_info_s *) | |
309 | qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s)); | |
310 | memset(s, 0, sizeof(struct pxa2xx_gpio_info_s)); | |
311 | s->base = base; | |
312 | s->pic = pic; | |
313 | s->lines = lines; | |
314 | s->cpu_env = env; | |
315 | ||
316 | iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn, | |
317 | pxa2xx_gpio_writefn, s); | |
187337f8 | 318 | cpu_register_physical_memory(base, 0x00001000, iomemtype); |
c1713132 | 319 | |
aa941b94 AZ |
320 | register_savevm("pxa2xx_gpio", 0, 0, |
321 | pxa2xx_gpio_save, pxa2xx_gpio_load, s); | |
322 | ||
c1713132 AZ |
323 | return s; |
324 | } | |
325 | ||
326 | void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line, | |
327 | gpio_handler_t handler, void *opaque) { | |
328 | if (line >= s->lines) { | |
329 | printf("%s: No GPIO pin %i\n", __FUNCTION__, line); | |
330 | return; | |
331 | } | |
332 | ||
333 | s->handler[line].fn = handler; | |
334 | s->handler[line].opaque = opaque; | |
335 | } | |
336 | ||
337 | /* | |
338 | * Registers a callback to notify on GPLR reads. This normally | |
339 | * shouldn't be needed but it is used for the hack on Spitz machines. | |
340 | */ | |
341 | void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, | |
342 | void (*handler)(void *opaque), void *opaque) { | |
343 | s->read_notify = handler; | |
344 | s->opaque = opaque; | |
345 | } |