[qemu.git] / hw / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "pxa.h"

#define PXA2XX_GPIO_BANKS	4

struct pxa2xx_gpio_info_s {
    target_phys_addr_t base;
    qemu_irq *pic;
    int lines;
    CPUState *cpu_env;
    qemu_irq *in;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gpsr[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
    else
        qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
    else
        qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
    else
        qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    bank = line >> 5;
    mask = 1 << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
}

static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ffs(diff) - 1;
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    uint32_t ret;
    int bank;
    offset -= s->base;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        printf("%s: Read from a write-only register " REG_FMT "\n",
                        __FUNCTION__, offset);
        return s->gpsr[bank];	/* Return last written value.  */

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        cpu_abort(cpu_single_env,
                "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque,
                target_phys_addr_t offset, uint32_t value)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    int bank;
    offset -= s->base;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        s->gpsr[bank] = value;
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        cpu_abort(cpu_single_env,
                "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
    pxa2xx_gpio_read,
    pxa2xx_gpio_read,
    pxa2xx_gpio_read
};

static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
    pxa2xx_gpio_write,
    pxa2xx_gpio_write,
    pxa2xx_gpio_write
};

static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    int i;

    qemu_put_be32(f, s->lines);

    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        qemu_put_be32s(f, &s->ilevel[i]);
        qemu_put_be32s(f, &s->olevel[i]);
        qemu_put_be32s(f, &s->dir[i]);
        qemu_put_be32s(f, &s->rising[i]);
        qemu_put_be32s(f, &s->falling[i]);
        qemu_put_be32s(f, &s->status[i]);
        qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
        qemu_put_be32s(f, &s->gafr[i * 2 + 1]);

        qemu_put_be32s(f, &s->prev_level[i]);
    }
}

static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
{
    struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
    int i;

    if (qemu_get_be32(f) != s->lines)
        return -EINVAL;

    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        qemu_get_be32s(f, &s->ilevel[i]);
        qemu_get_be32s(f, &s->olevel[i]);
        qemu_get_be32s(f, &s->dir[i]);
        qemu_get_be32s(f, &s->rising[i]);
        qemu_get_be32s(f, &s->falling[i]);
        qemu_get_be32s(f, &s->status[i]);
        qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
        qemu_get_be32s(f, &s->gafr[i * 2 + 1]);

        qemu_get_be32s(f, &s->prev_level[i]);
    }

    return 0;
}

struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, qemu_irq *pic, int lines)
{
    int iomemtype;
    struct pxa2xx_gpio_info_s *s;

    s = (struct pxa2xx_gpio_info_s *)
            qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
    memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
    s->base = base;
    s->pic = pic;
    s->lines = lines;
    s->cpu_env = env;
    s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);

    iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
                    pxa2xx_gpio_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    register_savevm("pxa2xx_gpio", 0, 0,
                    pxa2xx_gpio_save, pxa2xx_gpio_load, s);

    return s;
}

qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s)
{
    return s->in;
}

void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
                int line, qemu_irq handler)
{
    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    s->handler[line] = handler;
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
{
    s->read_notify = handler;
}
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
87ecb68b PB	10	#include "hw.h"
87ecb68b PB	11	#include "pxa.h"
c1713132 AZ	12
	13	#define PXA2XX_GPIO_BANKS 4
	14
	15	struct pxa2xx_gpio_info_s {
	16	target_phys_addr_t base;
	17	qemu_irq *pic;
	18	int lines;
	19	CPUState *cpu_env;
38641a52	20	qemu_irq *in;
c1713132 AZ	21
	22	/* XXX: GNU C vectors are more suitable */
	23	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	24	uint32_t olevel[PXA2XX_GPIO_BANKS];
	25	uint32_t dir[PXA2XX_GPIO_BANKS];
	26	uint32_t rising[PXA2XX_GPIO_BANKS];
	27	uint32_t falling[PXA2XX_GPIO_BANKS];
	28	uint32_t status[PXA2XX_GPIO_BANKS];
2b76bdc9	29	uint32_t gpsr[PXA2XX_GPIO_BANKS];
c1713132 AZ	30	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	31
	32	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	33	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	34	qemu_irq read_notify;
c1713132 AZ	35	};
	36
	37	static struct {
	38	enum {
	39	GPIO_NONE,
	40	GPLR,
	41	GPSR,
	42	GPCR,
	43	GPDR,
	44	GRER,
	45	GFER,
	46	GEDR,
	47	GAFR_L,
	48	GAFR_U,
	49	} reg;
	50	int bank;
	51	} pxa2xx_gpio_regs[0x200] = {
	52	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	53	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	54	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	55
	56	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	57	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	58	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	59	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	60	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	61	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	62	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	63	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	64	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	65	};
	66
	67	static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
	68	{
	69	if (s->status[0] & (1 << 0))
	70	qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
	71	else
	72	qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
	73
	74	if (s->status[0] & (1 << 1))
	75	qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
	76	else
	77	qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
	78
	79	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
	80	qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
	81	else
	82	qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
	83	}
	84
	85	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	86	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	87	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	88	};
	89
38641a52	90	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	91	{
38641a52	92	struct pxa2xx_gpio_info_s s = (struct pxa2xx_gpio_info_s ) opaque;
c1713132 AZ	93	int bank;
	94	uint32_t mask;
	95
	96	if (line >= s->lines) {
	97	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	98	return;
	99	}
	100
	101	bank = line >> 5;
	102	mask = 1 << (line & 31);
	103
	104	if (level) {
	105	s->status[bank] \|= s->rising[bank] & mask &
	106	~s->ilevel[bank] & ~s->dir[bank];
	107	s->ilevel[bank] \|= mask;
	108	} else {
	109	s->status[bank] \|= s->falling[bank] & mask &
	110	s->ilevel[bank] & ~s->dir[bank];
	111	s->ilevel[bank] &= ~mask;
	112	}
	113
	114	if (s->status[bank] & mask)
	115	pxa2xx_gpio_irq_update(s);
	116
	117	/* Wake-up GPIOs */
	118	if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
	119	cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
	120	}
	121
	122	static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
	123	uint32_t level, diff;
	124	int i, bit, line;
	125	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	126	level = s->olevel[i] & s->dir[i];
	127
	128	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
	129	bit = ffs(diff) - 1;
	130	line = bit + 32 * i;
38641a52	131	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	132	}
	133
	134	s->prev_level[i] = level;
	135	}
	136	}
	137
	138	static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
	139	{
	140	struct pxa2xx_gpio_info_s s = (struct pxa2xx_gpio_info_s ) opaque;
	141	uint32_t ret;
	142	int bank;
	143	offset -= s->base;
	144	if (offset >= 0x200)
	145	return 0;
	146
	147	bank = pxa2xx_gpio_regs[offset].bank;
	148	switch (pxa2xx_gpio_regs[offset].reg) {
	149	case GPDR: /* GPIO Pin-Direction registers */
	150	return s->dir[bank];
	151
2b76bdc9 AZ	152	case GPSR: /* GPIO Pin-Output Set registers */
	153	printf("%s: Read from a write-only register " REG_FMT "\n",
	154	__FUNCTION__, offset);
	155	return s->gpsr[bank]; /* Return last written value. */
	156
c1713132 AZ	157	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	158	return s->rising[bank];
	159
	160	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	161	return s->falling[bank];
	162
	163	case GAFR_L: /* GPIO Alternate Function registers */
	164	return s->gafr[bank * 2];
	165
	166	case GAFR_U: /* GPIO Alternate Function registers */
	167	return s->gafr[bank * 2 + 1];
	168
	169	case GPLR: /* GPIO Pin-Level registers */
	170	ret = (s->olevel[bank] & s->dir[bank]) \|
	171	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	172	qemu_irq_raise(s->read_notify);
c1713132 AZ	173	return ret;
	174
	175	case GEDR: /* GPIO Edge Detect Status registers */
	176	return s->status[bank];
	177
	178	default:
	179	cpu_abort(cpu_single_env,
	180	"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
	181	}
	182
	183	return 0;
	184	}
	185
	186	static void pxa2xx_gpio_write(void *opaque,
	187	target_phys_addr_t offset, uint32_t value)
	188	{
	189	struct pxa2xx_gpio_info_s s = (struct pxa2xx_gpio_info_s ) opaque;
	190	int bank;
	191	offset -= s->base;
	192	if (offset >= 0x200)
	193	return;
	194
	195	bank = pxa2xx_gpio_regs[offset].bank;
	196	switch (pxa2xx_gpio_regs[offset].reg) {
	197	case GPDR: /* GPIO Pin-Direction registers */
	198	s->dir[bank] = value;
	199	pxa2xx_gpio_handler_update(s);
	200	break;
	201
	202	case GPSR: /* GPIO Pin-Output Set registers */
	203	s->olevel[bank] \|= value;
	204	pxa2xx_gpio_handler_update(s);
2b76bdc9	205	s->gpsr[bank] = value;
c1713132 AZ	206	break;
	207
	208	case GPCR: /* GPIO Pin-Output Clear registers */
	209	s->olevel[bank] &= ~value;
	210	pxa2xx_gpio_handler_update(s);
	211	break;
	212
	213	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	214	s->rising[bank] = value;
	215	break;
	216
	217	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	218	s->falling[bank] = value;
	219	break;
	220
	221	case GAFR_L: /* GPIO Alternate Function registers */
	222	s->gafr[bank * 2] = value;
	223	break;
	224
	225	case GAFR_U: /* GPIO Alternate Function registers */
	226	s->gafr[bank * 2 + 1] = value;
	227	break;
	228
	229	case GEDR: /* GPIO Edge Detect Status registers */
	230	s->status[bank] &= ~value;
	231	pxa2xx_gpio_irq_update(s);
	232	break;
	233
	234	default:
	235	cpu_abort(cpu_single_env,
	236	"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
	237	}
	238	}
	239
	240	static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
	241	pxa2xx_gpio_read,
	242	pxa2xx_gpio_read,
	243	pxa2xx_gpio_read
	244	};
	245
	246	static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
	247	pxa2xx_gpio_write,
	248	pxa2xx_gpio_write,
	249	pxa2xx_gpio_write
	250	};
	251
aa941b94 AZ	252	static void pxa2xx_gpio_save(QEMUFile f, void opaque)
	253	{
	254	struct pxa2xx_gpio_info_s s = (struct pxa2xx_gpio_info_s ) opaque;
	255	int i;
	256
	257	qemu_put_be32(f, s->lines);
	258
	259	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	260	qemu_put_be32s(f, &s->ilevel[i]);
	261	qemu_put_be32s(f, &s->olevel[i]);
	262	qemu_put_be32s(f, &s->dir[i]);
	263	qemu_put_be32s(f, &s->rising[i]);
	264	qemu_put_be32s(f, &s->falling[i]);
	265	qemu_put_be32s(f, &s->status[i]);
	266	qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
	267	qemu_put_be32s(f, &s->gafr[i * 2 + 1]);
	268
	269	qemu_put_be32s(f, &s->prev_level[i]);
	270	}
	271	}
	272
	273	static int pxa2xx_gpio_load(QEMUFile f, void opaque, int version_id)
	274	{
	275	struct pxa2xx_gpio_info_s s = (struct pxa2xx_gpio_info_s ) opaque;
	276	int i;
	277
	278	if (qemu_get_be32(f) != s->lines)
	279	return -EINVAL;
	280
	281	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	282	qemu_get_be32s(f, &s->ilevel[i]);
	283	qemu_get_be32s(f, &s->olevel[i]);
	284	qemu_get_be32s(f, &s->dir[i]);
	285	qemu_get_be32s(f, &s->rising[i]);
	286	qemu_get_be32s(f, &s->falling[i]);
	287	qemu_get_be32s(f, &s->status[i]);
	288	qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
	289	qemu_get_be32s(f, &s->gafr[i * 2 + 1]);
	290
	291	qemu_get_be32s(f, &s->prev_level[i]);
	292	}
	293
	294	return 0;
	295	}
	296
c1713132 AZ	297	struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
	298	CPUState env, qemu_irq pic, int lines)
	299	{
	300	int iomemtype;
	301	struct pxa2xx_gpio_info_s *s;
	302
	303	s = (struct pxa2xx_gpio_info_s *)
	304	qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
	305	memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
	306	s->base = base;
	307	s->pic = pic;
	308	s->lines = lines;
	309	s->cpu_env = env;
38641a52	310	s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
c1713132 AZ	311
	312	iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
	313	pxa2xx_gpio_writefn, s);
187337f8	314	cpu_register_physical_memory(base, 0x00001000, iomemtype);
c1713132	315
aa941b94 AZ	316	register_savevm("pxa2xx_gpio", 0, 0,
	317	pxa2xx_gpio_save, pxa2xx_gpio_load, s);
	318
c1713132 AZ	319	return s;
	320	}
	321
38641a52 AZ	322	qemu_irq pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s s)
	323	{
	324	return s->in;
	325	}
	326
	327	void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
	328	int line, qemu_irq handler)
	329	{
c1713132 AZ	330	if (line >= s->lines) {
	331	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	332	return;
	333	}
	334
38641a52	335	s->handler[line] = handler;
c1713132 AZ	336	}
	337
	338	/*
	339	* Registers a callback to notify on GPLR reads. This normally
	340	* shouldn't be needed but it is used for the hack on Spitz machines.
	341	*/
38641a52 AZ	342	void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
38641a52 AZ	343	{
c1713132	344	s->read_notify = handler;
c1713132	345	}