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[qemu.git] / hw / pxa2xx_lcd.c
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a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 */
9
87ecb68b
PB		 10#include "hw.h"
11#include "console.h"
12#include "pxa.h"
e27f01ef 13#include "pixel_ops.h"
87ecb68b
PB		 14/* FIXME: For graphic_rotate. Should probably be done in common code. */
15#include "sysemu.h"
a171fe39
AZ		 16
17typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
18
19struct pxa2xx_lcdc_s {
20 target_phys_addr_t base;
21 qemu_irq irq;
22 int irqlevel;
23
24 int invalidated;
25 DisplayState *ds;
c60e08d9 26 QEMUConsole *console;
a171fe39
AZ		 27 drawfn *line_fn[2];
28 int dest_width;
29 int xres, yres;
30 int pal_for;
31 int transp;
32 enum {
33 pxa_lcdc_2bpp = 1,
34 pxa_lcdc_4bpp = 2,
35 pxa_lcdc_8bpp = 3,
36 pxa_lcdc_16bpp = 4,
37 pxa_lcdc_18bpp = 5,
38 pxa_lcdc_18pbpp = 6,
39 pxa_lcdc_19bpp = 7,
40 pxa_lcdc_19pbpp = 8,
41 pxa_lcdc_24bpp = 9,
42 pxa_lcdc_25bpp = 10,
43 } bpp;
44
45 uint32_t control[6];
46 uint32_t status[2];
47 uint32_t ovl1c[2];
48 uint32_t ovl2c[2];
49 uint32_t ccr;
50 uint32_t cmdcr;
51 uint32_t trgbr;
52 uint32_t tcr;
53 uint32_t liidr;
54 uint8_t bscntr;
55
56 struct {
57 target_phys_addr_t branch;
58 int up;
59 uint8_t palette[1024];
60 uint8_t pbuffer[1024];
61 void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
62 int *miny, int *maxy);
63
64 target_phys_addr_t descriptor;
65 target_phys_addr_t source;
66 uint32_t id;
67 uint32_t command;
68 } dma_ch[7];
69
38641a52 70 qemu_irq vsync_cb;
a171fe39
AZ		 71 int orientation;
72};
73
74struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
75 uint32_t fdaddr;
76 uint32_t fsaddr;
77 uint32_t fidr;
78 uint32_t ldcmd;
79};
80
81#define LCCR0 0x000 /* LCD Controller Control register 0 */
82#define LCCR1 0x004 /* LCD Controller Control register 1 */
83#define LCCR2 0x008 /* LCD Controller Control register 2 */
84#define LCCR3 0x00c /* LCD Controller Control register 3 */
85#define LCCR4 0x010 /* LCD Controller Control register 4 */
86#define LCCR5 0x014 /* LCD Controller Control register 5 */
87
88#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
89#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
90#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
91#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
92#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
93#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
94#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
95
96#define LCSR1 0x034 /* LCD Controller Status register 1 */
97#define LCSR0 0x038 /* LCD Controller Status register 0 */
98#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
99
100#define TRGBR 0x040 /* TMED RGB Seed register */
101#define TCR 0x044 /* TMED Control register */
102
103#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
104#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
105#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
106#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
107#define CCR 0x090 /* Cursor Control register */
108
109#define CMDCR 0x100 /* Command Control register */
110#define PRSR 0x104 /* Panel Read Status register */
111
112#define PXA_LCDDMA_CHANS 7
113#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
114#define DMA_FSADR 0x04 /* Frame Source Address register */
115#define DMA_FIDR 0x08 /* Frame ID register */
116#define DMA_LDCMD 0x0c /* Command register */
117
118/* LCD Buffer Strength Control register */
119#define BSCNTR 0x04000054
120
121/* Bitfield masks */
122#define LCCR0_ENB (1 << 0)
123#define LCCR0_CMS (1 << 1)
124#define LCCR0_SDS (1 << 2)
125#define LCCR0_LDM (1 << 3)
126#define LCCR0_SOFM0 (1 << 4)
127#define LCCR0_IUM (1 << 5)
128#define LCCR0_EOFM0 (1 << 6)
129#define LCCR0_PAS (1 << 7)
130#define LCCR0_DPD (1 << 9)
131#define LCCR0_DIS (1 << 10)
132#define LCCR0_QDM (1 << 11)
133#define LCCR0_PDD (0xff << 12)
134#define LCCR0_BSM0 (1 << 20)
135#define LCCR0_OUM (1 << 21)
136#define LCCR0_LCDT (1 << 22)
137#define LCCR0_RDSTM (1 << 23)
138#define LCCR0_CMDIM (1 << 24)
139#define LCCR0_OUC (1 << 25)
140#define LCCR0_LDDALT (1 << 26)
141#define LCCR1_PPL(x) ((x) & 0x3ff)
142#define LCCR2_LPP(x) ((x) & 0x3ff)
143#define LCCR3_API (15 << 16)
144#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
145#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
146#define LCCR4_K1(x) (((x) >> 0) & 7)
147#define LCCR4_K2(x) (((x) >> 3) & 7)
148#define LCCR4_K3(x) (((x) >> 6) & 7)
149#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
150#define LCCR5_SOFM(ch) (1 << (ch - 1))
151#define LCCR5_EOFM(ch) (1 << (ch + 7))
152#define LCCR5_BSM(ch) (1 << (ch + 15))
153#define LCCR5_IUM(ch) (1 << (ch + 23))
154#define OVLC1_EN (1 << 31)
155#define CCR_CEN (1 << 31)
156#define FBR_BRA (1 << 0)
157#define FBR_BINT (1 << 1)
158#define FBR_SRCADDR (0xfffffff << 4)
159#define LCSR0_LDD (1 << 0)
160#define LCSR0_SOF0 (1 << 1)
161#define LCSR0_BER (1 << 2)
162#define LCSR0_ABC (1 << 3)
163#define LCSR0_IU0 (1 << 4)
164#define LCSR0_IU1 (1 << 5)
165#define LCSR0_OU (1 << 6)
166#define LCSR0_QD (1 << 7)
167#define LCSR0_EOF0 (1 << 8)
168#define LCSR0_BS0 (1 << 9)
169#define LCSR0_SINT (1 << 10)
170#define LCSR0_RDST (1 << 11)
171#define LCSR0_CMDINT (1 << 12)
172#define LCSR0_BERCH(x) (((x) & 7) << 28)
173#define LCSR1_SOF(ch) (1 << (ch - 1))
174#define LCSR1_EOF(ch) (1 << (ch + 7))
175#define LCSR1_BS(ch) (1 << (ch + 15))
176#define LCSR1_IU(ch) (1 << (ch + 23))
177#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
178#define LDCMD_EOFINT (1 << 21)
179#define LDCMD_SOFINT (1 << 22)
180#define LDCMD_PAL (1 << 26)
181
182/* Route internal interrupt lines to the global IC */
183static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
184{
185 int level = 0;
186 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
187 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
188 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
189 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
190 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
191 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
192 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
193 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
194 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
195 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
196 level |= (s->status[1] & ~s->control[5]);
197
198 qemu_set_irq(s->irq, !!level);
199 s->irqlevel = level;
200}
201
202/* Set Branch Status interrupt high and poke associated registers */
203static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
204{
205 int unmasked;
206 if (ch == 0) {
207 s->status[0] |= LCSR0_BS0;
208 unmasked = !(s->control[0] & LCCR0_BSM0);
209 } else {
210 s->status[1] |= LCSR1_BS(ch);
211 unmasked = !(s->control[5] & LCCR5_BSM(ch));
212 }
213
214 if (unmasked) {
215 if (s->irqlevel)
216 s->status[0] |= LCSR0_SINT;
217 else
218 s->liidr = s->dma_ch[ch].id;
219 }
220}
221
222/* Set Start Of Frame Status interrupt high and poke associated registers */
223static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
224{
225 int unmasked;
226 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
227 return;
228
229 if (ch == 0) {
230 s->status[0] |= LCSR0_SOF0;
231 unmasked = !(s->control[0] & LCCR0_SOFM0);
232 } else {
233 s->status[1] |= LCSR1_SOF(ch);
234 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
235 }
236
237 if (unmasked) {
238 if (s->irqlevel)
239 s->status[0] |= LCSR0_SINT;
240 else
241 s->liidr = s->dma_ch[ch].id;
242 }
243}
244
245/* Set End Of Frame Status interrupt high and poke associated registers */
246static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
247{
248 int unmasked;
249 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
250 return;
251
252 if (ch == 0) {
253 s->status[0] |= LCSR0_EOF0;
254 unmasked = !(s->control[0] & LCCR0_EOFM0);
255 } else {
256 s->status[1] |= LCSR1_EOF(ch);
257 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
258 }
259
260 if (unmasked) {
261 if (s->irqlevel)
262 s->status[0] |= LCSR0_SINT;
263 else
264 s->liidr = s->dma_ch[ch].id;
265 }
266}
267
268/* Set Bus Error Status interrupt high and poke associated registers */
269static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
270{
271 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
272 if (s->irqlevel)
273 s->status[0] |= LCSR0_SINT;
274 else
275 s->liidr = s->dma_ch[ch].id;
276}
277
278/* Set Read Status interrupt high and poke associated registers */
279static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
280{
281 s->status[0] |= LCSR0_RDST;
282 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
283 s->status[0] |= LCSR0_SINT;
284}
285
286/* Load new Frame Descriptors from DMA */
287static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
288{
289 struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
290 target_phys_addr_t descptr;
291 int i;
292
293 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
294 desc[i] = 0;
295 s->dma_ch[i].source = 0;
296
297 if (!s->dma_ch[i].up)
298 continue;
299
300 if (s->dma_ch[i].branch & FBR_BRA) {
301 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
302 if (s->dma_ch[i].branch & FBR_BINT)
303 pxa2xx_dma_bs_set(s, i);
304 s->dma_ch[i].branch &= ~FBR_BRA;
305 } else
306 descptr = s->dma_ch[i].descriptor;
307
d95b2f8d
AZ		 308 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
309 sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
a171fe39
AZ		 310 continue;
311
d95b2f8d 312 descptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 313 desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
314 s->dma_ch[i].descriptor = desc[i]->fdaddr;
315 s->dma_ch[i].source = desc[i]->fsaddr;
316 s->dma_ch[i].id = desc[i]->fidr;
317 s->dma_ch[i].command = desc[i]->ldcmd;
318 }
319}
320
321static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
322{
323 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
324 int ch;
325 offset -= s->base;
326
327 switch (offset) {
328 case LCCR0:
329 return s->control[0];
330 case LCCR1:
331 return s->control[1];
332 case LCCR2:
333 return s->control[2];
334 case LCCR3:
335 return s->control[3];
336 case LCCR4:
337 return s->control[4];
338 case LCCR5:
339 return s->control[5];
340
341 case OVL1C1:
342 return s->ovl1c[0];
343 case OVL1C2:
344 return s->ovl1c[1];
345 case OVL2C1:
346 return s->ovl2c[0];
347 case OVL2C2:
348 return s->ovl2c[1];
349
350 case CCR:
351 return s->ccr;
352
353 case CMDCR:
354 return s->cmdcr;
355
356 case TRGBR:
357 return s->trgbr;
358 case TCR:
359 return s->tcr;
360
361 case 0x200 ... 0x1000: /* DMA per-channel registers */
362 ch = (offset - 0x200) >> 4;
363 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
364 goto fail;
365
366 switch (offset & 0xf) {
367 case DMA_FDADR:
368 return s->dma_ch[ch].descriptor;
369 case DMA_FSADR:
370 return s->dma_ch[ch].source;
371 case DMA_FIDR:
372 return s->dma_ch[ch].id;
373 case DMA_LDCMD:
374 return s->dma_ch[ch].command;
375 default:
376 goto fail;
377 }
378
379 case FBR0:
380 return s->dma_ch[0].branch;
381 case FBR1:
382 return s->dma_ch[1].branch;
383 case FBR2:
384 return s->dma_ch[2].branch;
385 case FBR3:
386 return s->dma_ch[3].branch;
387 case FBR4:
388 return s->dma_ch[4].branch;
389 case FBR5:
390 return s->dma_ch[5].branch;
391 case FBR6:
392 return s->dma_ch[6].branch;
393
394 case BSCNTR:
395 return s->bscntr;
396
397 case PRSR:
398 return 0;
399
400 case LCSR0:
401 return s->status[0];
402 case LCSR1:
403 return s->status[1];
404 case LIIDR:
405 return s->liidr;
406
407 default:
408 fail:
409 cpu_abort(cpu_single_env,
410 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
411 }
412
413 return 0;
414}
415
416static void pxa2xx_lcdc_write(void *opaque,
417 target_phys_addr_t offset, uint32_t value)
418{
419 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
420 int ch;
421 offset -= s->base;
422
423 switch (offset) {
424 case LCCR0:
425 /* ACK Quick Disable done */
426 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
427 s->status[0] |= LCSR0_QD;
428
429 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
430 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
431
432 if ((s->control[3] & LCCR3_API) &&
433 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
434 s->status[0] |= LCSR0_ABC;
435
436 s->control[0] = value & 0x07ffffff;
437 pxa2xx_lcdc_int_update(s);
438
439 s->dma_ch[0].up = !!(value & LCCR0_ENB);
440 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
441 break;
442
443 case LCCR1:
444 s->control[1] = value;
445 break;
446
447 case LCCR2:
448 s->control[2] = value;
449 break;
450
451 case LCCR3:
452 s->control[3] = value & 0xefffffff;
453 s->bpp = LCCR3_BPP(value);
454 break;
455
456 case LCCR4:
457 s->control[4] = value & 0x83ff81ff;
458 break;
459
460 case LCCR5:
461 s->control[5] = value & 0x3f3f3f3f;
462 break;
463
464 case OVL1C1:
465 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
466 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
467
468 s->ovl1c[0] = value & 0x80ffffff;
469 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
470 break;
471
472 case OVL1C2:
473 s->ovl1c[1] = value & 0x000fffff;
474 break;
475
476 case OVL2C1:
477 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
478 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
479
480 s->ovl2c[0] = value & 0x80ffffff;
481 s->dma_ch[2].up = !!(value & OVLC1_EN);
482 s->dma_ch[3].up = !!(value & OVLC1_EN);
483 s->dma_ch[4].up = !!(value & OVLC1_EN);
484 break;
485
486 case OVL2C2:
487 s->ovl2c[1] = value & 0x007fffff;
488 break;
489
490 case CCR:
491 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
492 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
493
494 s->ccr = value & 0x81ffffe7;
495 s->dma_ch[5].up = !!(value & CCR_CEN);
496 break;
497
498 case CMDCR:
499 s->cmdcr = value & 0xff;
500 break;
501
502 case TRGBR:
503 s->trgbr = value & 0x00ffffff;
504 break;
505
506 case TCR:
507 s->tcr = value & 0x7fff;
508 break;
509
510 case 0x200 ... 0x1000: /* DMA per-channel registers */
511 ch = (offset - 0x200) >> 4;
512 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
513 goto fail;
514
515 switch (offset & 0xf) {
516 case DMA_FDADR:
517 s->dma_ch[ch].descriptor = value & 0xfffffff0;
518 break;
519
520 default:
521 goto fail;
522 }
523 break;
524
525 case FBR0:
526 s->dma_ch[0].branch = value & 0xfffffff3;
527 break;
528 case FBR1:
529 s->dma_ch[1].branch = value & 0xfffffff3;
530 break;
531 case FBR2:
532 s->dma_ch[2].branch = value & 0xfffffff3;
533 break;
534 case FBR3:
535 s->dma_ch[3].branch = value & 0xfffffff3;
536 break;
537 case FBR4:
538 s->dma_ch[4].branch = value & 0xfffffff3;
539 break;
540 case FBR5:
541 s->dma_ch[5].branch = value & 0xfffffff3;
542 break;
543 case FBR6:
544 s->dma_ch[6].branch = value & 0xfffffff3;
545 break;
546
547 case BSCNTR:
548 s->bscntr = value & 0xf;
549 break;
550
551 case PRSR:
552 break;
553
554 case LCSR0:
555 s->status[0] &= ~(value & 0xfff);
556 if (value & LCSR0_BER)
557 s->status[0] &= ~LCSR0_BERCH(7);
558 break;
559
560 case LCSR1:
561 s->status[1] &= ~(value & 0x3e3f3f);
562 break;
563
564 default:
565 fail:
566 cpu_abort(cpu_single_env,
567 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
568 }
569}
570
571static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
572 pxa2xx_lcdc_read,
573 pxa2xx_lcdc_read,
574 pxa2xx_lcdc_read
575};
576
577static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
578 pxa2xx_lcdc_write,
579 pxa2xx_lcdc_write,
580 pxa2xx_lcdc_write
581};
582
a171fe39
AZ		 583/* Load new palette for a given DMA channel, convert to internal format */
584static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
585{
586 int i, n, format, r, g, b, alpha;
587 uint32_t *dest, *src;
588 s->pal_for = LCCR4_PALFOR(s->control[4]);
589 format = s->pal_for;
590
591 switch (bpp) {
592 case pxa_lcdc_2bpp:
593 n = 4;
594 break;
595 case pxa_lcdc_4bpp:
596 n = 16;
597 break;
598 case pxa_lcdc_8bpp:
599 n = 256;
600 break;
601 default:
602 format = 0;
603 return;
604 }
605
606 src = (uint32_t *) s->dma_ch[ch].pbuffer;
607 dest = (uint32_t *) s->dma_ch[ch].palette;
608 alpha = r = g = b = 0;
609
610 for (i = 0; i < n; i ++) {
611 switch (format) {
612 case 0: /* 16 bpp, no transparency */
613 alpha = 0;
614 if (s->control[0] & LCCR0_CMS)
615 r = g = b = *src & 0xff;
616 else {
617 r = (*src & 0xf800) >> 8;
618 g = (*src & 0x07e0) >> 3;
619 b = (*src & 0x001f) << 3;
620 }
621 break;
622 case 1: /* 16 bpp plus transparency */
623 alpha = *src & (1 << 24);
624 if (s->control[0] & LCCR0_CMS)
625 r = g = b = *src & 0xff;
626 else {
627 r = (*src & 0xf800) >> 8;
628 g = (*src & 0x07e0) >> 3;
629 b = (*src & 0x001f) << 3;
630 }
631 break;
632 case 2: /* 18 bpp plus transparency */
633 alpha = *src & (1 << 24);
634 if (s->control[0] & LCCR0_CMS)
635 r = g = b = *src & 0xff;
636 else {
637 r = (*src & 0xf80000) >> 16;
638 g = (*src & 0x00fc00) >> 8;
639 b = (*src & 0x0000f8);
640 }
641 break;
642 case 3: /* 24 bpp plus transparency */
643 alpha = *src & (1 << 24);
644 if (s->control[0] & LCCR0_CMS)
645 r = g = b = *src & 0xff;
646 else {
647 r = (*src & 0xff0000) >> 16;
648 g = (*src & 0x00ff00) >> 8;
649 b = (*src & 0x0000ff);
650 }
651 break;
652 }
653 switch (s->ds->depth) {
654 case 8:
655 *dest = rgb_to_pixel8(r, g, b) | alpha;
656 break;
657 case 15:
658 *dest = rgb_to_pixel15(r, g, b) | alpha;
659 break;
660 case 16:
661 *dest = rgb_to_pixel16(r, g, b) | alpha;
662 break;
663 case 24:
664 *dest = rgb_to_pixel24(r, g, b) | alpha;
665 break;
666 case 32:
667 *dest = rgb_to_pixel32(r, g, b) | alpha;
668 break;
669 }
670 src ++;
671 dest ++;
672 }
673}
674
675static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
676 uint8_t *fb, int *miny, int *maxy)
677{
678 int y, src_width, dest_width, dirty[2];
679 uint8_t *src, *dest;
680 ram_addr_t x, addr, new_addr, start, end;
681 drawfn fn = 0;
682 if (s->dest_width)
683 fn = s->line_fn[s->transp][s->bpp];
684 if (!fn)
685 return;
686
687 src = fb;
688 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
689 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
690 src_width *= 3;
691 else if (s->bpp > pxa_lcdc_16bpp)
692 src_width *= 4;
693 else if (s->bpp > pxa_lcdc_8bpp)
694 src_width *= 2;
695
696 dest = s->ds->data;
697 dest_width = s->xres * s->dest_width;
698
699 addr = (ram_addr_t) (fb - phys_ram_base);
700 start = addr + s->yres * src_width;
701 end = addr;
702 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
703 for (y = 0; y < s->yres; y ++) {
704 new_addr = addr + src_width;
705 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
706 x += TARGET_PAGE_SIZE) {
707 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
708 dirty[0] |= dirty[1];
709 }
710 if (dirty[0] || s->invalidated) {
711 fn((uint32_t *) s->dma_ch[0].palette,
712 dest, src, s->xres, s->dest_width);
713 if (addr < start)
714 start = addr;
a07dec22 715 end = new_addr;
a171fe39
AZ		 716 if (y < *miny)
717 *miny = y;
718 if (y >= *maxy)
719 *maxy = y + 1;
720 }
721 addr = new_addr;
722 dirty[0] = dirty[1];
723 src += src_width;
724 dest += dest_width;
725 }
726
727 if (end > start)
728 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
729}
730
731static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
732 uint8_t *fb, int *miny, int *maxy)
733{
734 int y, src_width, dest_width, dirty[2];
735 uint8_t *src, *dest;
736 ram_addr_t x, addr, new_addr, start, end;
737 drawfn fn = 0;
738 if (s->dest_width)
739 fn = s->line_fn[s->transp][s->bpp];
740 if (!fn)
741 return;
742
743 src = fb;
744 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
745 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
746 src_width *= 3;
747 else if (s->bpp > pxa_lcdc_16bpp)
748 src_width *= 4;
749 else if (s->bpp > pxa_lcdc_8bpp)
750 src_width *= 2;
751
752 dest_width = s->yres * s->dest_width;
753 dest = s->ds->data + dest_width * (s->xres - 1);
754
755 addr = (ram_addr_t) (fb - phys_ram_base);
756 start = addr + s->yres * src_width;
757 end = addr;
758 dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
759 for (y = 0; y < s->yres; y ++) {
760 new_addr = addr + src_width;
761 for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
762 x += TARGET_PAGE_SIZE) {
763 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
764 dirty[0] |= dirty[1];
765 }
766 if (dirty[0] || s->invalidated) {
767 fn((uint32_t *) s->dma_ch[0].palette,
768 dest, src, s->xres, -dest_width);
769 if (addr < start)
770 start = addr;
3f582262 771 end = new_addr;
a171fe39
AZ		 772 if (y < *miny)
773 *miny = y;
774 if (y >= *maxy)
775 *maxy = y + 1;
776 }
777 addr = new_addr;
778 dirty[0] = dirty[1];
779 src += src_width;
780 dest += s->dest_width;
781 }
782
783 if (end > start)
784 cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
785}
786
787static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
788{
789 int width, height;
790 if (!(s->control[0] & LCCR0_ENB))
791 return;
792
793 width = LCCR1_PPL(s->control[1]) + 1;
794 height = LCCR2_LPP(s->control[2]) + 1;
795
796 if (width != s->xres || height != s->yres) {
797 if (s->orientation)
c60e08d9 798 qemu_console_resize(s->console, height, width);
a171fe39 799 else
c60e08d9 800 qemu_console_resize(s->console, width, height);
a171fe39
AZ		 801 s->invalidated = 1;
802 s->xres = width;
803 s->yres = height;
804 }
805}
806
807static void pxa2xx_update_display(void *opaque)
808{
809 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
810 uint8_t *fb;
811 target_phys_addr_t fbptr;
812 int miny, maxy;
813 int ch;
814 if (!(s->control[0] & LCCR0_ENB))
815 return;
816
817 pxa2xx_descriptor_load(s);
818
819 pxa2xx_lcdc_resize(s);
820 miny = s->yres;
821 maxy = 0;
822 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
823 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
824 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
825 if (s->dma_ch[ch].up) {
826 if (!s->dma_ch[ch].source) {
827 pxa2xx_dma_ber_set(s, ch);
828 continue;
829 }
830 fbptr = s->dma_ch[ch].source;
d95b2f8d
AZ		 831 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
832 fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
a171fe39
AZ		 833 pxa2xx_dma_ber_set(s, ch);
834 continue;
835 }
d95b2f8d 836 fbptr -= PXA2XX_SDRAM_BASE;
a171fe39
AZ		 837 fb = phys_ram_base + fbptr;
838
839 if (s->dma_ch[ch].command & LDCMD_PAL) {
840 memcpy(s->dma_ch[ch].pbuffer, fb,
841 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
842 sizeof(s->dma_ch[ch].pbuffer)));
843 pxa2xx_palette_parse(s, ch, s->bpp);
844 } else {
845 /* Do we need to reparse palette */
846 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
847 pxa2xx_palette_parse(s, ch, s->bpp);
848
849 /* ACK frame start */
850 pxa2xx_dma_sof_set(s, ch);
851
852 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
853 s->invalidated = 0;
854
855 /* ACK frame completed */
856 pxa2xx_dma_eof_set(s, ch);
857 }
858 }
859
860 if (s->control[0] & LCCR0_DIS) {
861 /* ACK last frame completed */
862 s->control[0] &= ~LCCR0_ENB;
863 s->status[0] |= LCSR0_LDD;
864 }
865
866 if (s->orientation)
867 dpy_update(s->ds, miny, 0, maxy, s->xres);
868 else
869 dpy_update(s->ds, 0, miny, s->xres, maxy);
870 pxa2xx_lcdc_int_update(s);
871
38641a52 872 qemu_irq_raise(s->vsync_cb);
a171fe39
AZ		 873}
874
875static void pxa2xx_invalidate_display(void *opaque)
876{
877 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
878 s->invalidated = 1;
879}
880
881static void pxa2xx_screen_dump(void *opaque, const char *filename)
882{
883 /* TODO */
884}
885
9596ebb7 886static void pxa2xx_lcdc_orientation(void *opaque, int angle)
a171fe39
AZ		 887{
888 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
889
890 if (angle) {
891 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
892 } else {
893 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
894 }
895
896 s->orientation = angle;
897 s->xres = s->yres = -1;
898 pxa2xx_lcdc_resize(s);
899}
900
aa941b94
AZ		 901static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
902{
903 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
904 int i;
905
906 qemu_put_be32(f, s->irqlevel);
907 qemu_put_be32(f, s->transp);
908
909 for (i = 0; i < 6; i ++)
910 qemu_put_be32s(f, &s->control[i]);
911 for (i = 0; i < 2; i ++)
912 qemu_put_be32s(f, &s->status[i]);
913 for (i = 0; i < 2; i ++)
914 qemu_put_be32s(f, &s->ovl1c[i]);
915 for (i = 0; i < 2; i ++)
916 qemu_put_be32s(f, &s->ovl2c[i]);
917 qemu_put_be32s(f, &s->ccr);
918 qemu_put_be32s(f, &s->cmdcr);
919 qemu_put_be32s(f, &s->trgbr);
920 qemu_put_be32s(f, &s->tcr);
921 qemu_put_be32s(f, &s->liidr);
922 qemu_put_8s(f, &s->bscntr);
923
924 for (i = 0; i < 7; i ++) {
925 qemu_put_betl(f, s->dma_ch[i].branch);
926 qemu_put_byte(f, s->dma_ch[i].up);
927 qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
928
929 qemu_put_betl(f, s->dma_ch[i].descriptor);
930 qemu_put_betl(f, s->dma_ch[i].source);
931 qemu_put_be32s(f, &s->dma_ch[i].id);
932 qemu_put_be32s(f, &s->dma_ch[i].command);
933 }
934}
935
936static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
937{
938 struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
939 int i;
940
941 s->irqlevel = qemu_get_be32(f);
942 s->transp = qemu_get_be32(f);
943
944 for (i = 0; i < 6; i ++)
945 qemu_get_be32s(f, &s->control[i]);
946 for (i = 0; i < 2; i ++)
947 qemu_get_be32s(f, &s->status[i]);
948 for (i = 0; i < 2; i ++)
949 qemu_get_be32s(f, &s->ovl1c[i]);
950 for (i = 0; i < 2; i ++)
951 qemu_get_be32s(f, &s->ovl2c[i]);
952 qemu_get_be32s(f, &s->ccr);
953 qemu_get_be32s(f, &s->cmdcr);
954 qemu_get_be32s(f, &s->trgbr);
955 qemu_get_be32s(f, &s->tcr);
956 qemu_get_be32s(f, &s->liidr);
957 qemu_get_8s(f, &s->bscntr);
958
959 for (i = 0; i < 7; i ++) {
960 s->dma_ch[i].branch = qemu_get_betl(f);
961 s->dma_ch[i].up = qemu_get_byte(f);
962 qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
963
964 s->dma_ch[i].descriptor = qemu_get_betl(f);
965 s->dma_ch[i].source = qemu_get_betl(f);
966 qemu_get_be32s(f, &s->dma_ch[i].id);
967 qemu_get_be32s(f, &s->dma_ch[i].command);
968 }
969
970 s->bpp = LCCR3_BPP(s->control[3]);
971 s->xres = s->yres = s->pal_for = -1;
972
973 return 0;
974}
975
a171fe39
AZ		 976#define BITS 8
977#include "pxa2xx_template.h"
978#define BITS 15
979#include "pxa2xx_template.h"
980#define BITS 16
981#include "pxa2xx_template.h"
982#define BITS 24
983#include "pxa2xx_template.h"
984#define BITS 32
985#include "pxa2xx_template.h"
986
987struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
988 DisplayState *ds)
989{
990 int iomemtype;
991 struct pxa2xx_lcdc_s *s;
992
993 s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
994 s->base = base;
995 s->invalidated = 1;
996 s->irq = irq;
997 s->ds = ds;
998
999 pxa2xx_lcdc_orientation(s, graphic_rotate);
1000
1001 iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
1002 pxa2xx_lcdc_writefn, s);
187337f8 1003 cpu_register_physical_memory(base, 0x00100000, iomemtype);
a171fe39 1004
c60e08d9
PB		 1005 s->console = graphic_console_init(ds, pxa2xx_update_display,
1006 pxa2xx_invalidate_display,
1007 pxa2xx_screen_dump, NULL, s);
a171fe39
AZ		 1008
1009 switch (s->ds->depth) {
1010 case 0:
1011 s->dest_width = 0;
1012 break;
1013 case 8:
1014 s->line_fn[0] = pxa2xx_draw_fn_8;
1015 s->line_fn[1] = pxa2xx_draw_fn_8t;
1016 s->dest_width = 1;
1017 break;
1018 case 15:
1019 s->line_fn[0] = pxa2xx_draw_fn_15;
1020 s->line_fn[1] = pxa2xx_draw_fn_15t;
1021 s->dest_width = 2;
1022 break;
1023 case 16:
1024 s->line_fn[0] = pxa2xx_draw_fn_16;
1025 s->line_fn[1] = pxa2xx_draw_fn_16t;
1026 s->dest_width = 2;
1027 break;
1028 case 24:
1029 s->line_fn[0] = pxa2xx_draw_fn_24;
1030 s->line_fn[1] = pxa2xx_draw_fn_24t;
1031 s->dest_width = 3;
1032 break;
1033 case 32:
1034 s->line_fn[0] = pxa2xx_draw_fn_32;
1035 s->line_fn[1] = pxa2xx_draw_fn_32t;
1036 s->dest_width = 4;
1037 break;
1038 default:
1039 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1040 exit(1);
1041 }
aa941b94
AZ		 1042
1043 register_savevm("pxa2xx_lcdc", 0, 0,
1044 pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
1045
a171fe39
AZ		 1046 return s;
1047}
1048
38641a52
AZ		 1049void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
1050{
1051 s->vsync_cb = handler;
a171fe39 1052}
Qemu copy for testing