]> git.proxmox.com Git - qemu.git/blame - hw/pxa2xx_lcd.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
virtio-blk: hide VIRTIO_BLK_F_CONFIG_WCE from old machine types
[qemu.git] / hw / pxa2xx_lcd.c
CommitLineData
a171fe39
AZ		 1/*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
6b620ca3
PB		 8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
a171fe39
AZ		 11 */
12
87ecb68b
PB		 13#include "hw.h"
14#include "console.h"
15#include "pxa.h"
e27f01ef 16#include "pixel_ops.h"
87ecb68b
PB		 17/* FIXME: For graphic_rotate. Should probably be done in common code. */
18#include "sysemu.h"
714fa308 19#include "framebuffer.h"
a171fe39 20
2b7251e0 21struct DMAChannel {
27424dcc 22 uint32_t branch;
46995409 23 uint8_t up;
2b7251e0
JQ		 24 uint8_t palette[1024];
25 uint8_t pbuffer[1024];
26 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
27 int *miny, int *maxy);
28
27424dcc
MI		 29 uint32_t descriptor;
30 uint32_t source;
2b7251e0
JQ		 31 uint32_t id;
32 uint32_t command;
33};
34
bc24a225 35struct PXA2xxLCDState {
75c9d6c2 36 MemoryRegion *sysmem;
5a6fdd91 37 MemoryRegion iomem;
a171fe39
AZ		 38 qemu_irq irq;
39 int irqlevel;
40
41 int invalidated;
42 DisplayState *ds;
43 drawfn *line_fn[2];
44 int dest_width;
45 int xres, yres;
46 int pal_for;
47 int transp;
48 enum {
49 pxa_lcdc_2bpp = 1,
50 pxa_lcdc_4bpp = 2,
51 pxa_lcdc_8bpp = 3,
52 pxa_lcdc_16bpp = 4,
53 pxa_lcdc_18bpp = 5,
54 pxa_lcdc_18pbpp = 6,
55 pxa_lcdc_19bpp = 7,
56 pxa_lcdc_19pbpp = 8,
57 pxa_lcdc_24bpp = 9,
58 pxa_lcdc_25bpp = 10,
59 } bpp;
60
61 uint32_t control[6];
62 uint32_t status[2];
63 uint32_t ovl1c[2];
64 uint32_t ovl2c[2];
65 uint32_t ccr;
66 uint32_t cmdcr;
67 uint32_t trgbr;
68 uint32_t tcr;
69 uint32_t liidr;
70 uint8_t bscntr;
71
2b7251e0 72 struct DMAChannel dma_ch[7];
a171fe39 73
38641a52 74 qemu_irq vsync_cb;
a171fe39
AZ		 75 int orientation;
76};
77
541dc0d4 78typedef struct QEMU_PACKED {
a171fe39
AZ		 79 uint32_t fdaddr;
80 uint32_t fsaddr;
81 uint32_t fidr;
82 uint32_t ldcmd;
bc24a225 83} PXAFrameDescriptor;
a171fe39
AZ		 84
85#define LCCR0 0x000 /* LCD Controller Control register 0 */
86#define LCCR1 0x004 /* LCD Controller Control register 1 */
87#define LCCR2 0x008 /* LCD Controller Control register 2 */
88#define LCCR3 0x00c /* LCD Controller Control register 3 */
89#define LCCR4 0x010 /* LCD Controller Control register 4 */
90#define LCCR5 0x014 /* LCD Controller Control register 5 */
91
92#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
93#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
94#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
95#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
96#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
97#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
98#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
99
100#define LCSR1 0x034 /* LCD Controller Status register 1 */
101#define LCSR0 0x038 /* LCD Controller Status register 0 */
102#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
103
104#define TRGBR 0x040 /* TMED RGB Seed register */
105#define TCR 0x044 /* TMED Control register */
106
107#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
108#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
109#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
110#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
111#define CCR 0x090 /* Cursor Control register */
112
113#define CMDCR 0x100 /* Command Control register */
114#define PRSR 0x104 /* Panel Read Status register */
115
116#define PXA_LCDDMA_CHANS 7
117#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
118#define DMA_FSADR 0x04 /* Frame Source Address register */
119#define DMA_FIDR 0x08 /* Frame ID register */
120#define DMA_LDCMD 0x0c /* Command register */
121
122/* LCD Buffer Strength Control register */
123#define BSCNTR 0x04000054
124
125/* Bitfield masks */
126#define LCCR0_ENB (1 << 0)
127#define LCCR0_CMS (1 << 1)
128#define LCCR0_SDS (1 << 2)
129#define LCCR0_LDM (1 << 3)
130#define LCCR0_SOFM0 (1 << 4)
131#define LCCR0_IUM (1 << 5)
132#define LCCR0_EOFM0 (1 << 6)
133#define LCCR0_PAS (1 << 7)
134#define LCCR0_DPD (1 << 9)
135#define LCCR0_DIS (1 << 10)
136#define LCCR0_QDM (1 << 11)
137#define LCCR0_PDD (0xff << 12)
138#define LCCR0_BSM0 (1 << 20)
139#define LCCR0_OUM (1 << 21)
140#define LCCR0_LCDT (1 << 22)
141#define LCCR0_RDSTM (1 << 23)
142#define LCCR0_CMDIM (1 << 24)
143#define LCCR0_OUC (1 << 25)
144#define LCCR0_LDDALT (1 << 26)
145#define LCCR1_PPL(x) ((x) & 0x3ff)
146#define LCCR2_LPP(x) ((x) & 0x3ff)
147#define LCCR3_API (15 << 16)
148#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
149#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
150#define LCCR4_K1(x) (((x) >> 0) & 7)
151#define LCCR4_K2(x) (((x) >> 3) & 7)
152#define LCCR4_K3(x) (((x) >> 6) & 7)
153#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
154#define LCCR5_SOFM(ch) (1 << (ch - 1))
155#define LCCR5_EOFM(ch) (1 << (ch + 7))
156#define LCCR5_BSM(ch) (1 << (ch + 15))
157#define LCCR5_IUM(ch) (1 << (ch + 23))
158#define OVLC1_EN (1 << 31)
159#define CCR_CEN (1 << 31)
160#define FBR_BRA (1 << 0)
161#define FBR_BINT (1 << 1)
162#define FBR_SRCADDR (0xfffffff << 4)
163#define LCSR0_LDD (1 << 0)
164#define LCSR0_SOF0 (1 << 1)
165#define LCSR0_BER (1 << 2)
166#define LCSR0_ABC (1 << 3)
167#define LCSR0_IU0 (1 << 4)
168#define LCSR0_IU1 (1 << 5)
169#define LCSR0_OU (1 << 6)
170#define LCSR0_QD (1 << 7)
171#define LCSR0_EOF0 (1 << 8)
172#define LCSR0_BS0 (1 << 9)
173#define LCSR0_SINT (1 << 10)
174#define LCSR0_RDST (1 << 11)
175#define LCSR0_CMDINT (1 << 12)
176#define LCSR0_BERCH(x) (((x) & 7) << 28)
177#define LCSR1_SOF(ch) (1 << (ch - 1))
178#define LCSR1_EOF(ch) (1 << (ch + 7))
179#define LCSR1_BS(ch) (1 << (ch + 15))
180#define LCSR1_IU(ch) (1 << (ch + 23))
181#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
182#define LDCMD_EOFINT (1 << 21)
183#define LDCMD_SOFINT (1 << 22)
184#define LDCMD_PAL (1 << 26)
185
186/* Route internal interrupt lines to the global IC */
bc24a225 187static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
a171fe39
AZ		 188{
189 int level = 0;
190 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
191 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
192 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
193 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
194 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
195 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
196 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
197 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
198 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
199 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
200 level |= (s->status[1] & ~s->control[5]);
201
202 qemu_set_irq(s->irq, !!level);
203 s->irqlevel = level;
204}
205
206/* Set Branch Status interrupt high and poke associated registers */
bc24a225 207static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 208{
209 int unmasked;
210 if (ch == 0) {
211 s->status[0] |= LCSR0_BS0;
212 unmasked = !(s->control[0] & LCCR0_BSM0);
213 } else {
214 s->status[1] |= LCSR1_BS(ch);
215 unmasked = !(s->control[5] & LCCR5_BSM(ch));
216 }
217
218 if (unmasked) {
219 if (s->irqlevel)
220 s->status[0] |= LCSR0_SINT;
221 else
222 s->liidr = s->dma_ch[ch].id;
223 }
224}
225
226/* Set Start Of Frame Status interrupt high and poke associated registers */
bc24a225 227static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 228{
229 int unmasked;
230 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
231 return;
232
233 if (ch == 0) {
234 s->status[0] |= LCSR0_SOF0;
235 unmasked = !(s->control[0] & LCCR0_SOFM0);
236 } else {
237 s->status[1] |= LCSR1_SOF(ch);
238 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
239 }
240
241 if (unmasked) {
242 if (s->irqlevel)
243 s->status[0] |= LCSR0_SINT;
244 else
245 s->liidr = s->dma_ch[ch].id;
246 }
247}
248
249/* Set End Of Frame Status interrupt high and poke associated registers */
bc24a225 250static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 251{
252 int unmasked;
253 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
254 return;
255
256 if (ch == 0) {
257 s->status[0] |= LCSR0_EOF0;
258 unmasked = !(s->control[0] & LCCR0_EOFM0);
259 } else {
260 s->status[1] |= LCSR1_EOF(ch);
261 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
262 }
263
264 if (unmasked) {
265 if (s->irqlevel)
266 s->status[0] |= LCSR0_SINT;
267 else
268 s->liidr = s->dma_ch[ch].id;
269 }
270}
271
272/* Set Bus Error Status interrupt high and poke associated registers */
bc24a225 273static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
a171fe39
AZ		 274{
275 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
276 if (s->irqlevel)
277 s->status[0] |= LCSR0_SINT;
278 else
279 s->liidr = s->dma_ch[ch].id;
280}
281
282/* Set Read Status interrupt high and poke associated registers */
bc24a225 283static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
a171fe39
AZ		 284{
285 s->status[0] |= LCSR0_RDST;
286 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
287 s->status[0] |= LCSR0_SINT;
288}
289
290/* Load new Frame Descriptors from DMA */
bc24a225 291static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
a171fe39 292{
bc24a225 293 PXAFrameDescriptor desc;
c227f099 294 target_phys_addr_t descptr;
a171fe39
AZ		 295 int i;
296
297 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
a171fe39
AZ		 298 s->dma_ch[i].source = 0;
299
300 if (!s->dma_ch[i].up)
301 continue;
302
303 if (s->dma_ch[i].branch & FBR_BRA) {
304 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
305 if (s->dma_ch[i].branch & FBR_BINT)
306 pxa2xx_dma_bs_set(s, i);
307 s->dma_ch[i].branch &= ~FBR_BRA;
308 } else
309 descptr = s->dma_ch[i].descriptor;
310
4f56da61
VK		 311 if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
312 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
313 (descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
314 PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
a171fe39 315 continue;
4f56da61 316 }
a171fe39 317
d7585251
PB		 318 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
319 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
320 s->dma_ch[i].source = tswap32(desc.fsaddr);
321 s->dma_ch[i].id = tswap32(desc.fidr);
322 s->dma_ch[i].command = tswap32(desc.ldcmd);
a171fe39
AZ		 323 }
324}
325
5a6fdd91
BC		 326static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
327 unsigned size)
a171fe39 328{
bc24a225 329 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 330 int ch;
a171fe39
AZ		 331
332 switch (offset) {
333 case LCCR0:
334 return s->control[0];
335 case LCCR1:
336 return s->control[1];
337 case LCCR2:
338 return s->control[2];
339 case LCCR3:
340 return s->control[3];
341 case LCCR4:
342 return s->control[4];
343 case LCCR5:
344 return s->control[5];
345
346 case OVL1C1:
347 return s->ovl1c[0];
348 case OVL1C2:
349 return s->ovl1c[1];
350 case OVL2C1:
351 return s->ovl2c[0];
352 case OVL2C2:
353 return s->ovl2c[1];
354
355 case CCR:
356 return s->ccr;
357
358 case CMDCR:
359 return s->cmdcr;
360
361 case TRGBR:
362 return s->trgbr;
363 case TCR:
364 return s->tcr;
365
366 case 0x200 ... 0x1000: /* DMA per-channel registers */
367 ch = (offset - 0x200) >> 4;
368 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
369 goto fail;
370
371 switch (offset & 0xf) {
372 case DMA_FDADR:
373 return s->dma_ch[ch].descriptor;
374 case DMA_FSADR:
375 return s->dma_ch[ch].source;
376 case DMA_FIDR:
377 return s->dma_ch[ch].id;
378 case DMA_LDCMD:
379 return s->dma_ch[ch].command;
380 default:
381 goto fail;
382 }
383
384 case FBR0:
385 return s->dma_ch[0].branch;
386 case FBR1:
387 return s->dma_ch[1].branch;
388 case FBR2:
389 return s->dma_ch[2].branch;
390 case FBR3:
391 return s->dma_ch[3].branch;
392 case FBR4:
393 return s->dma_ch[4].branch;
394 case FBR5:
395 return s->dma_ch[5].branch;
396 case FBR6:
397 return s->dma_ch[6].branch;
398
399 case BSCNTR:
400 return s->bscntr;
401
402 case PRSR:
403 return 0;
404
405 case LCSR0:
406 return s->status[0];
407 case LCSR1:
408 return s->status[1];
409 case LIIDR:
410 return s->liidr;
411
412 default:
413 fail:
2ac71179 414 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 415 }
416
417 return 0;
418}
419
5a6fdd91
BC		 420static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
421 uint64_t value, unsigned size)
a171fe39 422{
bc24a225 423 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 424 int ch;
a171fe39
AZ		 425
426 switch (offset) {
427 case LCCR0:
428 /* ACK Quick Disable done */
429 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
430 s->status[0] |= LCSR0_QD;
431
432 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
433 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
434
435 if ((s->control[3] & LCCR3_API) &&
436 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
437 s->status[0] |= LCSR0_ABC;
438
439 s->control[0] = value & 0x07ffffff;
440 pxa2xx_lcdc_int_update(s);
441
442 s->dma_ch[0].up = !!(value & LCCR0_ENB);
443 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
444 break;
445
446 case LCCR1:
447 s->control[1] = value;
448 break;
449
450 case LCCR2:
451 s->control[2] = value;
452 break;
453
454 case LCCR3:
455 s->control[3] = value & 0xefffffff;
456 s->bpp = LCCR3_BPP(value);
457 break;
458
459 case LCCR4:
460 s->control[4] = value & 0x83ff81ff;
461 break;
462
463 case LCCR5:
464 s->control[5] = value & 0x3f3f3f3f;
465 break;
466
467 case OVL1C1:
468 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
469 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
470
471 s->ovl1c[0] = value & 0x80ffffff;
472 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
473 break;
474
475 case OVL1C2:
476 s->ovl1c[1] = value & 0x000fffff;
477 break;
478
479 case OVL2C1:
480 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
481 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
482
483 s->ovl2c[0] = value & 0x80ffffff;
484 s->dma_ch[2].up = !!(value & OVLC1_EN);
485 s->dma_ch[3].up = !!(value & OVLC1_EN);
486 s->dma_ch[4].up = !!(value & OVLC1_EN);
487 break;
488
489 case OVL2C2:
490 s->ovl2c[1] = value & 0x007fffff;
491 break;
492
493 case CCR:
494 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
495 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
496
497 s->ccr = value & 0x81ffffe7;
498 s->dma_ch[5].up = !!(value & CCR_CEN);
499 break;
500
501 case CMDCR:
502 s->cmdcr = value & 0xff;
503 break;
504
505 case TRGBR:
506 s->trgbr = value & 0x00ffffff;
507 break;
508
509 case TCR:
510 s->tcr = value & 0x7fff;
511 break;
512
513 case 0x200 ... 0x1000: /* DMA per-channel registers */
514 ch = (offset - 0x200) >> 4;
515 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
516 goto fail;
517
518 switch (offset & 0xf) {
519 case DMA_FDADR:
520 s->dma_ch[ch].descriptor = value & 0xfffffff0;
521 break;
522
523 default:
524 goto fail;
525 }
526 break;
527
528 case FBR0:
529 s->dma_ch[0].branch = value & 0xfffffff3;
530 break;
531 case FBR1:
532 s->dma_ch[1].branch = value & 0xfffffff3;
533 break;
534 case FBR2:
535 s->dma_ch[2].branch = value & 0xfffffff3;
536 break;
537 case FBR3:
538 s->dma_ch[3].branch = value & 0xfffffff3;
539 break;
540 case FBR4:
541 s->dma_ch[4].branch = value & 0xfffffff3;
542 break;
543 case FBR5:
544 s->dma_ch[5].branch = value & 0xfffffff3;
545 break;
546 case FBR6:
547 s->dma_ch[6].branch = value & 0xfffffff3;
548 break;
549
550 case BSCNTR:
551 s->bscntr = value & 0xf;
552 break;
553
554 case PRSR:
555 break;
556
557 case LCSR0:
558 s->status[0] &= ~(value & 0xfff);
559 if (value & LCSR0_BER)
560 s->status[0] &= ~LCSR0_BERCH(7);
561 break;
562
563 case LCSR1:
564 s->status[1] &= ~(value & 0x3e3f3f);
565 break;
566
567 default:
568 fail:
2ac71179 569 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39
AZ		 570 }
571}
572
5a6fdd91
BC		 573static const MemoryRegionOps pxa2xx_lcdc_ops = {
574 .read = pxa2xx_lcdc_read,
575 .write = pxa2xx_lcdc_write,
576 .endianness = DEVICE_NATIVE_ENDIAN,
a171fe39
AZ		 577};
578
a171fe39 579/* Load new palette for a given DMA channel, convert to internal format */
bc24a225 580static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
a171fe39
AZ		 581{
582 int i, n, format, r, g, b, alpha;
7ab3aedf
VK		 583 uint32_t *dest;
584 uint8_t *src;
a171fe39
AZ		 585 s->pal_for = LCCR4_PALFOR(s->control[4]);
586 format = s->pal_for;
587
588 switch (bpp) {
589 case pxa_lcdc_2bpp:
590 n = 4;
591 break;
592 case pxa_lcdc_4bpp:
593 n = 16;
594 break;
595 case pxa_lcdc_8bpp:
596 n = 256;
597 break;
598 default:
599 format = 0;
600 return;
601 }
602
7ab3aedf 603 src = (uint8_t *) s->dma_ch[ch].pbuffer;
a171fe39
AZ		 604 dest = (uint32_t *) s->dma_ch[ch].palette;
605 alpha = r = g = b = 0;
606
607 for (i = 0; i < n; i ++) {
608 switch (format) {
609 case 0: /* 16 bpp, no transparency */
610 alpha = 0;
7ab3aedf
VK		 611 if (s->control[0] & LCCR0_CMS) {
612 r = g = b = *(uint16_t *) src & 0xff;
613 }
a171fe39 614 else {
7ab3aedf
VK		 615 r = (*(uint16_t *) src & 0xf800) >> 8;
616 g = (*(uint16_t *) src & 0x07e0) >> 3;
617 b = (*(uint16_t *) src & 0x001f) << 3;
a171fe39 618 }
7ab3aedf 619 src += 2;
a171fe39
AZ		 620 break;
621 case 1: /* 16 bpp plus transparency */
7ab3aedf 622 alpha = *(uint16_t *) src & (1 << 24);
a171fe39 623 if (s->control[0] & LCCR0_CMS)
7ab3aedf 624 r = g = b = *(uint16_t *) src & 0xff;
a171fe39 625 else {
7ab3aedf
VK		 626 r = (*(uint16_t *) src & 0xf800) >> 8;
627 g = (*(uint16_t *) src & 0x07e0) >> 3;
628 b = (*(uint16_t *) src & 0x001f) << 3;
a171fe39 629 }
7ab3aedf 630 src += 2;
a171fe39
AZ		 631 break;
632 case 2: /* 18 bpp plus transparency */
7ab3aedf 633 alpha = *(uint32_t *) src & (1 << 24);
a171fe39 634 if (s->control[0] & LCCR0_CMS)
7ab3aedf 635 r = g = b = *(uint32_t *) src & 0xff;
a171fe39 636 else {
7ab3aedf
VK		 637 r = (*(uint32_t *) src & 0xf80000) >> 16;
638 g = (*(uint32_t *) src & 0x00fc00) >> 8;
639 b = (*(uint32_t *) src & 0x0000f8);
a171fe39 640 }
7ab3aedf 641 src += 4;
a171fe39
AZ		 642 break;
643 case 3: /* 24 bpp plus transparency */
7ab3aedf 644 alpha = *(uint32_t *) src & (1 << 24);
a171fe39 645 if (s->control[0] & LCCR0_CMS)
7ab3aedf 646 r = g = b = *(uint32_t *) src & 0xff;
a171fe39 647 else {
7ab3aedf
VK		 648 r = (*(uint32_t *) src & 0xff0000) >> 16;
649 g = (*(uint32_t *) src & 0x00ff00) >> 8;
650 b = (*(uint32_t *) src & 0x0000ff);
a171fe39 651 }
7ab3aedf 652 src += 4;
a171fe39
AZ		 653 break;
654 }
0e1f5a0c 655 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 656 case 8:
657 *dest = rgb_to_pixel8(r, g, b) | alpha;
658 break;
659 case 15:
660 *dest = rgb_to_pixel15(r, g, b) | alpha;
661 break;
662 case 16:
663 *dest = rgb_to_pixel16(r, g, b) | alpha;
664 break;
665 case 24:
666 *dest = rgb_to_pixel24(r, g, b) | alpha;
667 break;
668 case 32:
669 *dest = rgb_to_pixel32(r, g, b) | alpha;
670 break;
671 }
a171fe39
AZ		 672 dest ++;
673 }
674}
675
9312805d 676static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
c227f099 677 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 678{
714fa308 679 int src_width, dest_width;
b9d38e95 680 drawfn fn = NULL;
a171fe39
AZ		 681 if (s->dest_width)
682 fn = s->line_fn[s->transp][s->bpp];
683 if (!fn)
684 return;
685
a171fe39
AZ		 686 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
687 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
688 src_width *= 3;
689 else if (s->bpp > pxa_lcdc_16bpp)
690 src_width *= 4;
691 else if (s->bpp > pxa_lcdc_8bpp)
692 src_width *= 2;
693
a171fe39 694 dest_width = s->xres * s->dest_width;
714fa308 695 *miny = 0;
75c9d6c2 696 framebuffer_update_display(s->ds, s->sysmem,
714fa308
PB		 697 addr, s->xres, s->yres,
698 src_width, dest_width, s->dest_width,
699 s->invalidated,
700 fn, s->dma_ch[0].palette, miny, maxy);
a171fe39
AZ		 701}
702
9312805d 703static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
c227f099 704 target_phys_addr_t addr, int *miny, int *maxy)
a171fe39 705{
714fa308 706 int src_width, dest_width;
b9d38e95 707 drawfn fn = NULL;
a171fe39
AZ		 708 if (s->dest_width)
709 fn = s->line_fn[s->transp][s->bpp];
710 if (!fn)
711 return;
712
a171fe39
AZ		 713 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
714 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
715 src_width *= 3;
716 else if (s->bpp > pxa_lcdc_16bpp)
717 src_width *= 4;
718 else if (s->bpp > pxa_lcdc_8bpp)
719 src_width *= 2;
720
721 dest_width = s->yres * s->dest_width;
714fa308 722 *miny = 0;
75c9d6c2 723 framebuffer_update_display(s->ds, s->sysmem,
714fa308
PB		 724 addr, s->xres, s->yres,
725 src_width, s->dest_width, -dest_width,
726 s->invalidated,
727 fn, s->dma_ch[0].palette,
728 miny, maxy);
a171fe39
AZ		 729}
730
9312805d
VK		 731static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
732 target_phys_addr_t addr, int *miny, int *maxy)
733{
734 int src_width, dest_width;
735 drawfn fn = NULL;
736 if (s->dest_width) {
737 fn = s->line_fn[s->transp][s->bpp];
738 }
739 if (!fn) {
740 return;
741 }
742
743 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
744 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
745 src_width *= 3;
746 } else if (s->bpp > pxa_lcdc_16bpp) {
747 src_width *= 4;
748 } else if (s->bpp > pxa_lcdc_8bpp) {
749 src_width *= 2;
750 }
751
752 dest_width = s->xres * s->dest_width;
753 *miny = 0;
75c9d6c2 754 framebuffer_update_display(s->ds, s->sysmem,
9312805d
VK		 755 addr, s->xres, s->yres,
756 src_width, -dest_width, -s->dest_width,
757 s->invalidated,
758 fn, s->dma_ch[0].palette, miny, maxy);
759}
760
761static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
762 target_phys_addr_t addr, int *miny, int *maxy)
763{
764 int src_width, dest_width;
765 drawfn fn = NULL;
766 if (s->dest_width) {
767 fn = s->line_fn[s->transp][s->bpp];
768 }
769 if (!fn) {
770 return;
771 }
772
773 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
774 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
775 src_width *= 3;
776 } else if (s->bpp > pxa_lcdc_16bpp) {
777 src_width *= 4;
778 } else if (s->bpp > pxa_lcdc_8bpp) {
779 src_width *= 2;
780 }
781
782 dest_width = s->yres * s->dest_width;
783 *miny = 0;
75c9d6c2 784 framebuffer_update_display(s->ds, s->sysmem,
9312805d
VK		 785 addr, s->xres, s->yres,
786 src_width, -s->dest_width, dest_width,
787 s->invalidated,
788 fn, s->dma_ch[0].palette,
789 miny, maxy);
790}
791
bc24a225 792static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
a171fe39
AZ		 793{
794 int width, height;
795 if (!(s->control[0] & LCCR0_ENB))
796 return;
797
798 width = LCCR1_PPL(s->control[1]) + 1;
799 height = LCCR2_LPP(s->control[2]) + 1;
800
801 if (width != s->xres || height != s->yres) {
9312805d 802 if (s->orientation == 90 || s->orientation == 270) {
3023f332 803 qemu_console_resize(s->ds, height, width);
9312805d 804 } else {
3023f332 805 qemu_console_resize(s->ds, width, height);
9312805d 806 }
a171fe39
AZ		 807 s->invalidated = 1;
808 s->xres = width;
809 s->yres = height;
810 }
811}
812
813static void pxa2xx_update_display(void *opaque)
814{
bc24a225 815 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
c227f099 816 target_phys_addr_t fbptr;
a171fe39
AZ		 817 int miny, maxy;
818 int ch;
819 if (!(s->control[0] & LCCR0_ENB))
820 return;
821
822 pxa2xx_descriptor_load(s);
823
824 pxa2xx_lcdc_resize(s);
825 miny = s->yres;
826 maxy = 0;
827 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
828 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
829 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
830 if (s->dma_ch[ch].up) {
831 if (!s->dma_ch[ch].source) {
832 pxa2xx_dma_ber_set(s, ch);
833 continue;
834 }
835 fbptr = s->dma_ch[ch].source;
4f56da61
VK		 836 if (!((fbptr >= PXA2XX_SDRAM_BASE &&
837 fbptr <= PXA2XX_SDRAM_BASE + ram_size) ||
838 (fbptr >= PXA2XX_INTERNAL_BASE &&
839 fbptr <= PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
a171fe39
AZ		 840 pxa2xx_dma_ber_set(s, ch);
841 continue;
842 }
a171fe39
AZ		 843
844 if (s->dma_ch[ch].command & LDCMD_PAL) {
714fa308
PB		 845 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
846 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
847 sizeof(s->dma_ch[ch].pbuffer)));
a171fe39
AZ		 848 pxa2xx_palette_parse(s, ch, s->bpp);
849 } else {
850 /* Do we need to reparse palette */
851 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
852 pxa2xx_palette_parse(s, ch, s->bpp);
853
854 /* ACK frame start */
855 pxa2xx_dma_sof_set(s, ch);
856
714fa308 857 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
a171fe39
AZ		 858 s->invalidated = 0;
859
860 /* ACK frame completed */
861 pxa2xx_dma_eof_set(s, ch);
862 }
863 }
864
865 if (s->control[0] & LCCR0_DIS) {
866 /* ACK last frame completed */
867 s->control[0] &= ~LCCR0_ENB;
868 s->status[0] |= LCSR0_LDD;
869 }
870
714fa308 871 if (miny >= 0) {
9312805d
VK		 872 switch (s->orientation) {
873 case 0:
874 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
875 break;
876 case 90:
877 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
878 break;
879 case 180:
880 maxy = s->yres - maxy - 1;
881 miny = s->yres - miny - 1;
882 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
883 break;
884 case 270:
885 maxy = s->yres - maxy - 1;
886 miny = s->yres - miny - 1;
887 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
888 break;
889 }
714fa308 890 }
a171fe39
AZ		 891 pxa2xx_lcdc_int_update(s);
892
38641a52 893 qemu_irq_raise(s->vsync_cb);
a171fe39
AZ		 894}
895
896static void pxa2xx_invalidate_display(void *opaque)
897{
bc24a225 898 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39
AZ		 899 s->invalidated = 1;
900}
901
9596ebb7 902static void pxa2xx_lcdc_orientation(void *opaque, int angle)
a171fe39 903{
bc24a225 904 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
a171fe39 905
9312805d
VK		 906 switch (angle) {
907 case 0:
908 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
909 break;
910 case 90:
911 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
912 break;
913 case 180:
914 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
915 break;
916 case 270:
917 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
918 break;
a171fe39
AZ		 919 }
920
921 s->orientation = angle;
922 s->xres = s->yres = -1;
923 pxa2xx_lcdc_resize(s);
924}
925
99838363
JQ		 926static const VMStateDescription vmstate_dma_channel = {
927 .name = "dma_channel",
928 .version_id = 0,
929 .minimum_version_id = 0,
930 .minimum_version_id_old = 0,
931 .fields = (VMStateField[]) {
27424dcc 932 VMSTATE_UINT32(branch, struct DMAChannel),
99838363
JQ		 933 VMSTATE_UINT8(up, struct DMAChannel),
934 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
27424dcc
MI		 935 VMSTATE_UINT32(descriptor, struct DMAChannel),
936 VMSTATE_UINT32(source, struct DMAChannel),
99838363
JQ		 937 VMSTATE_UINT32(id, struct DMAChannel),
938 VMSTATE_UINT32(command, struct DMAChannel),
939 VMSTATE_END_OF_LIST()
aa941b94 940 }
99838363 941};
aa941b94 942
99838363 943static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
aa941b94 944{
99838363 945 PXA2xxLCDState *s = opaque;
aa941b94
AZ		 946
947 s->bpp = LCCR3_BPP(s->control[3]);
948 s->xres = s->yres = s->pal_for = -1;
949
950 return 0;
951}
952
99838363
JQ		 953static const VMStateDescription vmstate_pxa2xx_lcdc = {
954 .name = "pxa2xx_lcdc",
955 .version_id = 0,
956 .minimum_version_id = 0,
957 .minimum_version_id_old = 0,
958 .post_load = pxa2xx_lcdc_post_load,
959 .fields = (VMStateField[]) {
960 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
961 VMSTATE_INT32(transp, PXA2xxLCDState),
962 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
963 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
964 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
965 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
966 VMSTATE_UINT32(ccr, PXA2xxLCDState),
967 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
968 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
969 VMSTATE_UINT32(tcr, PXA2xxLCDState),
970 VMSTATE_UINT32(liidr, PXA2xxLCDState),
971 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
972 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
973 vmstate_dma_channel, struct DMAChannel),
974 VMSTATE_END_OF_LIST()
975 }
976};
977
a171fe39
AZ		 978#define BITS 8
979#include "pxa2xx_template.h"
980#define BITS 15
981#include "pxa2xx_template.h"
982#define BITS 16
983#include "pxa2xx_template.h"
984#define BITS 24
985#include "pxa2xx_template.h"
986#define BITS 32
987#include "pxa2xx_template.h"
988
5a6fdd91
BC		 989PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
990 target_phys_addr_t base, qemu_irq irq)
a171fe39 991{
bc24a225 992 PXA2xxLCDState *s;
a171fe39 993
7267c094 994 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
a171fe39
AZ		 995 s->invalidated = 1;
996 s->irq = irq;
75c9d6c2 997 s->sysmem = sysmem;
a171fe39
AZ		 998
999 pxa2xx_lcdc_orientation(s, graphic_rotate);
1000
5a6fdd91
BC		 1001 memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
1002 "pxa2xx-lcd-controller", 0x00100000);
1003 memory_region_add_subregion(sysmem, base, &s->iomem);
a171fe39 1004
3023f332
AL		 1005 s->ds = graphic_console_init(pxa2xx_update_display,
1006 pxa2xx_invalidate_display,
16735102 1007 NULL, NULL, s);
a171fe39 1008
0e1f5a0c 1009 switch (ds_get_bits_per_pixel(s->ds)) {
a171fe39
AZ		 1010 case 0:
1011 s->dest_width = 0;
1012 break;
1013 case 8:
1014 s->line_fn[0] = pxa2xx_draw_fn_8;
1015 s->line_fn[1] = pxa2xx_draw_fn_8t;
1016 s->dest_width = 1;
1017 break;
1018 case 15:
1019 s->line_fn[0] = pxa2xx_draw_fn_15;
1020 s->line_fn[1] = pxa2xx_draw_fn_15t;
1021 s->dest_width = 2;
1022 break;
1023 case 16:
1024 s->line_fn[0] = pxa2xx_draw_fn_16;
1025 s->line_fn[1] = pxa2xx_draw_fn_16t;
1026 s->dest_width = 2;
1027 break;
1028 case 24:
1029 s->line_fn[0] = pxa2xx_draw_fn_24;
1030 s->line_fn[1] = pxa2xx_draw_fn_24t;
1031 s->dest_width = 3;
1032 break;
1033 case 32:
1034 s->line_fn[0] = pxa2xx_draw_fn_32;
1035 s->line_fn[1] = pxa2xx_draw_fn_32t;
1036 s->dest_width = 4;
1037 break;
1038 default:
1039 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1040 exit(1);
1041 }
aa941b94 1042
99838363 1043 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
aa941b94 1044
a171fe39
AZ		 1045 return s;
1046}
1047
bc24a225 1048void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
38641a52
AZ		 1049{
1050 s->vsync_cb = handler;
a171fe39 1051}
Qemu copy for testing