[qemu.git] / hw / pxa2xx_pic.c

/*
 * Intel XScale PXA Programmable Interrupt Controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "pxa.h"
#include "sysbus.h"

#define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
#define ICMR	0x04	/* Interrupt Controller Mask register */
#define ICLR	0x08	/* Interrupt Controller Level register */
#define ICFP	0x0c	/* Interrupt Controller FIQ Pending register */
#define ICPR	0x10	/* Interrupt Controller Pending register */
#define ICCR	0x14	/* Interrupt Controller Control register */
#define ICHP	0x18	/* Interrupt Controller Highest Priority register */
#define IPR0	0x1c	/* Interrupt Controller Priority register 0 */
#define IPR31	0x98	/* Interrupt Controller Priority register 31 */
#define ICIP2	0x9c	/* Interrupt Controller IRQ Pending register 2 */
#define ICMR2	0xa0	/* Interrupt Controller Mask register 2 */
#define ICLR2	0xa4	/* Interrupt Controller Level register 2 */
#define ICFP2	0xa8	/* Interrupt Controller FIQ Pending register 2 */
#define ICPR2	0xac	/* Interrupt Controller Pending register 2 */
#define IPR32	0xb0	/* Interrupt Controller Priority register 32 */
#define IPR39	0xcc	/* Interrupt Controller Priority register 39 */

#define PXA2XX_PIC_SRCS	40

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    ARMCPU *cpu;
    uint32_t int_enabled[2];
    uint32_t int_pending[2];
    uint32_t is_fiq[2];
    uint32_t int_idle;
    uint32_t priority[PXA2XX_PIC_SRCS];
} PXA2xxPICState;

static void pxa2xx_pic_update(void *opaque)
{
    uint32_t mask[2];
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;

    if (s->cpu->env.halted) {
        mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
        mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
        if (mask[0] || mask[1]) {
            cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
        }
    }

    mask[0] = s->int_pending[0] & s->int_enabled[0];
    mask[1] = s->int_pending[1] & s->int_enabled[1];

    if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
    } else {
        cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
    }

    if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
    }
}

/* Note: Here level means state of the signal on a pin, not
 * IRQ/FIQ distinction as in PXA Developer Manual.  */
static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
    int int_set = (irq >= 32);
    irq &= 31;

    if (level)
        s->int_pending[int_set] |= 1 << irq;
    else
        s->int_pending[int_set] &= ~(1 << irq);

    pxa2xx_pic_update(opaque);
}

static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
    int i, int_set, irq;
    uint32_t bit, mask[2];
    uint32_t ichp = 0x003f003f;	/* Both IDs invalid */

    mask[0] = s->int_pending[0] & s->int_enabled[0];
    mask[1] = s->int_pending[1] & s->int_enabled[1];

    for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
        irq = s->priority[i] & 0x3f;
        if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
            /* Source peripheral ID is valid.  */
            bit = 1 << (irq & 31);
            int_set = (irq >= 32);

            if (mask[int_set] & bit & s->is_fiq[int_set]) {
                /* FIQ asserted */
                ichp &= 0xffff0000;
                ichp |= (1 << 15) | irq;
            }

            if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
                /* IRQ asserted */
                ichp &= 0x0000ffff;
                ichp |= (1 << 31) | (irq << 16);
            }
        }
    }

    return ichp;
}

static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
                                    unsigned size)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;

    switch (offset) {
    case ICIP:	/* IRQ Pending register */
        return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
    case ICIP2:	/* IRQ Pending register 2 */
        return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
    case ICMR:	/* Mask register */
        return s->int_enabled[0];
    case ICMR2:	/* Mask register 2 */
        return s->int_enabled[1];
    case ICLR:	/* Level register */
        return s->is_fiq[0];
    case ICLR2:	/* Level register 2 */
        return s->is_fiq[1];
    case ICCR:	/* Idle mask */
        return (s->int_idle == 0);
    case ICFP:	/* FIQ Pending register */
        return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
    case ICFP2:	/* FIQ Pending register 2 */
        return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
    case ICPR:	/* Pending register */
        return s->int_pending[0];
    case ICPR2:	/* Pending register 2 */
        return s->int_pending[1];
    case IPR0  ... IPR31:
        return s->priority[0  + ((offset - IPR0 ) >> 2)];
    case IPR32 ... IPR39:
        return s->priority[32 + ((offset - IPR32) >> 2)];
    case ICHP:	/* Highest Priority register */
        return pxa2xx_pic_highest(s);
    default:
        printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
        return 0;
    }
}

static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
                                 uint64_t value, unsigned size)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;

    switch (offset) {
    case ICMR:	/* Mask register */
        s->int_enabled[0] = value;
        break;
    case ICMR2:	/* Mask register 2 */
        s->int_enabled[1] = value;
        break;
    case ICLR:	/* Level register */
        s->is_fiq[0] = value;
        break;
    case ICLR2:	/* Level register 2 */
        s->is_fiq[1] = value;
        break;
    case ICCR:	/* Idle mask */
        s->int_idle = (value & 1) ? 0 : ~0;
        break;
    case IPR0  ... IPR31:
        s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
        break;
    case IPR32 ... IPR39:
        s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
        break;
    default:
        printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
        return;
    }
    pxa2xx_pic_update(opaque);
}

/* Interrupt Controller Coprocessor Space Register Mapping */
static const int pxa2xx_cp_reg_map[0x10] = {
    [0x0 ... 0xf] = -1,
    [0x0] = ICIP,
    [0x1] = ICMR,
    [0x2] = ICLR,
    [0x3] = ICFP,
    [0x4] = ICPR,
    [0x5] = ICHP,
    [0x6] = ICIP2,
    [0x7] = ICMR2,
    [0x8] = ICLR2,
    [0x9] = ICFP2,
    [0xa] = ICPR2,
};

static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t *value)
{
    int offset = pxa2xx_cp_reg_map[ri->crn];
    *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
    return 0;
}

static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                               uint64_t value)
{
    int offset = pxa2xx_cp_reg_map[ri->crn];
    pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
    return 0;
}

#define REGINFO_FOR_PIC_CP(NAME, CRN) \
    { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
      .access = PL1_RW, \
      .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }

static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
    REGINFO_FOR_PIC_CP("ICIP", 0),
    REGINFO_FOR_PIC_CP("ICMR", 1),
    REGINFO_FOR_PIC_CP("ICLR", 2),
    REGINFO_FOR_PIC_CP("ICFP", 3),
    REGINFO_FOR_PIC_CP("ICPR", 4),
    REGINFO_FOR_PIC_CP("ICHP", 5),
    REGINFO_FOR_PIC_CP("ICIP2", 6),
    REGINFO_FOR_PIC_CP("ICMR2", 7),
    REGINFO_FOR_PIC_CP("ICLR2", 8),
    REGINFO_FOR_PIC_CP("ICFP2", 9),
    REGINFO_FOR_PIC_CP("ICPR2", 0xa),
    REGINFO_SENTINEL
};

static const MemoryRegionOps pxa2xx_pic_ops = {
    .read = pxa2xx_pic_mem_read,
    .write = pxa2xx_pic_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pxa2xx_pic_post_load(void *opaque, int version_id)
{
    pxa2xx_pic_update(opaque);
    return 0;
}

DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
    CPUARMState *env = &cpu->env;
    DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
    PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));

    s->cpu = cpu;

    s->int_pending[0] = 0;
    s->int_pending[1] = 0;
    s->int_enabled[0] = 0;
    s->int_enabled[1] = 0;
    s->is_fiq[0] = 0;
    s->is_fiq[1] = 0;

    qdev_init_nofail(dev);

    qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);

    /* Enable IC memory-mapped registers access.  */
    memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
                          "pxa2xx-pic", 0x00100000);
    sysbus_init_mmio(sysbus_from_qdev(dev), &s->iomem);
    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);

    /* Enable IC coprocessor access.  */
    define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);

    return dev;
}

static VMStateDescription vmstate_pxa2xx_pic_regs = {
    .name = "pxa2xx_pic",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .post_load = pxa2xx_pic_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
        VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
        VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
        VMSTATE_UINT32(int_idle, PXA2xxPICState),
        VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
        VMSTATE_END_OF_LIST(),
    },
};

static int pxa2xx_pic_initfn(SysBusDevice *dev)
{
    return 0;
}

static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_pic_initfn;
    dc->desc = "PXA2xx PIC";
    dc->vmsd = &vmstate_pxa2xx_pic_regs;
}

static const TypeInfo pxa2xx_pic_info = {
    .name          = "pxa2xx_pic",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxPICState),
    .class_init    = pxa2xx_pic_class_init,
};

static void pxa2xx_pic_register_types(void)
{
    type_register_static(&pxa2xx_pic_info);
}

type_init(pxa2xx_pic_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA Programmable Interrupt Controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <balrog@zabor.org>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
87ecb68b PB	11	#include "hw.h"
87ecb68b PB	12	#include "pxa.h"
e1f8c729	13	#include "sysbus.h"
c1713132 AZ	14
	15	#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
	16	#define ICMR 0x04 /* Interrupt Controller Mask register */
	17	#define ICLR 0x08 /* Interrupt Controller Level register */
	18	#define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
	19	#define ICPR 0x10 /* Interrupt Controller Pending register */
	20	#define ICCR 0x14 /* Interrupt Controller Control register */
	21	#define ICHP 0x18 /* Interrupt Controller Highest Priority register */
	22	#define IPR0 0x1c /* Interrupt Controller Priority register 0 */
	23	#define IPR31 0x98 /* Interrupt Controller Priority register 31 */
	24	#define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
	25	#define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
	26	#define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
	27	#define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
	28	#define ICPR2 0xac /* Interrupt Controller Pending register 2 */
	29	#define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
	30	#define IPR39 0xcc /* Interrupt Controller Priority register 39 */
	31
	32	#define PXA2XX_PIC_SRCS 40
	33
bc24a225	34	typedef struct {
e1f8c729	35	SysBusDevice busdev;
90e8e5a3	36	MemoryRegion iomem;
e9d872cf	37	ARMCPU *cpu;
c1713132 AZ	38	uint32_t int_enabled[2];
	39	uint32_t int_pending[2];
	40	uint32_t is_fiq[2];
	41	uint32_t int_idle;
	42	uint32_t priority[PXA2XX_PIC_SRCS];
bc24a225	43	} PXA2xxPICState;
c1713132 AZ	44
	45	static void pxa2xx_pic_update(void *opaque)
	46	{
	47	uint32_t mask[2];
bc24a225	48	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132	49
e9d872cf	50	if (s->cpu->env.halted) {
c1713132 AZ	51	mask[0] = s->int_pending[0] & (s->int_enabled[0] \| s->int_idle);
c1713132 AZ	52	mask[1] = s->int_pending[1] & (s->int_enabled[1] \| s->int_idle);
e9d872cf AF	53	if (mask[0] \|\| mask[1]) {
	54	cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
	55	}
c1713132 AZ	56	}
	57
	58	mask[0] = s->int_pending[0] & s->int_enabled[0];
	59	mask[1] = s->int_pending[1] & s->int_enabled[1];
	60
e9d872cf AF	61	if ((mask[0] & s->is_fiq[0]) \|\| (mask[1] & s->is_fiq[1])) {
	62	cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
	63	} else {
	64	cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
	65	}
c1713132	66
e9d872cf AF	67	if ((mask[0] & ~s->is_fiq[0]) \|\| (mask[1] & ~s->is_fiq[1])) {
	68	cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
	69	} else {
	70	cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
	71	}
c1713132 AZ	72	}
	73
	74	/* Note: Here level means state of the signal on a pin, not
	75	* IRQ/FIQ distinction as in PXA Developer Manual. */
	76	static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
	77	{
bc24a225	78	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	79	int int_set = (irq >= 32);
	80	irq &= 31;
	81
	82	if (level)
	83	s->int_pending[int_set] \|= 1 << irq;
	84	else
	85	s->int_pending[int_set] &= ~(1 << irq);
	86
	87	pxa2xx_pic_update(opaque);
	88	}
	89
bc24a225	90	static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
c1713132 AZ	91	int i, int_set, irq;
	92	uint32_t bit, mask[2];
	93	uint32_t ichp = 0x003f003f; /* Both IDs invalid */
	94
	95	mask[0] = s->int_pending[0] & s->int_enabled[0];
	96	mask[1] = s->int_pending[1] & s->int_enabled[1];
	97
	98	for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
	99	irq = s->priority[i] & 0x3f;
	100	if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
	101	/* Source peripheral ID is valid. */
	102	bit = 1 << (irq & 31);
	103	int_set = (irq >= 32);
	104
	105	if (mask[int_set] & bit & s->is_fiq[int_set]) {
	106	/* FIQ asserted */
	107	ichp &= 0xffff0000;
	108	ichp \|= (1 << 15) \| irq;
	109	}
	110
	111	if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
	112	/* IRQ asserted */
	113	ichp &= 0x0000ffff;
	114	ichp \|= (1 << 31) \| (irq << 16);
	115	}
	116	}
	117	}
	118
	119	return ichp;
	120	}
	121
a8170e5e	122	static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
90e8e5a3	123	unsigned size)
c1713132	124	{
bc24a225	125	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	126
	127	switch (offset) {
	128	case ICIP: /* IRQ Pending register */
	129	return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
	130	case ICIP2: /* IRQ Pending register 2 */
	131	return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
	132	case ICMR: /* Mask register */
	133	return s->int_enabled[0];
	134	case ICMR2: /* Mask register 2 */
	135	return s->int_enabled[1];
	136	case ICLR: /* Level register */
	137	return s->is_fiq[0];
	138	case ICLR2: /* Level register 2 */
	139	return s->is_fiq[1];
	140	case ICCR: /* Idle mask */
	141	return (s->int_idle == 0);
	142	case ICFP: /* FIQ Pending register */
	143	return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
	144	case ICFP2: /* FIQ Pending register 2 */
	145	return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
	146	case ICPR: /* Pending register */
	147	return s->int_pending[0];
	148	case ICPR2: /* Pending register 2 */
	149	return s->int_pending[1];
	150	case IPR0 ... IPR31:
	151	return s->priority[0 + ((offset - IPR0 ) >> 2)];
	152	case IPR32 ... IPR39:
	153	return s->priority[32 + ((offset - IPR32) >> 2)];
	154	case ICHP: /* Highest Priority register */
	155	return pxa2xx_pic_highest(s);
	156	default:
	157	printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
	158	return 0;
	159	}
	160	}
	161
a8170e5e	162	static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
90e8e5a3	163	uint64_t value, unsigned size)
c1713132	164	{
bc24a225	165	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	166
	167	switch (offset) {
	168	case ICMR: /* Mask register */
	169	s->int_enabled[0] = value;
	170	break;
	171	case ICMR2: /* Mask register 2 */
	172	s->int_enabled[1] = value;
	173	break;
	174	case ICLR: /* Level register */
	175	s->is_fiq[0] = value;
	176	break;
	177	case ICLR2: /* Level register 2 */
	178	s->is_fiq[1] = value;
	179	break;
	180	case ICCR: /* Idle mask */
	181	s->int_idle = (value & 1) ? 0 : ~0;
	182	break;
	183	case IPR0 ... IPR31:
	184	s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
	185	break;
	186	case IPR32 ... IPR39:
	187	s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
	188	break;
	189	default:
	190	printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
	191	return;
	192	}
	193	pxa2xx_pic_update(opaque);
	194	}
	195
	196	/* Interrupt Controller Coprocessor Space Register Mapping */
	197	static const int pxa2xx_cp_reg_map[0x10] = {
	198	[0x0 ... 0xf] = -1,
	199	[0x0] = ICIP,
	200	[0x1] = ICMR,
	201	[0x2] = ICLR,
	202	[0x3] = ICFP,
	203	[0x4] = ICPR,
	204	[0x5] = ICHP,
	205	[0x6] = ICIP2,
	206	[0x7] = ICMR2,
	207	[0x8] = ICLR2,
	208	[0x9] = ICFP2,
	209	[0xa] = ICPR2,
	210	};
	211
9ee703b0 PM	212	static int pxa2xx_pic_cp_read(CPUARMState env, const ARMCPRegInfo ri,
9ee703b0 PM	213	uint64_t *value)
c1713132	214	{
9ee703b0 PM	215	int offset = pxa2xx_cp_reg_map[ri->crn];
	216	*value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
	217	return 0;
c1713132 AZ	218	}
c1713132 AZ	219
9ee703b0 PM	220	static int pxa2xx_pic_cp_write(CPUARMState env, const ARMCPRegInfo ri,
9ee703b0 PM	221	uint64_t value)
c1713132	222	{
9ee703b0 PM	223	int offset = pxa2xx_cp_reg_map[ri->crn];
	224	pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
	225	return 0;
c1713132 AZ	226	}
c1713132 AZ	227
9ee703b0 PM	228	#define REGINFO_FOR_PIC_CP(NAME, CRN) \
	229	{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
	230	.access = PL1_RW, \
	231	.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
	232
	233	static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
	234	REGINFO_FOR_PIC_CP("ICIP", 0),
	235	REGINFO_FOR_PIC_CP("ICMR", 1),
	236	REGINFO_FOR_PIC_CP("ICLR", 2),
	237	REGINFO_FOR_PIC_CP("ICFP", 3),
	238	REGINFO_FOR_PIC_CP("ICPR", 4),
	239	REGINFO_FOR_PIC_CP("ICHP", 5),
	240	REGINFO_FOR_PIC_CP("ICIP2", 6),
	241	REGINFO_FOR_PIC_CP("ICMR2", 7),
	242	REGINFO_FOR_PIC_CP("ICLR2", 8),
	243	REGINFO_FOR_PIC_CP("ICFP2", 9),
	244	REGINFO_FOR_PIC_CP("ICPR2", 0xa),
	245	REGINFO_SENTINEL
	246	};
	247
90e8e5a3 BC	248	static const MemoryRegionOps pxa2xx_pic_ops = {
	249	.read = pxa2xx_pic_mem_read,
	250	.write = pxa2xx_pic_mem_write,
	251	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	252	};
c1713132 AZ	253
e1f8c729	254	static int pxa2xx_pic_post_load(void *opaque, int version_id)
aa941b94	255	{
aa941b94 AZ	256	pxa2xx_pic_update(opaque);
	257	return 0;
	258	}
	259
a8170e5e	260	DeviceState pxa2xx_pic_init(hwaddr base, ARMCPU cpu)
c1713132	261	{
f161bcd0	262	CPUARMState *env = &cpu->env;
e1f8c729	263	DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
e1f8c729	264	PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
c1713132	265
e9d872cf	266	s->cpu = cpu;
c1713132 AZ	267
	268	s->int_pending[0] = 0;
	269	s->int_pending[1] = 0;
	270	s->int_enabled[0] = 0;
	271	s->int_enabled[1] = 0;
	272	s->is_fiq[0] = 0;
	273	s->is_fiq[1] = 0;
	274
e1f8c729 DES	275	qdev_init_nofail(dev);
	276
	277	qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
c1713132 AZ	278
c1713132 AZ	279	/* Enable IC memory-mapped registers access. */
90e8e5a3 BC	280	memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
90e8e5a3 BC	281	"pxa2xx-pic", 0x00100000);
750ecd44	282	sysbus_init_mmio(sysbus_from_qdev(dev), &s->iomem);
7c29d6ce	283	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
c1713132 AZ	284
c1713132 AZ	285	/* Enable IC coprocessor access. */
9ee703b0	286	define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);
c1713132	287
e1f8c729 DES	288	return dev;
	289	}
	290
	291	static VMStateDescription vmstate_pxa2xx_pic_regs = {
	292	.name = "pxa2xx_pic",
	293	.version_id = 0,
	294	.minimum_version_id = 0,
	295	.minimum_version_id_old = 0,
	296	.post_load = pxa2xx_pic_post_load,
	297	.fields = (VMStateField[]) {
	298	VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
	299	VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
	300	VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
	301	VMSTATE_UINT32(int_idle, PXA2xxPICState),
	302	VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
	303	VMSTATE_END_OF_LIST(),
	304	},
	305	};
aa941b94	306
e1f8c729 DES	307	static int pxa2xx_pic_initfn(SysBusDevice *dev)
	308	{
	309	return 0;
	310	}
	311
999e12bb AL	312	static void pxa2xx_pic_class_init(ObjectClass klass, void data)
999e12bb AL	313	{
39bffca2	314	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	315	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	316
	317	k->init = pxa2xx_pic_initfn;
39bffca2 AL	318	dc->desc = "PXA2xx PIC";
39bffca2 AL	319	dc->vmsd = &vmstate_pxa2xx_pic_regs;
999e12bb AL	320	}
999e12bb AL	321
8c43a6f0	322	static const TypeInfo pxa2xx_pic_info = {
39bffca2 AL	323	.name = "pxa2xx_pic",
	324	.parent = TYPE_SYS_BUS_DEVICE,
	325	.instance_size = sizeof(PXA2xxPICState),
	326	.class_init = pxa2xx_pic_class_init,
e1f8c729 DES	327	};
e1f8c729 DES	328
83f7d43a	329	static void pxa2xx_pic_register_types(void)
e1f8c729	330	{
39bffca2	331	type_register_static(&pxa2xx_pic_info);
c1713132	332	}
83f7d43a AF	333
83f7d43a AF	334	type_init(pxa2xx_pic_register_types)