[qemu.git] / hw / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licenced under the GPL.
 */

#include "vl.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

struct pxa2xx_timer0_s {
    uint32_t value;
    int level;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    void *info;
};

struct pxa2xx_timer4_s {
    struct pxa2xx_timer0_s tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
};

typedef struct {
    target_phys_addr_t base;
    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    struct pxa2xx_timer0_s timer[4];
    struct pxa2xx_timer4_s *tm4;
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;
} pxa2xx_timer_info;

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        ticks_per_sec, s->freq);
        qemu_mod_timer(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        qemu_del_timer(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, ticks_per_sec);

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    ticks_per_sec, s->tm4[counter].freq);
    qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}

static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
{
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
    int tm = 0;

    offset -= s->base;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!s->tm4)
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_get_clock(vm_clock) -
                        s->lastload, s->freq, ticks_per_sec);
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!s->tm4)
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_get_clock(vm_clock) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, ticks_per_sec);
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
                        s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm ++;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!s->tm4)
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
                        REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
                uint32_t value)
{
    int i, tm = 0;
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;

    offset -= s->base;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
        break;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_get_clock(vm_clock);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_get_clock(vm_clock);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1) {
            if (s->timer[i].level && (value & 1)) {
                s->timer[i].level = 0;
                qemu_irq_lower(s->timer[i].irq);
            }
        }
        if (s->tm4) {
            for (i = 0; i < 8; i ++, value >>= 1)
                if (s->tm4[i].tm.level && (value & 1))
                    s->tm4[i].tm.level = 0;
            if (!(s->events & 0xff0))
                qemu_irq_lower(s->tm4->tm.irq);
        }
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        }
        break;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm += 4;
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        }
        break;
    default:
    badreg:
        cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
                        REG_FMT "\n", offset);
    }
}

static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
    pxa2xx_timer_read,
    pxa2xx_timer_read,
    pxa2xx_timer_read,
};

static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
    pxa2xx_timer_write,
    pxa2xx_timer_write,
    pxa2xx_timer_write,
};

static void pxa2xx_timer_tick(void *opaque)
{
    struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
    pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;

    if (i->irq_enabled & (1 << t->num)) {
        t->level = 1;
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
    pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
}

static void pxa2xx_timer_save(QEMUFile *f, void *opaque)
{
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
    int i;

    qemu_put_be32s(f, &s->clock);
    qemu_put_be32s(f, &s->oldclock);
    qemu_put_be64s(f, &s->lastload);

    for (i = 0; i < 4; i ++) {
        qemu_put_be32s(f, &s->timer[i].value);
        qemu_put_be32(f, s->timer[i].level);
    }
    if (s->tm4)
        for (i = 0; i < 8; i ++) {
            qemu_put_be32s(f, &s->tm4[i].tm.value);
            qemu_put_be32(f, s->tm4[i].tm.level);
            qemu_put_be32s(f, &s->tm4[i].oldclock);
            qemu_put_be32s(f, &s->tm4[i].clock);
            qemu_put_be64s(f, &s->tm4[i].lastload);
            qemu_put_be32s(f, &s->tm4[i].freq);
            qemu_put_be32s(f, &s->tm4[i].control);
        }

    qemu_put_be32s(f, &s->events);
    qemu_put_be32s(f, &s->irq_enabled);
    qemu_put_be32s(f, &s->reset3);
    qemu_put_be32s(f, &s->snapshot);
}

static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
    int64_t now;
    int i;

    qemu_get_be32s(f, &s->clock);
    qemu_get_be32s(f, &s->oldclock);
    qemu_get_be64s(f, &s->lastload);

    now = qemu_get_clock(vm_clock);
    for (i = 0; i < 4; i ++) {
        qemu_get_be32s(f, &s->timer[i].value);
        s->timer[i].level = qemu_get_be32(f);
    }
    pxa2xx_timer_update(s, now);

    if (s->tm4)
        for (i = 0; i < 8; i ++) {
            qemu_get_be32s(f, &s->tm4[i].tm.value);
            s->tm4[i].tm.level = qemu_get_be32(f);
            qemu_get_be32s(f, &s->tm4[i].oldclock);
            qemu_get_be32s(f, &s->tm4[i].clock);
            qemu_get_be64s(f, &s->tm4[i].lastload);
            qemu_get_be32s(f, &s->tm4[i].freq);
            qemu_get_be32s(f, &s->tm4[i].control);
            pxa2xx_timer_update4(s, now, i);
        }

    qemu_get_be32s(f, &s->events);
    qemu_get_be32s(f, &s->irq_enabled);
    qemu_get_be32s(f, &s->reset3);
    qemu_get_be32s(f, &s->snapshot);

    return 0;
}

static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
                qemu_irq *irqs)
{
    int i;
    int iomemtype;
    pxa2xx_timer_info *s;

    s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
    s->base = base;
    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_get_clock(vm_clock);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        s->timer[i].irq = irqs[i];
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].level = 0;
        s->timer[i].qtimer = qemu_new_timer(vm_clock,
                        pxa2xx_timer_tick, &s->timer[i]);
    }

    iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
                    pxa2xx_timer_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    register_savevm("pxa2xx_timer", 0, 0,
                    pxa2xx_timer_save, pxa2xx_timer_load, s);

    return s;
}

void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
{
    pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
    s->freq = PXA25X_FREQ;
    s->tm4 = 0;
}

void pxa27x_timer_init(target_phys_addr_t base,
                qemu_irq *irqs, qemu_irq irq4)
{
    pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
    int i;
    s->freq = PXA27X_FREQ;
    s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
                    sizeof(struct pxa2xx_timer4_s));
    for (i = 0; i < 8; i ++) {
        s->tm4[i].tm.value = 0;
        s->tm4[i].tm.irq = irq4;
        s->tm4[i].tm.info = s;
        s->tm4[i].tm.num = i + 4;
        s->tm4[i].tm.level = 0;
        s->tm4[i].freq = 0;
        s->tm4[i].control = 0x0;
        s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
                        pxa2xx_timer_tick4, &s->tm4[i]);
    }
}
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
	10	#include "vl.h"
	11
	12	#define OSMR0 0x00
	13	#define OSMR1 0x04
	14	#define OSMR2 0x08
	15	#define OSMR3 0x0c
	16	#define OSMR4 0x80
	17	#define OSMR5 0x84
	18	#define OSMR6 0x88
	19	#define OSMR7 0x8c
	20	#define OSMR8 0x90
	21	#define OSMR9 0x94
	22	#define OSMR10 0x98
	23	#define OSMR11 0x9c
	24	#define OSCR 0x10 /* OS Timer Count */
	25	#define OSCR4 0x40
	26	#define OSCR5 0x44
	27	#define OSCR6 0x48
	28	#define OSCR7 0x4c
	29	#define OSCR8 0x50
	30	#define OSCR9 0x54
	31	#define OSCR10 0x58
	32	#define OSCR11 0x5c
	33	#define OSSR 0x14 /* Timer status register */
	34	#define OWER 0x18
	35	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	36	#define OMCR4 0xc0 /* OS Match Control registers */
	37	#define OMCR5 0xc4
	38	#define OMCR6 0xc8
	39	#define OMCR7 0xcc
	40	#define OMCR8 0xd0
	41	#define OMCR9 0xd4
	42	#define OMCR10 0xd8
	43	#define OMCR11 0xdc
	44	#define OSNR 0x20
	45
	46	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	47	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	48
	49	static int pxa2xx_timer4_freq[8] = {
	50	[0] = 0,
	51	[1] = 32768,
	52	[2] = 1000,
	53	[3] = 1,
	54	[4] = 1000000,
	55	/* [5] is the "Externally supplied clock". Assign if necessary. */
	56	[5 ... 7] = 0,
	57	};
	58
	59	struct pxa2xx_timer0_s {
	60	uint32_t value;
	61	int level;
	62	qemu_irq irq;
	63	QEMUTimer *qtimer;
	64	int num;
65	void *info;
66	};
67
68	struct pxa2xx_timer4_s {
3bdd58a4	69	struct pxa2xx_timer0_s tm;
a171fe39 AZ	70	int32_t oldclock;
	71	int32_t clock;
	72	uint64_t lastload;
	73	uint32_t freq;
	74	uint32_t control;
	75	};
	76
	77	typedef struct {
3f582262	78	target_phys_addr_t base;
a171fe39 AZ	79	int32_t clock;
	80	int32_t oldclock;
	81	uint64_t lastload;
	82	uint32_t freq;
	83	struct pxa2xx_timer0_s timer[4];
	84	struct pxa2xx_timer4_s *tm4;
	85	uint32_t events;
	86	uint32_t irq_enabled;
	87	uint32_t reset3;
a171fe39 AZ	88	uint32_t snapshot;
	89	} pxa2xx_timer_info;
	90
	91	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	92	{
	93	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	94	int i;
	95	uint32_t now_vm;
	96	uint64_t new_qemu;
	97
	98	now_vm = s->clock +
	99	muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);
	100
	101	for (i = 0; i < 4; i ++) {
	102	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
	103	ticks_per_sec, s->freq);
	104	qemu_mod_timer(s->timer[i].qtimer, new_qemu);
	105	}
	106	}
	107
	108	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	109	{
	110	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	111	uint32_t now_vm;
	112	uint64_t new_qemu;
	113	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	114	int counter;
	115
	116	if (s->tm4[n].control & (1 << 7))
	117	counter = n;
	118	else
	119	counter = counters[n];
	120
	121	if (!s->tm4[counter].freq) {
3f582262	122	qemu_del_timer(s->tm4[n].tm.qtimer);
a171fe39 AZ	123	return;
	124	}
	125
	126	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	127	s->tm4[counter].lastload,
	128	s->tm4[counter].freq, ticks_per_sec);
	129
3bdd58a4	130	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
a171fe39	131	ticks_per_sec, s->tm4[counter].freq);
3f582262	132	qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	133	}
	134
	135	static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
	136	{
	137	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	138	int tm = 0;
	139
	140	offset -= s->base;
	141
	142	switch (offset) {
	143	case OSMR3: tm ++;
	144	case OSMR2: tm ++;
	145	case OSMR1: tm ++;
	146	case OSMR0:
	147	return s->timer[tm].value;
	148	case OSMR11: tm ++;
	149	case OSMR10: tm ++;
	150	case OSMR9: tm ++;
	151	case OSMR8: tm ++;
	152	case OSMR7: tm ++;
	153	case OSMR6: tm ++;
	154	case OSMR5: tm ++;
	155	case OSMR4:
	156	if (!s->tm4)
	157	goto badreg;
3bdd58a4	158	return s->tm4[tm].tm.value;
a171fe39 AZ	159	case OSCR:
	160	return s->clock + muldiv64(qemu_get_clock(vm_clock) -
	161	s->lastload, s->freq, ticks_per_sec);
	162	case OSCR11: tm ++;
	163	case OSCR10: tm ++;
	164	case OSCR9: tm ++;
	165	case OSCR8: tm ++;
	166	case OSCR7: tm ++;
	167	case OSCR6: tm ++;
	168	case OSCR5: tm ++;
	169	case OSCR4:
	170	if (!s->tm4)
	171	goto badreg;
	172
	173	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	174	if (s->tm4[tm - 1].freq)
	175	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
	176	qemu_get_clock(vm_clock) -
	177	s->tm4[tm - 1].lastload,
	178	s->tm4[tm - 1].freq, ticks_per_sec);
	179	else
	180	s->snapshot = s->tm4[tm - 1].clock;
	181	}
	182
	183	if (!s->tm4[tm].freq)
	184	return s->tm4[tm].clock;
	185	return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
	186	s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
	187	case OIER:
	188	return s->irq_enabled;
	189	case OSSR: /* Status register */
	190	return s->events;
	191	case OWER:
	192	return s->reset3;
	193	case OMCR11: tm ++;
	194	case OMCR10: tm ++;
	195	case OMCR9: tm ++;
	196	case OMCR8: tm ++;
	197	case OMCR7: tm ++;
	198	case OMCR6: tm ++;
	199	case OMCR5: tm ++;
	200	case OMCR4:
	201	if (!s->tm4)
	202	goto badreg;
	203	return s->tm4[tm].control;
	204	case OSNR:
	205	return s->snapshot;
	206	default:
	207	badreg:
	208	cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
	209	REG_FMT "\n", offset);
	210	}
	211
	212	return 0;
	213	}
	214
	215	static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
	216	uint32_t value)
	217	{
	218	int i, tm = 0;
	219	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	220
	221	offset -= s->base;
	222
223	switch (offset) {
224	case OSMR3: tm ++;
225	case OSMR2: tm ++;
226	case OSMR1: tm ++;
227	case OSMR0:
228	s->timer[tm].value = value;
229	pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
230	break;
231	case OSMR11: tm ++;
232	case OSMR10: tm ++;
233	case OSMR9: tm ++;
234	case OSMR8: tm ++;
235	case OSMR7: tm ++;
236	case OSMR6: tm ++;
237	case OSMR5: tm ++;
238	case OSMR4:
239	if (!s->tm4)
240	goto badreg;
3bdd58a4	241	s->tm4[tm].tm.value = value;
a171fe39 AZ	242	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	243	break;
	244	case OSCR:
	245	s->oldclock = s->clock;
	246	s->lastload = qemu_get_clock(vm_clock);
	247	s->clock = value;
	248	pxa2xx_timer_update(s, s->lastload);
	249	break;
	250	case OSCR11: tm ++;
	251	case OSCR10: tm ++;
	252	case OSCR9: tm ++;
	253	case OSCR8: tm ++;
	254	case OSCR7: tm ++;
	255	case OSCR6: tm ++;
	256	case OSCR5: tm ++;
	257	case OSCR4:
	258	if (!s->tm4)
	259	goto badreg;
	260	s->tm4[tm].oldclock = s->tm4[tm].clock;
	261	s->tm4[tm].lastload = qemu_get_clock(vm_clock);
	262	s->tm4[tm].clock = value;
	263	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	264	break;
	265	case OIER:
	266	s->irq_enabled = value & 0xfff;
	267	break;
	268	case OSSR: /* Status register */
	269	s->events &= ~value;
	270	for (i = 0; i < 4; i ++, value >>= 1) {
	271	if (s->timer[i].level && (value & 1)) {
	272	s->timer[i].level = 0;
	273	qemu_irq_lower(s->timer[i].irq);
	274	}
	275	}
	276	if (s->tm4) {
	277	for (i = 0; i < 8; i ++, value >>= 1)
3bdd58a4 AZ	278	if (s->tm4[i].tm.level && (value & 1))
3bdd58a4 AZ	279	s->tm4[i].tm.level = 0;
a171fe39	280	if (!(s->events & 0xff0))
3bdd58a4	281	qemu_irq_lower(s->tm4->tm.irq);
a171fe39 AZ	282	}
	283	break;
	284	case OWER: /* XXX: Reset on OSMR3 match? */
	285	s->reset3 = value;
	286	break;
	287	case OMCR7: tm ++;
	288	case OMCR6: tm ++;
	289	case OMCR5: tm ++;
	290	case OMCR4:
	291	if (!s->tm4)
	292	goto badreg;
	293	s->tm4[tm].control = value & 0x0ff;
	294	/* XXX Stop if running (shouldn't happen) */
	295	if ((value & (1 << 7)) \|\| tm == 0)
	296	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	297	else {
	298	s->tm4[tm].freq = 0;
	299	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	300	}
	301	break;
	302	case OMCR11: tm ++;
	303	case OMCR10: tm ++;
	304	case OMCR9: tm ++;
	305	case OMCR8: tm += 4;
	306	if (!s->tm4)
	307	goto badreg;
	308	s->tm4[tm].control = value & 0x3ff;
	309	/* XXX Stop if running (shouldn't happen) */
	310	if ((value & (1 << 7)) \|\| !(tm & 1))
	311	s->tm4[tm].freq =
	312	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	313	else {
	314	s->tm4[tm].freq = 0;
	315	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	316	}
	317	break;
	318	default:
	319	badreg:
	320	cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
	321	REG_FMT "\n", offset);
	322	}
	323	}
	324
	325	static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
	326	pxa2xx_timer_read,
	327	pxa2xx_timer_read,
	328	pxa2xx_timer_read,
	329	};
	330
	331	static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
	332	pxa2xx_timer_write,
	333	pxa2xx_timer_write,
	334	pxa2xx_timer_write,
	335	};
	336
	337	static void pxa2xx_timer_tick(void *opaque)
	338	{
	339	struct pxa2xx_timer0_s t = (struct pxa2xx_timer0_s ) opaque;
	340	pxa2xx_timer_info i = (pxa2xx_timer_info ) t->info;
	341
	342	if (i->irq_enabled & (1 << t->num)) {
	343	t->level = 1;
	344	i->events \|= 1 << t->num;
	345	qemu_irq_raise(t->irq);
346	}
347
348	if (t->num == 3)
349	if (i->reset3 & 1) {
350	i->reset3 = 0;
3f582262	351	qemu_system_reset_request();
a171fe39 AZ	352	}
	353	}
	354
	355	static void pxa2xx_timer_tick4(void *opaque)
	356	{
	357	struct pxa2xx_timer4_s t = (struct pxa2xx_timer4_s ) opaque;
3bdd58a4	358	pxa2xx_timer_info i = (pxa2xx_timer_info ) t->tm.info;
a171fe39	359
3bdd58a4	360	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	361	if (t->control & (1 << 3))
	362	t->clock = 0;
	363	if (t->control & (1 << 6))
3bdd58a4	364	pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
a171fe39 AZ	365	}
a171fe39 AZ	366
aa941b94 AZ	367	static void pxa2xx_timer_save(QEMUFile f, void opaque)
	368	{
	369	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	370	int i;
	371
	372	qemu_put_be32s(f, &s->clock);
	373	qemu_put_be32s(f, &s->oldclock);
	374	qemu_put_be64s(f, &s->lastload);
	375
	376	for (i = 0; i < 4; i ++) {
	377	qemu_put_be32s(f, &s->timer[i].value);
	378	qemu_put_be32(f, s->timer[i].level);
	379	}
	380	if (s->tm4)
	381	for (i = 0; i < 8; i ++) {
	382	qemu_put_be32s(f, &s->tm4[i].tm.value);
	383	qemu_put_be32(f, s->tm4[i].tm.level);
	384	qemu_put_be32s(f, &s->tm4[i].oldclock);
	385	qemu_put_be32s(f, &s->tm4[i].clock);
	386	qemu_put_be64s(f, &s->tm4[i].lastload);
	387	qemu_put_be32s(f, &s->tm4[i].freq);
	388	qemu_put_be32s(f, &s->tm4[i].control);
	389	}
	390
	391	qemu_put_be32s(f, &s->events);
	392	qemu_put_be32s(f, &s->irq_enabled);
	393	qemu_put_be32s(f, &s->reset3);
	394	qemu_put_be32s(f, &s->snapshot);
	395	}
	396
	397	static int pxa2xx_timer_load(QEMUFile f, void opaque, int version_id)
	398	{
	399	pxa2xx_timer_info s = (pxa2xx_timer_info ) opaque;
	400	int64_t now;
	401	int i;
	402
	403	qemu_get_be32s(f, &s->clock);
	404	qemu_get_be32s(f, &s->oldclock);
	405	qemu_get_be64s(f, &s->lastload);
	406
	407	now = qemu_get_clock(vm_clock);
	408	for (i = 0; i < 4; i ++) {
	409	qemu_get_be32s(f, &s->timer[i].value);
	410	s->timer[i].level = qemu_get_be32(f);
	411	}
	412	pxa2xx_timer_update(s, now);
	413
	414	if (s->tm4)
	415	for (i = 0; i < 8; i ++) {
	416	qemu_get_be32s(f, &s->tm4[i].tm.value);
	417	s->tm4[i].tm.level = qemu_get_be32(f);
	418	qemu_get_be32s(f, &s->tm4[i].oldclock);
	419	qemu_get_be32s(f, &s->tm4[i].clock);
	420	qemu_get_be64s(f, &s->tm4[i].lastload);
	421	qemu_get_be32s(f, &s->tm4[i].freq);
	422	qemu_get_be32s(f, &s->tm4[i].control);
	423	pxa2xx_timer_update4(s, now, i);
	424	}
	425
	426	qemu_get_be32s(f, &s->events);
	427	qemu_get_be32s(f, &s->irq_enabled);
	428	qemu_get_be32s(f, &s->reset3);
	429	qemu_get_be32s(f, &s->snapshot);
	430
431	return 0;
432	}
433
a171fe39	434	static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
3f582262	435	qemu_irq *irqs)
a171fe39 AZ	436	{
	437	int i;
	438	int iomemtype;
	439	pxa2xx_timer_info *s;
	440
	441	s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
	442	s->base = base;
	443	s->irq_enabled = 0;
	444	s->oldclock = 0;
	445	s->clock = 0;
	446	s->lastload = qemu_get_clock(vm_clock);
	447	s->reset3 = 0;
a171fe39 AZ	448
	449	for (i = 0; i < 4; i ++) {
	450	s->timer[i].value = 0;
	451	s->timer[i].irq = irqs[i];
	452	s->timer[i].info = s;
	453	s->timer[i].num = i;
	454	s->timer[i].level = 0;
	455	s->timer[i].qtimer = qemu_new_timer(vm_clock,
	456	pxa2xx_timer_tick, &s->timer[i]);
	457	}
	458
	459	iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
	460	pxa2xx_timer_writefn, s);
187337f8	461	cpu_register_physical_memory(base, 0x00001000, iomemtype);
aa941b94 AZ	462
	463	register_savevm("pxa2xx_timer", 0, 0,
	464	pxa2xx_timer_save, pxa2xx_timer_load, s);
	465
a171fe39 AZ	466	return s;
	467	}
	468
3f582262	469	void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
a171fe39	470	{
3f582262	471	pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
a171fe39 AZ	472	s->freq = PXA25X_FREQ;
	473	s->tm4 = 0;
	474	}
	475
	476	void pxa27x_timer_init(target_phys_addr_t base,
3f582262	477	qemu_irq *irqs, qemu_irq irq4)
a171fe39	478	{
3f582262	479	pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
a171fe39 AZ	480	int i;
	481	s->freq = PXA27X_FREQ;
	482	s->tm4 = (struct pxa2xx_timer4_s ) qemu_mallocz(8
	483	sizeof(struct pxa2xx_timer4_s));
	484	for (i = 0; i < 8; i ++) {
3bdd58a4 AZ	485	s->tm4[i].tm.value = 0;
	486	s->tm4[i].tm.irq = irq4;
	487	s->tm4[i].tm.info = s;
	488	s->tm4[i].tm.num = i + 4;
	489	s->tm4[i].tm.level = 0;
a171fe39 AZ	490	s->tm4[i].freq = 0;
a171fe39 AZ	491	s->tm4[i].control = 0x0;
3bdd58a4	492	s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
a171fe39 AZ	493	pxa2xx_timer_tick4, &s->tm4[i]);
	494	}
	495	}