[qemu.git] / hw / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licenced under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "qdev.h"
#include "pxa.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

typedef struct {
    uint32_t value;
    int level;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    void *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

typedef struct {
    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    PXA2xxTimer4 *tm4;
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;
} PXA2xxTimerInfo;

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        get_ticks_per_sec(), s->freq);
        qemu_mod_timer(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        qemu_del_timer(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, get_ticks_per_sec());

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    get_ticks_per_sec(), s->tm4[counter].freq);
    qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}

static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!s->tm4)
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_get_clock(vm_clock) -
                        s->lastload, s->freq, get_ticks_per_sec());
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!s->tm4)
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_get_clock(vm_clock) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, get_ticks_per_sec());
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
                        s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm ++;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!s->tm4)
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
                uint32_t value)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
        break;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_get_clock(vm_clock);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_get_clock(vm_clock);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1) {
            if (s->timer[i].level && (value & 1)) {
                s->timer[i].level = 0;
                qemu_irq_lower(s->timer[i].irq);
            }
        }
        if (s->tm4) {
            for (i = 0; i < 8; i ++, value >>= 1)
                if (s->tm4[i].tm.level && (value & 1))
                    s->tm4[i].tm.level = 0;
            if (!(s->events & 0xff0))
                qemu_irq_lower(s->tm4->tm.irq);
        }
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        }
        break;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm += 4;
        if (!s->tm4)
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
        }
        break;
    default:
    badreg:
        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
    }
}

static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
    pxa2xx_timer_read,
    pxa2xx_timer_read,
    pxa2xx_timer_read,
};

static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
    pxa2xx_timer_write,
    pxa2xx_timer_write,
    pxa2xx_timer_write,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->info;

    if (i->irq_enabled & (1 << t->num)) {
        t->level = 1;
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
}

static void pxa2xx_timer_save(QEMUFile *f, void *opaque)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;

    qemu_put_be32s(f, (uint32_t *) &s->clock);
    qemu_put_be32s(f, (uint32_t *) &s->oldclock);
    qemu_put_be64s(f, &s->lastload);

    for (i = 0; i < 4; i ++) {
        qemu_put_be32s(f, &s->timer[i].value);
        qemu_put_be32(f, s->timer[i].level);
    }
    if (s->tm4)
        for (i = 0; i < 8; i ++) {
            qemu_put_be32s(f, &s->tm4[i].tm.value);
            qemu_put_be32(f, s->tm4[i].tm.level);
            qemu_put_sbe32s(f, &s->tm4[i].oldclock);
            qemu_put_sbe32s(f, &s->tm4[i].clock);
            qemu_put_be64s(f, &s->tm4[i].lastload);
            qemu_put_be32s(f, &s->tm4[i].freq);
            qemu_put_be32s(f, &s->tm4[i].control);
        }

    qemu_put_be32s(f, &s->events);
    qemu_put_be32s(f, &s->irq_enabled);
    qemu_put_be32s(f, &s->reset3);
    qemu_put_be32s(f, &s->snapshot);
}

static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    qemu_get_be32s(f, (uint32_t *) &s->clock);
    qemu_get_be32s(f, (uint32_t *) &s->oldclock);
    qemu_get_be64s(f, &s->lastload);

    now = qemu_get_clock(vm_clock);
    for (i = 0; i < 4; i ++) {
        qemu_get_be32s(f, &s->timer[i].value);
        s->timer[i].level = qemu_get_be32(f);
    }
    pxa2xx_timer_update(s, now);

    if (s->tm4)
        for (i = 0; i < 8; i ++) {
            qemu_get_be32s(f, &s->tm4[i].tm.value);
            s->tm4[i].tm.level = qemu_get_be32(f);
            qemu_get_sbe32s(f, &s->tm4[i].oldclock);
            qemu_get_sbe32s(f, &s->tm4[i].clock);
            qemu_get_be64s(f, &s->tm4[i].lastload);
            qemu_get_be32s(f, &s->tm4[i].freq);
            qemu_get_be32s(f, &s->tm4[i].control);
            pxa2xx_timer_update4(s, now, i);
        }

    qemu_get_be32s(f, &s->events);
    qemu_get_be32s(f, &s->irq_enabled);
    qemu_get_be32s(f, &s->reset3);
    qemu_get_be32s(f, &s->snapshot);

    return 0;
}

static PXA2xxTimerInfo *pxa2xx_timer_init(target_phys_addr_t base,
                DeviceState *pic)
{
    int i;
    int iomemtype;
    PXA2xxTimerInfo *s;

    s = (PXA2xxTimerInfo *) qemu_mallocz(sizeof(PXA2xxTimerInfo));
    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_get_clock(vm_clock);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        s->timer[i].irq = qdev_get_gpio_in(pic, PXA2XX_PIC_OST_0 + i);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].level = 0;
        s->timer[i].qtimer = qemu_new_timer(vm_clock,
                        pxa2xx_timer_tick, &s->timer[i]);
    }

    iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
                    pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);

    register_savevm(NULL, "pxa2xx_timer", 0, 0,
                    pxa2xx_timer_save, pxa2xx_timer_load, s);

    return s;
}

void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
{
    PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
    s->freq = PXA25X_FREQ;
    s->tm4 = NULL;
}

void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic)
{
    PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
    int i;
    s->freq = PXA27X_FREQ;
    s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
                    sizeof(PXA2xxTimer4));
    for (i = 0; i < 8; i ++) {
        s->tm4[i].tm.value = 0;
        s->tm4[i].tm.irq = qdev_get_gpio_in(pic, PXA27X_PIC_OST_4_11);
        s->tm4[i].tm.info = s;
        s->tm4[i].tm.num = i + 4;
        s->tm4[i].tm.level = 0;
        s->tm4[i].freq = 0;
        s->tm4[i].control = 0x0;
        s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
                        pxa2xx_timer_tick4, &s->tm4[i]);
    }
}
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
87ecb68b PB	10	#include "hw.h"
	11	#include "qemu-timer.h"
	12	#include "sysemu.h"
e1f8c729	13	#include "qdev.h"
87ecb68b	14	#include "pxa.h"
a171fe39 AZ	15
	16	#define OSMR0 0x00
	17	#define OSMR1 0x04
	18	#define OSMR2 0x08
	19	#define OSMR3 0x0c
	20	#define OSMR4 0x80
	21	#define OSMR5 0x84
	22	#define OSMR6 0x88
	23	#define OSMR7 0x8c
	24	#define OSMR8 0x90
	25	#define OSMR9 0x94
	26	#define OSMR10 0x98
	27	#define OSMR11 0x9c
	28	#define OSCR 0x10 /* OS Timer Count */
	29	#define OSCR4 0x40
	30	#define OSCR5 0x44
	31	#define OSCR6 0x48
	32	#define OSCR7 0x4c
	33	#define OSCR8 0x50
	34	#define OSCR9 0x54
	35	#define OSCR10 0x58
	36	#define OSCR11 0x5c
	37	#define OSSR 0x14 /* Timer status register */
	38	#define OWER 0x18
	39	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	40	#define OMCR4 0xc0 /* OS Match Control registers */
	41	#define OMCR5 0xc4
	42	#define OMCR6 0xc8
	43	#define OMCR7 0xcc
	44	#define OMCR8 0xd0
	45	#define OMCR9 0xd4
	46	#define OMCR10 0xd8
	47	#define OMCR11 0xdc
	48	#define OSNR 0x20
	49
	50	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	51	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	52
	53	static int pxa2xx_timer4_freq[8] = {
	54	[0] = 0,
	55	[1] = 32768,
	56	[2] = 1000,
	57	[3] = 1,
	58	[4] = 1000000,
	59	/* [5] is the "Externally supplied clock". Assign if necessary. */
	60	[5 ... 7] = 0,
	61	};
	62
bc24a225	63	typedef struct {
a171fe39 AZ	64	uint32_t value;
	65	int level;
	66	qemu_irq irq;
	67	QEMUTimer *qtimer;
	68	int num;
	69	void *info;
bc24a225	70	} PXA2xxTimer0;
a171fe39	71
bc24a225 PB	72	typedef struct {
bc24a225 PB	73	PXA2xxTimer0 tm;
a171fe39 AZ	74	int32_t oldclock;
	75	int32_t clock;
	76	uint64_t lastload;
	77	uint32_t freq;
	78	uint32_t control;
bc24a225	79	} PXA2xxTimer4;
a171fe39 AZ	80
a171fe39 AZ	81	typedef struct {
a171fe39 AZ	82	int32_t clock;
	83	int32_t oldclock;
	84	uint64_t lastload;
	85	uint32_t freq;
bc24a225 PB	86	PXA2xxTimer0 timer[4];
bc24a225 PB	87	PXA2xxTimer4 *tm4;
a171fe39 AZ	88	uint32_t events;
	89	uint32_t irq_enabled;
	90	uint32_t reset3;
a171fe39	91	uint32_t snapshot;
d353eb43	92	} PXA2xxTimerInfo;
a171fe39 AZ	93
	94	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	95	{
d353eb43	96	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	97	int i;
	98	uint32_t now_vm;
	99	uint64_t new_qemu;
	100
	101	now_vm = s->clock +
6ee093c9	102	muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	103
	104	for (i = 0; i < 4; i ++) {
	105	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
6ee093c9	106	get_ticks_per_sec(), s->freq);
a171fe39 AZ	107	qemu_mod_timer(s->timer[i].qtimer, new_qemu);
	108	}
	109	}
	110
	111	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	112	{
d353eb43	113	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	114	uint32_t now_vm;
	115	uint64_t new_qemu;
	116	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	117	int counter;
	118
	119	if (s->tm4[n].control & (1 << 7))
	120	counter = n;
	121	else
	122	counter = counters[n];
	123
	124	if (!s->tm4[counter].freq) {
3f582262	125	qemu_del_timer(s->tm4[n].tm.qtimer);
a171fe39 AZ	126	return;
	127	}
	128
	129	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	130	s->tm4[counter].lastload,
6ee093c9	131	s->tm4[counter].freq, get_ticks_per_sec());
a171fe39	132
3bdd58a4	133	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
6ee093c9	134	get_ticks_per_sec(), s->tm4[counter].freq);
3f582262	135	qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	136	}
a171fe39 AZ	137
c227f099	138	static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
a171fe39	139	{
d353eb43	140	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	141	int tm = 0;
a171fe39 AZ	142
a171fe39 AZ	143	switch (offset) {
	144	case OSMR3: tm ++;
	145	case OSMR2: tm ++;
	146	case OSMR1: tm ++;
	147	case OSMR0:
	148	return s->timer[tm].value;
	149	case OSMR11: tm ++;
	150	case OSMR10: tm ++;
	151	case OSMR9: tm ++;
	152	case OSMR8: tm ++;
	153	case OSMR7: tm ++;
	154	case OSMR6: tm ++;
	155	case OSMR5: tm ++;
	156	case OSMR4:
	157	if (!s->tm4)
	158	goto badreg;
3bdd58a4	159	return s->tm4[tm].tm.value;
a171fe39 AZ	160	case OSCR:
a171fe39 AZ	161	return s->clock + muldiv64(qemu_get_clock(vm_clock) -
6ee093c9	162	s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	163	case OSCR11: tm ++;
	164	case OSCR10: tm ++;
	165	case OSCR9: tm ++;
	166	case OSCR8: tm ++;
	167	case OSCR7: tm ++;
	168	case OSCR6: tm ++;
	169	case OSCR5: tm ++;
	170	case OSCR4:
	171	if (!s->tm4)
	172	goto badreg;
	173
	174	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	175	if (s->tm4[tm - 1].freq)
	176	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
	177	qemu_get_clock(vm_clock) -
	178	s->tm4[tm - 1].lastload,
6ee093c9	179	s->tm4[tm - 1].freq, get_ticks_per_sec());
a171fe39 AZ	180	else
	181	s->snapshot = s->tm4[tm - 1].clock;
	182	}
	183
	184	if (!s->tm4[tm].freq)
	185	return s->tm4[tm].clock;
	186	return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
6ee093c9	187	s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
a171fe39 AZ	188	case OIER:
	189	return s->irq_enabled;
	190	case OSSR: /* Status register */
	191	return s->events;
	192	case OWER:
	193	return s->reset3;
	194	case OMCR11: tm ++;
	195	case OMCR10: tm ++;
	196	case OMCR9: tm ++;
	197	case OMCR8: tm ++;
	198	case OMCR7: tm ++;
	199	case OMCR6: tm ++;
	200	case OMCR5: tm ++;
	201	case OMCR4:
	202	if (!s->tm4)
	203	goto badreg;
	204	return s->tm4[tm].control;
	205	case OSNR:
	206	return s->snapshot;
	207	default:
	208	badreg:
2ac71179	209	hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	210	}
	211
	212	return 0;
	213	}
	214
c227f099	215	static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
a171fe39 AZ	216	uint32_t value)
	217	{
	218	int i, tm = 0;
d353eb43	219	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	220
a171fe39 AZ	221	switch (offset) {
	222	case OSMR3: tm ++;
	223	case OSMR2: tm ++;
	224	case OSMR1: tm ++;
	225	case OSMR0:
	226	s->timer[tm].value = value;
	227	pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
	228	break;
	229	case OSMR11: tm ++;
	230	case OSMR10: tm ++;
	231	case OSMR9: tm ++;
	232	case OSMR8: tm ++;
	233	case OSMR7: tm ++;
	234	case OSMR6: tm ++;
	235	case OSMR5: tm ++;
	236	case OSMR4:
	237	if (!s->tm4)
	238	goto badreg;
3bdd58a4	239	s->tm4[tm].tm.value = value;
a171fe39 AZ	240	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	241	break;
	242	case OSCR:
	243	s->oldclock = s->clock;
	244	s->lastload = qemu_get_clock(vm_clock);
	245	s->clock = value;
	246	pxa2xx_timer_update(s, s->lastload);
	247	break;
	248	case OSCR11: tm ++;
	249	case OSCR10: tm ++;
	250	case OSCR9: tm ++;
	251	case OSCR8: tm ++;
	252	case OSCR7: tm ++;
	253	case OSCR6: tm ++;
	254	case OSCR5: tm ++;
	255	case OSCR4:
	256	if (!s->tm4)
	257	goto badreg;
	258	s->tm4[tm].oldclock = s->tm4[tm].clock;
	259	s->tm4[tm].lastload = qemu_get_clock(vm_clock);
	260	s->tm4[tm].clock = value;
	261	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	262	break;
	263	case OIER:
	264	s->irq_enabled = value & 0xfff;
	265	break;
	266	case OSSR: /* Status register */
	267	s->events &= ~value;
	268	for (i = 0; i < 4; i ++, value >>= 1) {
	269	if (s->timer[i].level && (value & 1)) {
	270	s->timer[i].level = 0;
	271	qemu_irq_lower(s->timer[i].irq);
	272	}
	273	}
	274	if (s->tm4) {
	275	for (i = 0; i < 8; i ++, value >>= 1)
3bdd58a4 AZ	276	if (s->tm4[i].tm.level && (value & 1))
3bdd58a4 AZ	277	s->tm4[i].tm.level = 0;
a171fe39	278	if (!(s->events & 0xff0))
3bdd58a4	279	qemu_irq_lower(s->tm4->tm.irq);
a171fe39 AZ	280	}
	281	break;
	282	case OWER: /* XXX: Reset on OSMR3 match? */
	283	s->reset3 = value;
	284	break;
	285	case OMCR7: tm ++;
	286	case OMCR6: tm ++;
	287	case OMCR5: tm ++;
	288	case OMCR4:
	289	if (!s->tm4)
	290	goto badreg;
	291	s->tm4[tm].control = value & 0x0ff;
	292	/* XXX Stop if running (shouldn't happen) */
	293	if ((value & (1 << 7)) \|\| tm == 0)
	294	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	295	else {
	296	s->tm4[tm].freq = 0;
	297	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	298	}
	299	break;
	300	case OMCR11: tm ++;
	301	case OMCR10: tm ++;
	302	case OMCR9: tm ++;
	303	case OMCR8: tm += 4;
	304	if (!s->tm4)
	305	goto badreg;
	306	s->tm4[tm].control = value & 0x3ff;
	307	/* XXX Stop if running (shouldn't happen) */
	308	if ((value & (1 << 7)) \|\| !(tm & 1))
	309	s->tm4[tm].freq =
	310	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	311	else {
	312	s->tm4[tm].freq = 0;
	313	pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
	314	}
	315	break;
	316	default:
	317	badreg:
2ac71179	318	hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	319	}
	320	}
	321
d60efc6b	322	static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
a171fe39 AZ	323	pxa2xx_timer_read,
	324	pxa2xx_timer_read,
	325	pxa2xx_timer_read,
	326	};
	327
d60efc6b	328	static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
a171fe39 AZ	329	pxa2xx_timer_write,
	330	pxa2xx_timer_write,
	331	pxa2xx_timer_write,
	332	};
	333
	334	static void pxa2xx_timer_tick(void *opaque)
	335	{
bc24a225	336	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
d353eb43	337	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->info;
a171fe39 AZ	338
	339	if (i->irq_enabled & (1 << t->num)) {
	340	t->level = 1;
	341	i->events \|= 1 << t->num;
	342	qemu_irq_raise(t->irq);
	343	}
	344
	345	if (t->num == 3)
	346	if (i->reset3 & 1) {
	347	i->reset3 = 0;
3f582262	348	qemu_system_reset_request();
a171fe39 AZ	349	}
	350	}
	351
	352	static void pxa2xx_timer_tick4(void *opaque)
	353	{
bc24a225	354	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	355	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	356
3bdd58a4	357	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	358	if (t->control & (1 << 3))
	359	t->clock = 0;
	360	if (t->control & (1 << 6))
3bdd58a4	361	pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
a171fe39 AZ	362	}
a171fe39 AZ	363
aa941b94 AZ	364	static void pxa2xx_timer_save(QEMUFile f, void opaque)
aa941b94 AZ	365	{
d353eb43	366	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	367	int i;
aa941b94 AZ	368
a050e24d AZ	369	qemu_put_be32s(f, (uint32_t *) &s->clock);
a050e24d AZ	370	qemu_put_be32s(f, (uint32_t *) &s->oldclock);
aa941b94 AZ	371	qemu_put_be64s(f, &s->lastload);
	372
	373	for (i = 0; i < 4; i ++) {
	374	qemu_put_be32s(f, &s->timer[i].value);
	375	qemu_put_be32(f, s->timer[i].level);
	376	}
	377	if (s->tm4)
	378	for (i = 0; i < 8; i ++) {
	379	qemu_put_be32s(f, &s->tm4[i].tm.value);
	380	qemu_put_be32(f, s->tm4[i].tm.level);
b6c4f71f BS	381	qemu_put_sbe32s(f, &s->tm4[i].oldclock);
b6c4f71f BS	382	qemu_put_sbe32s(f, &s->tm4[i].clock);
aa941b94 AZ	383	qemu_put_be64s(f, &s->tm4[i].lastload);
	384	qemu_put_be32s(f, &s->tm4[i].freq);
	385	qemu_put_be32s(f, &s->tm4[i].control);
	386	}
	387
	388	qemu_put_be32s(f, &s->events);
	389	qemu_put_be32s(f, &s->irq_enabled);
	390	qemu_put_be32s(f, &s->reset3);
	391	qemu_put_be32s(f, &s->snapshot);
	392	}
	393
	394	static int pxa2xx_timer_load(QEMUFile f, void opaque, int version_id)
	395	{
d353eb43	396	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	397	int64_t now;
	398	int i;
	399
a050e24d AZ	400	qemu_get_be32s(f, (uint32_t *) &s->clock);
a050e24d AZ	401	qemu_get_be32s(f, (uint32_t *) &s->oldclock);
aa941b94 AZ	402	qemu_get_be64s(f, &s->lastload);
	403
	404	now = qemu_get_clock(vm_clock);
	405	for (i = 0; i < 4; i ++) {
	406	qemu_get_be32s(f, &s->timer[i].value);
	407	s->timer[i].level = qemu_get_be32(f);
	408	}
	409	pxa2xx_timer_update(s, now);
	410
	411	if (s->tm4)
	412	for (i = 0; i < 8; i ++) {
	413	qemu_get_be32s(f, &s->tm4[i].tm.value);
	414	s->tm4[i].tm.level = qemu_get_be32(f);
b6c4f71f BS	415	qemu_get_sbe32s(f, &s->tm4[i].oldclock);
b6c4f71f BS	416	qemu_get_sbe32s(f, &s->tm4[i].clock);
aa941b94 AZ	417	qemu_get_be64s(f, &s->tm4[i].lastload);
	418	qemu_get_be32s(f, &s->tm4[i].freq);
	419	qemu_get_be32s(f, &s->tm4[i].control);
	420	pxa2xx_timer_update4(s, now, i);
	421	}
	422
	423	qemu_get_be32s(f, &s->events);
	424	qemu_get_be32s(f, &s->irq_enabled);
	425	qemu_get_be32s(f, &s->reset3);
	426	qemu_get_be32s(f, &s->snapshot);
	427
	428	return 0;
	429	}
	430
d353eb43	431	static PXA2xxTimerInfo *pxa2xx_timer_init(target_phys_addr_t base,
e1f8c729	432	DeviceState *pic)
a171fe39 AZ	433	{
	434	int i;
	435	int iomemtype;
d353eb43	436	PXA2xxTimerInfo *s;
a171fe39	437
d353eb43	438	s = (PXA2xxTimerInfo *) qemu_mallocz(sizeof(PXA2xxTimerInfo));
a171fe39 AZ	439	s->irq_enabled = 0;
	440	s->oldclock = 0;
	441	s->clock = 0;
	442	s->lastload = qemu_get_clock(vm_clock);
	443	s->reset3 = 0;
a171fe39 AZ	444
	445	for (i = 0; i < 4; i ++) {
	446	s->timer[i].value = 0;
e1f8c729	447	s->timer[i].irq = qdev_get_gpio_in(pic, PXA2XX_PIC_OST_0 + i);
a171fe39 AZ	448	s->timer[i].info = s;
	449	s->timer[i].num = i;
	450	s->timer[i].level = 0;
	451	s->timer[i].qtimer = qemu_new_timer(vm_clock,
	452	pxa2xx_timer_tick, &s->timer[i]);
	453	}
	454
1eed09cb	455	iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
2507c12a	456	pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
187337f8	457	cpu_register_physical_memory(base, 0x00001000, iomemtype);
aa941b94	458
0be71e32	459	register_savevm(NULL, "pxa2xx_timer", 0, 0,
aa941b94 AZ	460	pxa2xx_timer_save, pxa2xx_timer_load, s);
aa941b94 AZ	461
a171fe39 AZ	462	return s;
	463	}
	464
e1f8c729	465	void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
a171fe39	466	{
d353eb43	467	PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
a171fe39	468	s->freq = PXA25X_FREQ;
b9d38e95	469	s->tm4 = NULL;
a171fe39 AZ	470	}
a171fe39 AZ	471
e1f8c729	472	void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic)
a171fe39	473	{
d353eb43	474	PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
a171fe39 AZ	475	int i;
a171fe39 AZ	476	s->freq = PXA27X_FREQ;
bc24a225 PB	477	s->tm4 = (PXA2xxTimer4 ) qemu_mallocz(8
bc24a225 PB	478	sizeof(PXA2xxTimer4));
a171fe39	479	for (i = 0; i < 8; i ++) {
3bdd58a4	480	s->tm4[i].tm.value = 0;
e1f8c729	481	s->tm4[i].tm.irq = qdev_get_gpio_in(pic, PXA27X_PIC_OST_4_11);
3bdd58a4 AZ	482	s->tm4[i].tm.info = s;
	483	s->tm4[i].tm.num = i + 4;
	484	s->tm4[i].tm.level = 0;
a171fe39 AZ	485	s->tm4[i].freq = 0;
a171fe39 AZ	486	s->tm4[i].control = 0x0;
3bdd58a4	487	s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
a171fe39 AZ	488	pxa2xx_timer_tick4, &s->tm4[i]);
	489	}
	490	}