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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <kraxel@redhat.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
a19cbfb3 GH |
21 | #include "qemu-common.h" |
22 | #include "qemu-timer.h" | |
23 | #include "qemu-queue.h" | |
24 | #include "monitor.h" | |
25 | #include "sysemu.h" | |
c480bb7d | 26 | #include "trace.h" |
a19cbfb3 GH |
27 | |
28 | #include "qxl.h" | |
29 | ||
0b81c478 AL |
30 | /* |
31 | * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as | |
32 | * such can be changed by the guest, so to avoid a guest trigerrable | |
0a530548 | 33 | * abort we just qxl_set_guest_bug and set the return to NULL. Still |
0b81c478 AL |
34 | * it may happen as a result of emulator bug as well. |
35 | */ | |
a19cbfb3 | 36 | #undef SPICE_RING_PROD_ITEM |
0b81c478 | 37 | #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \ |
a19cbfb3 GH |
38 | typeof(r) start = r; \ |
39 | typeof(r) end = r + 1; \ | |
40 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ | |
41 | typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ | |
42 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
0a530548 | 43 | qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \ |
0b81c478 AL |
44 | "! %p <= %p < %p", (uint8_t *)start, \ |
45 | (uint8_t *)m_item, (uint8_t *)end); \ | |
46 | ret = NULL; \ | |
47 | } else { \ | |
48 | ret = &m_item->el; \ | |
a19cbfb3 | 49 | } \ |
a19cbfb3 GH |
50 | } |
51 | ||
52 | #undef SPICE_RING_CONS_ITEM | |
0b81c478 | 53 | #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \ |
a19cbfb3 GH |
54 | typeof(r) start = r; \ |
55 | typeof(r) end = r + 1; \ | |
56 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ | |
57 | typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ | |
58 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
0a530548 | 59 | qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \ |
0b81c478 AL |
60 | "! %p <= %p < %p", (uint8_t *)start, \ |
61 | (uint8_t *)m_item, (uint8_t *)end); \ | |
62 | ret = NULL; \ | |
63 | } else { \ | |
64 | ret = &m_item->el; \ | |
a19cbfb3 | 65 | } \ |
a19cbfb3 GH |
66 | } |
67 | ||
68 | #undef ALIGN | |
69 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
70 | ||
71 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
72 | ||
73 | #define QXL_MODE(_x, _y, _b, _o) \ | |
74 | { .x_res = _x, \ | |
75 | .y_res = _y, \ | |
76 | .bits = _b, \ | |
77 | .stride = (_x) * (_b) / 8, \ | |
78 | .x_mili = PIXEL_SIZE * (_x), \ | |
79 | .y_mili = PIXEL_SIZE * (_y), \ | |
80 | .orientation = _o, \ | |
81 | } | |
82 | ||
83 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
84 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
85 | QXL_MODE(x_res, y_res, 32, orientation) | |
86 | ||
87 | #define QXL_MODE_EX(x_res, y_res) \ | |
88 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
89 | QXL_MODE_16_32(y_res, x_res, 1), \ | |
90 | QXL_MODE_16_32(x_res, y_res, 2), \ | |
91 | QXL_MODE_16_32(y_res, x_res, 3) | |
92 | ||
93 | static QXLMode qxl_modes[] = { | |
94 | QXL_MODE_EX(640, 480), | |
95 | QXL_MODE_EX(800, 480), | |
96 | QXL_MODE_EX(800, 600), | |
97 | QXL_MODE_EX(832, 624), | |
98 | QXL_MODE_EX(960, 640), | |
99 | QXL_MODE_EX(1024, 600), | |
100 | QXL_MODE_EX(1024, 768), | |
101 | QXL_MODE_EX(1152, 864), | |
102 | QXL_MODE_EX(1152, 870), | |
103 | QXL_MODE_EX(1280, 720), | |
104 | QXL_MODE_EX(1280, 760), | |
105 | QXL_MODE_EX(1280, 768), | |
106 | QXL_MODE_EX(1280, 800), | |
107 | QXL_MODE_EX(1280, 960), | |
108 | QXL_MODE_EX(1280, 1024), | |
109 | QXL_MODE_EX(1360, 768), | |
110 | QXL_MODE_EX(1366, 768), | |
111 | QXL_MODE_EX(1400, 1050), | |
112 | QXL_MODE_EX(1440, 900), | |
113 | QXL_MODE_EX(1600, 900), | |
114 | QXL_MODE_EX(1600, 1200), | |
115 | QXL_MODE_EX(1680, 1050), | |
116 | QXL_MODE_EX(1920, 1080), | |
117 | #if VGA_RAM_SIZE >= (16 * 1024 * 1024) | |
118 | /* these modes need more than 8 MB video memory */ | |
119 | QXL_MODE_EX(1920, 1200), | |
120 | QXL_MODE_EX(1920, 1440), | |
121 | QXL_MODE_EX(2048, 1536), | |
122 | QXL_MODE_EX(2560, 1440), | |
123 | QXL_MODE_EX(2560, 1600), | |
124 | #endif | |
125 | #if VGA_RAM_SIZE >= (32 * 1024 * 1024) | |
126 | /* these modes need more than 16 MB video memory */ | |
127 | QXL_MODE_EX(2560, 2048), | |
128 | QXL_MODE_EX(2800, 2100), | |
129 | QXL_MODE_EX(3200, 2400), | |
130 | #endif | |
131 | }; | |
132 | ||
133 | static PCIQXLDevice *qxl0; | |
134 | ||
135 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); | |
5ff4e36c | 136 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async); |
a19cbfb3 GH |
137 | static void qxl_reset_memslots(PCIQXLDevice *d); |
138 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
139 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
140 | ||
0a530548 | 141 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 | 142 | { |
2bce0400 | 143 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); |
2bce0400 | 144 | if (qxl->guestdebug) { |
7635392c AL |
145 | va_list ap; |
146 | va_start(ap, msg); | |
147 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
148 | vfprintf(stderr, msg, ap); | |
149 | fprintf(stderr, "\n"); | |
150 | va_end(ap); | |
2bce0400 GH |
151 | } |
152 | } | |
153 | ||
aee32bf3 GH |
154 | |
155 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
156 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
157 | uint32_t num_dirty_rects, | |
5ff4e36c | 158 | uint32_t clear_dirty_region, |
2e1a98c9 | 159 | qxl_async_io async, struct QXLCookie *cookie) |
aee32bf3 | 160 | { |
c480bb7d AL |
161 | trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, |
162 | area->top, area->bottom); | |
163 | trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, | |
164 | clear_dirty_region); | |
5ff4e36c AL |
165 | if (async == QXL_SYNC) { |
166 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, | |
167 | dirty_rects, num_dirty_rects, clear_dirty_region); | |
168 | } else { | |
2e1a98c9 | 169 | assert(cookie != NULL); |
5ff4e36c | 170 | spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, |
5dba0d45 | 171 | clear_dirty_region, (uintptr_t)cookie); |
5ff4e36c | 172 | } |
aee32bf3 GH |
173 | } |
174 | ||
5ff4e36c AL |
175 | static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl, |
176 | uint32_t id) | |
aee32bf3 | 177 | { |
c480bb7d | 178 | trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); |
14898cf6 | 179 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
180 | qxl->guest_surfaces.cmds[id] = 0; |
181 | qxl->guest_surfaces.count--; | |
182 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
183 | } |
184 | ||
5ff4e36c AL |
185 | static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id, |
186 | qxl_async_io async) | |
187 | { | |
2e1a98c9 AL |
188 | QXLCookie *cookie; |
189 | ||
c480bb7d | 190 | trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); |
5ff4e36c | 191 | if (async) { |
2e1a98c9 AL |
192 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
193 | QXL_IO_DESTROY_SURFACE_ASYNC); | |
194 | cookie->u.surface_id = id; | |
5dba0d45 | 195 | spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); |
5ff4e36c AL |
196 | } else { |
197 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); | |
5ff4e36c AL |
198 | } |
199 | } | |
200 | ||
3e16b9c5 AL |
201 | static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl) |
202 | { | |
c480bb7d AL |
203 | trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, |
204 | qxl->num_free_res); | |
2e1a98c9 | 205 | spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
206 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
207 | QXL_IO_FLUSH_SURFACES_ASYNC)); | |
3e16b9c5 | 208 | } |
3e16b9c5 | 209 | |
aee32bf3 GH |
210 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
211 | uint32_t count) | |
212 | { | |
c480bb7d | 213 | trace_qxl_spice_loadvm_commands(qxl->id, ext, count); |
aee32bf3 GH |
214 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); |
215 | } | |
216 | ||
217 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
218 | { | |
c480bb7d | 219 | trace_qxl_spice_oom(qxl->id); |
aee32bf3 GH |
220 | qxl->ssd.worker->oom(qxl->ssd.worker); |
221 | } | |
222 | ||
223 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
224 | { | |
c480bb7d | 225 | trace_qxl_spice_reset_memslots(qxl->id); |
aee32bf3 GH |
226 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); |
227 | } | |
228 | ||
5ff4e36c | 229 | static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl) |
aee32bf3 | 230 | { |
c480bb7d | 231 | trace_qxl_spice_destroy_surfaces_complete(qxl->id); |
14898cf6 | 232 | qemu_mutex_lock(&qxl->track_lock); |
14898cf6 GH |
233 | memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds)); |
234 | qxl->guest_surfaces.count = 0; | |
235 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
236 | } |
237 | ||
5ff4e36c AL |
238 | static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async) |
239 | { | |
c480bb7d | 240 | trace_qxl_spice_destroy_surfaces(qxl->id, async); |
5ff4e36c | 241 | if (async) { |
2e1a98c9 | 242 | spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, |
5dba0d45 PM |
243 | (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO, |
244 | QXL_IO_DESTROY_ALL_SURFACES_ASYNC)); | |
5ff4e36c AL |
245 | } else { |
246 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); | |
247 | qxl_spice_destroy_surfaces_complete(qxl); | |
248 | } | |
249 | } | |
250 | ||
aee32bf3 GH |
251 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) |
252 | { | |
c480bb7d | 253 | trace_qxl_spice_reset_image_cache(qxl->id); |
aee32bf3 GH |
254 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); |
255 | } | |
256 | ||
257 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
258 | { | |
c480bb7d | 259 | trace_qxl_spice_reset_cursor(qxl->id); |
aee32bf3 | 260 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); |
30f6da66 YH |
261 | qemu_mutex_lock(&qxl->track_lock); |
262 | qxl->guest_cursor = 0; | |
263 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
264 | } |
265 | ||
266 | ||
a19cbfb3 GH |
267 | static inline uint32_t msb_mask(uint32_t val) |
268 | { | |
269 | uint32_t mask; | |
270 | ||
271 | do { | |
272 | mask = ~(val - 1) & val; | |
273 | val &= ~mask; | |
274 | } while (mask < val); | |
275 | ||
276 | return mask; | |
277 | } | |
278 | ||
279 | static ram_addr_t qxl_rom_size(void) | |
280 | { | |
281 | uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); | |
282 | rom_size = MAX(rom_size, TARGET_PAGE_SIZE); | |
283 | rom_size = msb_mask(rom_size * 2 - 1); | |
284 | return rom_size; | |
285 | } | |
286 | ||
287 | static void init_qxl_rom(PCIQXLDevice *d) | |
288 | { | |
b1950430 | 289 | QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); |
a19cbfb3 GH |
290 | QXLModes *modes = (QXLModes *)(rom + 1); |
291 | uint32_t ram_header_size; | |
292 | uint32_t surface0_area_size; | |
293 | uint32_t num_pages; | |
294 | uint32_t fb, maxfb = 0; | |
295 | int i; | |
296 | ||
297 | memset(rom, 0, d->rom_size); | |
298 | ||
299 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
300 | rom->id = cpu_to_le32(d->id); | |
301 | rom->log_level = cpu_to_le32(d->guestdebug); | |
302 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
303 | ||
304 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
305 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
306 | rom->slots_start = 1; | |
307 | rom->slots_end = NUM_MEMSLOTS - 1; | |
308 | rom->n_surfaces = cpu_to_le32(NUM_SURFACES); | |
309 | ||
310 | modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); | |
311 | for (i = 0; i < modes->n_modes; i++) { | |
312 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; | |
313 | if (maxfb < fb) { | |
314 | maxfb = fb; | |
315 | } | |
316 | modes->modes[i].id = cpu_to_le32(i); | |
317 | modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
318 | modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
319 | modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); | |
320 | modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); | |
321 | modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
322 | modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
323 | modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
324 | } | |
325 | if (maxfb < VGA_RAM_SIZE && d->id == 0) | |
326 | maxfb = VGA_RAM_SIZE; | |
327 | ||
328 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
329 | surface0_area_size = ALIGN(maxfb, 4096); | |
330 | num_pages = d->vga.vram_size; | |
331 | num_pages -= ram_header_size; | |
332 | num_pages -= surface0_area_size; | |
333 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
334 | ||
335 | rom->draw_area_offset = cpu_to_le32(0); | |
336 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
337 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
338 | rom->num_pages = cpu_to_le32(num_pages); | |
339 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
340 | ||
341 | d->shadow_rom = *rom; | |
342 | d->rom = rom; | |
343 | d->modes = modes; | |
344 | } | |
345 | ||
346 | static void init_qxl_ram(PCIQXLDevice *d) | |
347 | { | |
348 | uint8_t *buf; | |
349 | uint64_t *item; | |
350 | ||
351 | buf = d->vga.vram_ptr; | |
352 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
353 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
354 | d->ram->int_pending = cpu_to_le32(0); | |
355 | d->ram->int_mask = cpu_to_le32(0); | |
9f0f352d | 356 | d->ram->update_surface = 0; |
a19cbfb3 GH |
357 | SPICE_RING_INIT(&d->ram->cmd_ring); |
358 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
359 | SPICE_RING_INIT(&d->ram->release_ring); | |
0b81c478 AL |
360 | SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item); |
361 | assert(item); | |
a19cbfb3 GH |
362 | *item = 0; |
363 | qxl_ring_set_dirty(d); | |
364 | } | |
365 | ||
366 | /* can be called from spice server thread context */ | |
b1950430 | 367 | static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end) |
a19cbfb3 | 368 | { |
fd4aa979 | 369 | memory_region_set_dirty(mr, addr, end - addr); |
a19cbfb3 GH |
370 | } |
371 | ||
372 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
373 | { | |
b1950430 | 374 | qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); |
a19cbfb3 GH |
375 | } |
376 | ||
377 | /* called from spice server thread context only */ | |
378 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
379 | { | |
a19cbfb3 GH |
380 | void *base = qxl->vga.vram_ptr; |
381 | intptr_t offset; | |
382 | ||
383 | offset = ptr - base; | |
384 | offset &= ~(TARGET_PAGE_SIZE-1); | |
385 | assert(offset < qxl->vga.vram_size); | |
b1950430 | 386 | qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE); |
a19cbfb3 GH |
387 | } |
388 | ||
389 | /* can be called from spice server thread context */ | |
390 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
391 | { | |
b1950430 AK |
392 | ram_addr_t addr = qxl->shadow_rom.ram_header_offset; |
393 | ram_addr_t end = qxl->vga.vram_size; | |
394 | qxl_set_dirty(&qxl->vga.vram, addr, end); | |
a19cbfb3 GH |
395 | } |
396 | ||
397 | /* | |
398 | * keep track of some command state, for savevm/loadvm. | |
399 | * called from spice server thread context only | |
400 | */ | |
fae2afb1 | 401 | static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) |
a19cbfb3 GH |
402 | { |
403 | switch (le32_to_cpu(ext->cmd.type)) { | |
404 | case QXL_CMD_SURFACE: | |
405 | { | |
406 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
407 | |
408 | if (!cmd) { | |
409 | return 1; | |
410 | } | |
a19cbfb3 | 411 | uint32_t id = le32_to_cpu(cmd->surface_id); |
47eddfbf AL |
412 | |
413 | if (id >= NUM_SURFACES) { | |
0a530548 AL |
414 | qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id, |
415 | NUM_SURFACES); | |
47eddfbf AL |
416 | return 1; |
417 | } | |
14898cf6 | 418 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
419 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
420 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
421 | qxl->guest_surfaces.count++; | |
422 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
423 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
424 | } | |
425 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
426 | qxl->guest_surfaces.cmds[id] = 0; | |
427 | qxl->guest_surfaces.count--; | |
428 | } | |
14898cf6 | 429 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
430 | break; |
431 | } | |
432 | case QXL_CMD_CURSOR: | |
433 | { | |
434 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
fae2afb1 AL |
435 | |
436 | if (!cmd) { | |
437 | return 1; | |
438 | } | |
a19cbfb3 | 439 | if (cmd->type == QXL_CURSOR_SET) { |
30f6da66 | 440 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 | 441 | qxl->guest_cursor = ext->cmd.data; |
30f6da66 | 442 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
443 | } |
444 | break; | |
445 | } | |
446 | } | |
fae2afb1 | 447 | return 0; |
a19cbfb3 GH |
448 | } |
449 | ||
450 | /* spice display interface callbacks */ | |
451 | ||
452 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
453 | { | |
454 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
455 | ||
c480bb7d | 456 | trace_qxl_interface_attach_worker(qxl->id); |
a19cbfb3 GH |
457 | qxl->ssd.worker = qxl_worker; |
458 | } | |
459 | ||
460 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
461 | { | |
462 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
463 | ||
c480bb7d | 464 | trace_qxl_interface_set_compression_level(qxl->id, level); |
a19cbfb3 GH |
465 | qxl->shadow_rom.compression_level = cpu_to_le32(level); |
466 | qxl->rom->compression_level = cpu_to_le32(level); | |
467 | qxl_rom_set_dirty(qxl); | |
468 | } | |
469 | ||
470 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
471 | { | |
472 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
473 | ||
c480bb7d | 474 | trace_qxl_interface_set_mm_time(qxl->id, mm_time); |
a19cbfb3 GH |
475 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); |
476 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
477 | qxl_rom_set_dirty(qxl); | |
478 | } | |
479 | ||
480 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
481 | { | |
482 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
483 | ||
c480bb7d | 484 | trace_qxl_interface_get_init_info(qxl->id); |
a19cbfb3 GH |
485 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; |
486 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
487 | info->num_memslots = NUM_MEMSLOTS; | |
488 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
489 | info->internal_groupslot_id = 0; | |
490 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
491 | info->n_surfaces = NUM_SURFACES; | |
492 | } | |
493 | ||
5b77870c AL |
494 | static const char *qxl_mode_to_string(int mode) |
495 | { | |
496 | switch (mode) { | |
497 | case QXL_MODE_COMPAT: | |
498 | return "compat"; | |
499 | case QXL_MODE_NATIVE: | |
500 | return "native"; | |
501 | case QXL_MODE_UNDEFINED: | |
502 | return "undefined"; | |
503 | case QXL_MODE_VGA: | |
504 | return "vga"; | |
505 | } | |
506 | return "INVALID"; | |
507 | } | |
508 | ||
8b92e298 AL |
509 | static const char *io_port_to_string(uint32_t io_port) |
510 | { | |
511 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
512 | return "out of range"; | |
513 | } | |
514 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
515 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
516 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
517 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
518 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
519 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
520 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
521 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
522 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
523 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
524 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
525 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
526 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
527 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
528 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
529 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
530 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
8b92e298 AL |
531 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", |
532 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
533 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
534 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
535 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
536 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
537 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
538 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
539 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
8b92e298 AL |
540 | }; |
541 | return io_port_to_string[io_port]; | |
542 | } | |
543 | ||
a19cbfb3 GH |
544 | /* called from spice server thread context only */ |
545 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
546 | { | |
547 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
548 | SimpleSpiceUpdate *update; | |
549 | QXLCommandRing *ring; | |
550 | QXLCommand *cmd; | |
e0c64d08 | 551 | int notify, ret; |
a19cbfb3 | 552 | |
c480bb7d AL |
553 | trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
554 | ||
a19cbfb3 GH |
555 | switch (qxl->mode) { |
556 | case QXL_MODE_VGA: | |
e0c64d08 GH |
557 | ret = false; |
558 | qemu_mutex_lock(&qxl->ssd.lock); | |
559 | if (qxl->ssd.update != NULL) { | |
560 | update = qxl->ssd.update; | |
561 | qxl->ssd.update = NULL; | |
562 | *ext = update->ext; | |
563 | ret = true; | |
a19cbfb3 | 564 | } |
e0c64d08 | 565 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 566 | if (ret) { |
c480bb7d | 567 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
568 | qxl_log_command(qxl, "vga", ext); |
569 | } | |
e0c64d08 | 570 | return ret; |
a19cbfb3 GH |
571 | case QXL_MODE_COMPAT: |
572 | case QXL_MODE_NATIVE: | |
573 | case QXL_MODE_UNDEFINED: | |
a19cbfb3 GH |
574 | ring = &qxl->ram->cmd_ring; |
575 | if (SPICE_RING_IS_EMPTY(ring)) { | |
576 | return false; | |
577 | } | |
0b81c478 AL |
578 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
579 | if (!cmd) { | |
580 | return false; | |
581 | } | |
a19cbfb3 GH |
582 | ext->cmd = *cmd; |
583 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
584 | ext->flags = qxl->cmdflags; | |
585 | SPICE_RING_POP(ring, notify); | |
586 | qxl_ring_set_dirty(qxl); | |
587 | if (notify) { | |
588 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
589 | } | |
590 | qxl->guest_primary.commands++; | |
591 | qxl_track_command(qxl, ext); | |
592 | qxl_log_command(qxl, "cmd", ext); | |
0b81c478 | 593 | trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
594 | return true; |
595 | default: | |
596 | return false; | |
597 | } | |
598 | } | |
599 | ||
600 | /* called from spice server thread context only */ | |
601 | static int interface_req_cmd_notification(QXLInstance *sin) | |
602 | { | |
603 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
604 | int wait = 1; | |
605 | ||
c480bb7d | 606 | trace_qxl_ring_command_req_notification(qxl->id); |
a19cbfb3 GH |
607 | switch (qxl->mode) { |
608 | case QXL_MODE_COMPAT: | |
609 | case QXL_MODE_NATIVE: | |
610 | case QXL_MODE_UNDEFINED: | |
611 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
612 | qxl_ring_set_dirty(qxl); | |
613 | break; | |
614 | default: | |
615 | /* nothing */ | |
616 | break; | |
617 | } | |
618 | return wait; | |
619 | } | |
620 | ||
621 | /* called from spice server thread context only */ | |
622 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
623 | { | |
624 | QXLReleaseRing *ring = &d->ram->release_ring; | |
625 | uint64_t *item; | |
626 | int notify; | |
627 | ||
628 | #define QXL_FREE_BUNCH_SIZE 32 | |
629 | ||
630 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
631 | /* ring full -- can't push */ | |
632 | return; | |
633 | } | |
634 | if (!flush && d->oom_running) { | |
635 | /* collect everything from oom handler before pushing */ | |
636 | return; | |
637 | } | |
638 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
639 | /* collect a bit more before pushing */ | |
640 | return; | |
641 | } | |
642 | ||
643 | SPICE_RING_PUSH(ring, notify); | |
c480bb7d AL |
644 | trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), |
645 | d->guest_surfaces.count, d->num_free_res, | |
646 | d->last_release, notify ? "yes" : "no"); | |
647 | trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, | |
648 | ring->num_items, ring->prod, ring->cons); | |
a19cbfb3 GH |
649 | if (notify) { |
650 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
651 | } | |
0b81c478 AL |
652 | SPICE_RING_PROD_ITEM(d, ring, item); |
653 | if (!item) { | |
654 | return; | |
655 | } | |
a19cbfb3 GH |
656 | *item = 0; |
657 | d->num_free_res = 0; | |
658 | d->last_release = NULL; | |
659 | qxl_ring_set_dirty(d); | |
660 | } | |
661 | ||
662 | /* called from spice server thread context only */ | |
663 | static void interface_release_resource(QXLInstance *sin, | |
664 | struct QXLReleaseInfoExt ext) | |
665 | { | |
666 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
667 | QXLReleaseRing *ring; | |
668 | uint64_t *item, id; | |
669 | ||
670 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
671 | /* host group -> vga mode update request */ | |
f4a8a424 | 672 | qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id); |
a19cbfb3 GH |
673 | return; |
674 | } | |
675 | ||
676 | /* | |
677 | * ext->info points into guest-visible memory | |
678 | * pci bar 0, $command.release_info | |
679 | */ | |
680 | ring = &qxl->ram->release_ring; | |
0b81c478 AL |
681 | SPICE_RING_PROD_ITEM(qxl, ring, item); |
682 | if (!item) { | |
683 | return; | |
684 | } | |
a19cbfb3 GH |
685 | if (*item == 0) { |
686 | /* stick head into the ring */ | |
687 | id = ext.info->id; | |
688 | ext.info->next = 0; | |
689 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
690 | *item = id; | |
691 | qxl_ring_set_dirty(qxl); | |
692 | } else { | |
693 | /* append item to the list */ | |
694 | qxl->last_release->next = ext.info->id; | |
695 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
696 | ext.info->next = 0; | |
697 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
698 | } | |
699 | qxl->last_release = ext.info; | |
700 | qxl->num_free_res++; | |
c480bb7d | 701 | trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); |
a19cbfb3 GH |
702 | qxl_push_free_res(qxl, 0); |
703 | } | |
704 | ||
705 | /* called from spice server thread context only */ | |
706 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
707 | { | |
708 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
709 | QXLCursorRing *ring; | |
710 | QXLCommand *cmd; | |
711 | int notify; | |
712 | ||
c480bb7d AL |
713 | trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); |
714 | ||
a19cbfb3 GH |
715 | switch (qxl->mode) { |
716 | case QXL_MODE_COMPAT: | |
717 | case QXL_MODE_NATIVE: | |
718 | case QXL_MODE_UNDEFINED: | |
719 | ring = &qxl->ram->cursor_ring; | |
720 | if (SPICE_RING_IS_EMPTY(ring)) { | |
721 | return false; | |
722 | } | |
0b81c478 AL |
723 | SPICE_RING_CONS_ITEM(qxl, ring, cmd); |
724 | if (!cmd) { | |
725 | return false; | |
726 | } | |
a19cbfb3 GH |
727 | ext->cmd = *cmd; |
728 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
729 | ext->flags = qxl->cmdflags; | |
730 | SPICE_RING_POP(ring, notify); | |
731 | qxl_ring_set_dirty(qxl); | |
732 | if (notify) { | |
733 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
734 | } | |
735 | qxl->guest_primary.commands++; | |
736 | qxl_track_command(qxl, ext); | |
737 | qxl_log_command(qxl, "csr", ext); | |
738 | if (qxl->id == 0) { | |
739 | qxl_render_cursor(qxl, ext); | |
740 | } | |
c480bb7d | 741 | trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
742 | return true; |
743 | default: | |
744 | return false; | |
745 | } | |
746 | } | |
747 | ||
748 | /* called from spice server thread context only */ | |
749 | static int interface_req_cursor_notification(QXLInstance *sin) | |
750 | { | |
751 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
752 | int wait = 1; | |
753 | ||
c480bb7d | 754 | trace_qxl_ring_cursor_req_notification(qxl->id); |
a19cbfb3 GH |
755 | switch (qxl->mode) { |
756 | case QXL_MODE_COMPAT: | |
757 | case QXL_MODE_NATIVE: | |
758 | case QXL_MODE_UNDEFINED: | |
759 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
760 | qxl_ring_set_dirty(qxl); | |
761 | break; | |
762 | default: | |
763 | /* nothing */ | |
764 | break; | |
765 | } | |
766 | return wait; | |
767 | } | |
768 | ||
769 | /* called from spice server thread context */ | |
770 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
771 | { | |
baeae407 AL |
772 | /* |
773 | * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in | |
774 | * use by xf86-video-qxl and is defined out in the qxl windows driver. | |
775 | * Probably was at some earlier version that is prior to git start (2009), | |
776 | * and is still guest trigerrable. | |
777 | */ | |
778 | fprintf(stderr, "%s: deprecated\n", __func__); | |
a19cbfb3 GH |
779 | } |
780 | ||
781 | /* called from spice server thread context only */ | |
782 | static int interface_flush_resources(QXLInstance *sin) | |
783 | { | |
784 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
785 | int ret; | |
786 | ||
a19cbfb3 GH |
787 | ret = qxl->num_free_res; |
788 | if (ret) { | |
789 | qxl_push_free_res(qxl, 1); | |
790 | } | |
791 | return ret; | |
792 | } | |
793 | ||
5ff4e36c AL |
794 | static void qxl_create_guest_primary_complete(PCIQXLDevice *d); |
795 | ||
5ff4e36c | 796 | /* called from spice server thread context only */ |
2e1a98c9 | 797 | static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie) |
5ff4e36c | 798 | { |
5ff4e36c AL |
799 | uint32_t current_async; |
800 | ||
801 | qemu_mutex_lock(&qxl->async_lock); | |
802 | current_async = qxl->current_async; | |
803 | qxl->current_async = QXL_UNDEFINED_IO; | |
804 | qemu_mutex_unlock(&qxl->async_lock); | |
805 | ||
c480bb7d | 806 | trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); |
2e1a98c9 AL |
807 | if (!cookie) { |
808 | fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__); | |
809 | return; | |
810 | } | |
811 | if (cookie && current_async != cookie->io) { | |
812 | fprintf(stderr, | |
2fce7edf AL |
813 | "qxl: %s: error: current_async = %d != %" |
814 | PRId64 " = cookie->io\n", __func__, current_async, cookie->io); | |
2e1a98c9 | 815 | } |
5ff4e36c | 816 | switch (current_async) { |
81fb6f15 AL |
817 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
818 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
819 | case QXL_IO_UPDATE_AREA_ASYNC: | |
820 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
821 | break; | |
5ff4e36c AL |
822 | case QXL_IO_CREATE_PRIMARY_ASYNC: |
823 | qxl_create_guest_primary_complete(qxl); | |
824 | break; | |
825 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
826 | qxl_spice_destroy_surfaces_complete(qxl); | |
827 | break; | |
828 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
2e1a98c9 | 829 | qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); |
5ff4e36c | 830 | break; |
81fb6f15 AL |
831 | default: |
832 | fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__, | |
833 | current_async); | |
5ff4e36c AL |
834 | } |
835 | qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD); | |
836 | } | |
837 | ||
81fb6f15 AL |
838 | /* called from spice server thread context only */ |
839 | static void interface_update_area_complete(QXLInstance *sin, | |
840 | uint32_t surface_id, | |
841 | QXLRect *dirty, uint32_t num_updated_rects) | |
842 | { | |
843 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
844 | int i; | |
845 | int qxl_i; | |
846 | ||
847 | qemu_mutex_lock(&qxl->ssd.lock); | |
848 | if (surface_id != 0 || !qxl->render_update_cookie_num) { | |
849 | qemu_mutex_unlock(&qxl->ssd.lock); | |
850 | return; | |
851 | } | |
c480bb7d AL |
852 | trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, |
853 | dirty->right, dirty->top, dirty->bottom); | |
854 | trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); | |
81fb6f15 AL |
855 | if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { |
856 | /* | |
857 | * overflow - treat this as a full update. Not expected to be common. | |
858 | */ | |
c480bb7d AL |
859 | trace_qxl_interface_update_area_complete_overflow(qxl->id, |
860 | QXL_NUM_DIRTY_RECTS); | |
81fb6f15 AL |
861 | qxl->guest_primary.resized = 1; |
862 | } | |
863 | if (qxl->guest_primary.resized) { | |
864 | /* | |
865 | * Don't bother copying or scheduling the bh since we will flip | |
866 | * the whole area anyway on completion of the update_area async call | |
867 | */ | |
868 | qemu_mutex_unlock(&qxl->ssd.lock); | |
869 | return; | |
870 | } | |
871 | qxl_i = qxl->num_dirty_rects; | |
872 | for (i = 0; i < num_updated_rects; i++) { | |
873 | qxl->dirty[qxl_i++] = dirty[i]; | |
874 | } | |
875 | qxl->num_dirty_rects += num_updated_rects; | |
c480bb7d AL |
876 | trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, |
877 | qxl->num_dirty_rects); | |
81fb6f15 AL |
878 | qemu_bh_schedule(qxl->update_area_bh); |
879 | qemu_mutex_unlock(&qxl->ssd.lock); | |
880 | } | |
881 | ||
2e1a98c9 AL |
882 | /* called from spice server thread context only */ |
883 | static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token) | |
884 | { | |
885 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
5dba0d45 | 886 | QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token; |
2e1a98c9 AL |
887 | |
888 | switch (cookie->type) { | |
889 | case QXL_COOKIE_TYPE_IO: | |
890 | interface_async_complete_io(qxl, cookie); | |
81fb6f15 AL |
891 | g_free(cookie); |
892 | break; | |
893 | case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA: | |
894 | qxl_render_update_area_done(qxl, cookie); | |
2e1a98c9 AL |
895 | break; |
896 | default: | |
897 | fprintf(stderr, "qxl: %s: unexpected cookie type %d\n", | |
898 | __func__, cookie->type); | |
81fb6f15 | 899 | g_free(cookie); |
2e1a98c9 | 900 | } |
2e1a98c9 AL |
901 | } |
902 | ||
a19cbfb3 GH |
903 | static const QXLInterface qxl_interface = { |
904 | .base.type = SPICE_INTERFACE_QXL, | |
905 | .base.description = "qxl gpu", | |
906 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
907 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
908 | ||
909 | .attache_worker = interface_attach_worker, | |
910 | .set_compression_level = interface_set_compression_level, | |
911 | .set_mm_time = interface_set_mm_time, | |
912 | .get_init_info = interface_get_init_info, | |
913 | ||
914 | /* the callbacks below are called from spice server thread context */ | |
915 | .get_command = interface_get_command, | |
916 | .req_cmd_notification = interface_req_cmd_notification, | |
917 | .release_resource = interface_release_resource, | |
918 | .get_cursor_command = interface_get_cursor_command, | |
919 | .req_cursor_notification = interface_req_cursor_notification, | |
920 | .notify_update = interface_notify_update, | |
921 | .flush_resources = interface_flush_resources, | |
5ff4e36c | 922 | .async_complete = interface_async_complete, |
81fb6f15 | 923 | .update_area_complete = interface_update_area_complete, |
a19cbfb3 GH |
924 | }; |
925 | ||
926 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
927 | { | |
928 | if (d->mode == QXL_MODE_VGA) { | |
929 | return; | |
930 | } | |
c480bb7d | 931 | trace_qxl_enter_vga_mode(d->id); |
a19cbfb3 GH |
932 | qemu_spice_create_host_primary(&d->ssd); |
933 | d->mode = QXL_MODE_VGA; | |
934 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
935 | } | |
936 | ||
937 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
938 | { | |
939 | if (d->mode != QXL_MODE_VGA) { | |
940 | return; | |
941 | } | |
c480bb7d | 942 | trace_qxl_exit_vga_mode(d->id); |
5ff4e36c | 943 | qxl_destroy_primary(d, QXL_SYNC); |
a19cbfb3 GH |
944 | } |
945 | ||
40010aea | 946 | static void qxl_update_irq(PCIQXLDevice *d) |
a19cbfb3 GH |
947 | { |
948 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
949 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
950 | int level = !!(pending & mask); | |
951 | qemu_set_irq(d->pci.irq[0], level); | |
952 | qxl_ring_set_dirty(d); | |
953 | } | |
954 | ||
a19cbfb3 GH |
955 | static void qxl_check_state(PCIQXLDevice *d) |
956 | { | |
957 | QXLRam *ram = d->ram; | |
958 | ||
be48e995 YH |
959 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
960 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
961 | } |
962 | ||
963 | static void qxl_reset_state(PCIQXLDevice *d) | |
964 | { | |
a19cbfb3 GH |
965 | QXLRom *rom = d->rom; |
966 | ||
be48e995 | 967 | qxl_check_state(d); |
a19cbfb3 GH |
968 | d->shadow_rom.update_id = cpu_to_le32(0); |
969 | *rom = d->shadow_rom; | |
970 | qxl_rom_set_dirty(d); | |
971 | init_qxl_ram(d); | |
972 | d->num_free_res = 0; | |
973 | d->last_release = NULL; | |
974 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
975 | } | |
976 | ||
977 | static void qxl_soft_reset(PCIQXLDevice *d) | |
978 | { | |
c480bb7d | 979 | trace_qxl_soft_reset(d->id); |
a19cbfb3 GH |
980 | qxl_check_state(d); |
981 | ||
982 | if (d->id == 0) { | |
983 | qxl_enter_vga_mode(d); | |
984 | } else { | |
985 | d->mode = QXL_MODE_UNDEFINED; | |
986 | } | |
987 | } | |
988 | ||
989 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
990 | { | |
c480bb7d | 991 | trace_qxl_hard_reset(d->id, loadvm); |
a19cbfb3 | 992 | |
aee32bf3 GH |
993 | qxl_spice_reset_cursor(d); |
994 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
995 | qxl_reset_surfaces(d); |
996 | qxl_reset_memslots(d); | |
997 | ||
998 | /* pre loadvm reset must not touch QXLRam. This lives in | |
999 | * device memory, is migrated together with RAM and thus | |
1000 | * already loaded at this point */ | |
1001 | if (!loadvm) { | |
1002 | qxl_reset_state(d); | |
1003 | } | |
1004 | qemu_spice_create_host_memslot(&d->ssd); | |
1005 | qxl_soft_reset(d); | |
a19cbfb3 GH |
1006 | } |
1007 | ||
1008 | static void qxl_reset_handler(DeviceState *dev) | |
1009 | { | |
1010 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
c480bb7d | 1011 | |
a19cbfb3 GH |
1012 | qxl_hard_reset(d, 0); |
1013 | } | |
1014 | ||
1015 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
1016 | { | |
1017 | VGACommonState *vga = opaque; | |
1018 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
1019 | ||
c480bb7d | 1020 | trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); |
a19cbfb3 | 1021 | if (qxl->mode != QXL_MODE_VGA) { |
5ff4e36c | 1022 | qxl_destroy_primary(qxl, QXL_SYNC); |
a19cbfb3 GH |
1023 | qxl_soft_reset(qxl); |
1024 | } | |
1025 | vga_ioport_write(opaque, addr, val); | |
1026 | } | |
1027 | ||
f67ab77a GH |
1028 | static const MemoryRegionPortio qxl_vga_portio_list[] = { |
1029 | { 0x04, 2, 1, .read = vga_ioport_read, | |
1030 | .write = qxl_vga_ioport_write }, /* 3b4 */ | |
1031 | { 0x0a, 1, 1, .read = vga_ioport_read, | |
1032 | .write = qxl_vga_ioport_write }, /* 3ba */ | |
1033 | { 0x10, 16, 1, .read = vga_ioport_read, | |
1034 | .write = qxl_vga_ioport_write }, /* 3c0 */ | |
1035 | { 0x24, 2, 1, .read = vga_ioport_read, | |
1036 | .write = qxl_vga_ioport_write }, /* 3d4 */ | |
1037 | { 0x2a, 1, 1, .read = vga_ioport_read, | |
1038 | .write = qxl_vga_ioport_write }, /* 3da */ | |
1039 | PORTIO_END_OF_LIST(), | |
1040 | }; | |
1041 | ||
e954ea28 AL |
1042 | static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta, |
1043 | qxl_async_io async) | |
a19cbfb3 GH |
1044 | { |
1045 | static const int regions[] = { | |
1046 | QXL_RAM_RANGE_INDEX, | |
1047 | QXL_VRAM_RANGE_INDEX, | |
6f2b175a | 1048 | QXL_VRAM64_RANGE_INDEX, |
a19cbfb3 GH |
1049 | }; |
1050 | uint64_t guest_start; | |
1051 | uint64_t guest_end; | |
1052 | int pci_region; | |
1053 | pcibus_t pci_start; | |
1054 | pcibus_t pci_end; | |
1055 | intptr_t virt_start; | |
1056 | QXLDevMemSlot memslot; | |
1057 | int i; | |
1058 | ||
1059 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
1060 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
1061 | ||
c480bb7d | 1062 | trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); |
a19cbfb3 | 1063 | |
e954ea28 | 1064 | if (slot_id >= NUM_MEMSLOTS) { |
0a530548 | 1065 | qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__, |
e954ea28 AL |
1066 | slot_id, NUM_MEMSLOTS); |
1067 | return 1; | |
1068 | } | |
1069 | if (guest_start > guest_end) { | |
0a530548 | 1070 | qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64 |
e954ea28 AL |
1071 | " > 0x%" PRIx64, __func__, guest_start, guest_end); |
1072 | return 1; | |
1073 | } | |
a19cbfb3 GH |
1074 | |
1075 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
1076 | pci_region = regions[i]; | |
1077 | pci_start = d->pci.io_regions[pci_region].addr; | |
1078 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
1079 | /* mapped? */ | |
1080 | if (pci_start == -1) { | |
1081 | continue; | |
1082 | } | |
1083 | /* start address in range ? */ | |
1084 | if (guest_start < pci_start || guest_start > pci_end) { | |
1085 | continue; | |
1086 | } | |
1087 | /* end address in range ? */ | |
1088 | if (guest_end > pci_end) { | |
1089 | continue; | |
1090 | } | |
1091 | /* passed */ | |
1092 | break; | |
1093 | } | |
e954ea28 | 1094 | if (i == ARRAY_SIZE(regions)) { |
0a530548 | 1095 | qxl_set_guest_bug(d, "%s: finished loop without match", __func__); |
e954ea28 AL |
1096 | return 1; |
1097 | } | |
a19cbfb3 GH |
1098 | |
1099 | switch (pci_region) { | |
1100 | case QXL_RAM_RANGE_INDEX: | |
b1950430 | 1101 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram); |
a19cbfb3 GH |
1102 | break; |
1103 | case QXL_VRAM_RANGE_INDEX: | |
6f2b175a | 1104 | case 4 /* vram 64bit */: |
b1950430 | 1105 | virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar); |
a19cbfb3 GH |
1106 | break; |
1107 | default: | |
1108 | /* should not happen */ | |
0a530548 | 1109 | qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region); |
e954ea28 | 1110 | return 1; |
a19cbfb3 GH |
1111 | } |
1112 | ||
1113 | memslot.slot_id = slot_id; | |
1114 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
1115 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
1116 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
1117 | memslot.addr_delta = memslot.virt_start - delta; | |
1118 | memslot.generation = d->rom->slot_generation = 0; | |
1119 | qxl_rom_set_dirty(d); | |
1120 | ||
5ff4e36c | 1121 | qemu_spice_add_memslot(&d->ssd, &memslot, async); |
a19cbfb3 GH |
1122 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
1123 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
1124 | d->guest_slots[slot_id].delta = delta; | |
1125 | d->guest_slots[slot_id].active = 1; | |
e954ea28 | 1126 | return 0; |
a19cbfb3 GH |
1127 | } |
1128 | ||
1129 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
1130 | { | |
5c59d118 | 1131 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
1132 | d->guest_slots[slot_id].active = 0; |
1133 | } | |
1134 | ||
1135 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
1136 | { | |
aee32bf3 | 1137 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
1138 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
1139 | } | |
1140 | ||
1141 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
1142 | { | |
c480bb7d | 1143 | trace_qxl_reset_surfaces(d->id); |
a19cbfb3 | 1144 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1145 | qxl_spice_destroy_surfaces(d, QXL_SYNC); |
a19cbfb3 GH |
1146 | } |
1147 | ||
e25139b3 | 1148 | /* can be also called from spice server thread context */ |
a19cbfb3 GH |
1149 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) |
1150 | { | |
1151 | uint64_t phys = le64_to_cpu(pqxl); | |
1152 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
1153 | uint64_t offset = phys & 0xffffffffffff; | |
1154 | ||
1155 | switch (group_id) { | |
1156 | case MEMSLOT_GROUP_HOST: | |
f4a8a424 | 1157 | return (void *)(intptr_t)offset; |
a19cbfb3 | 1158 | case MEMSLOT_GROUP_GUEST: |
4b635c59 | 1159 | if (slot >= NUM_MEMSLOTS) { |
0a530548 AL |
1160 | qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot, |
1161 | NUM_MEMSLOTS); | |
4b635c59 AL |
1162 | return NULL; |
1163 | } | |
1164 | if (!qxl->guest_slots[slot].active) { | |
0a530548 | 1165 | qxl_set_guest_bug(qxl, "inactive slot %d\n", slot); |
4b635c59 AL |
1166 | return NULL; |
1167 | } | |
1168 | if (offset < qxl->guest_slots[slot].delta) { | |
0a530548 AL |
1169 | qxl_set_guest_bug(qxl, |
1170 | "slot %d offset %"PRIu64" < delta %"PRIu64"\n", | |
4b635c59 AL |
1171 | slot, offset, qxl->guest_slots[slot].delta); |
1172 | return NULL; | |
1173 | } | |
a19cbfb3 | 1174 | offset -= qxl->guest_slots[slot].delta; |
4b635c59 | 1175 | if (offset > qxl->guest_slots[slot].size) { |
0a530548 AL |
1176 | qxl_set_guest_bug(qxl, |
1177 | "slot %d offset %"PRIu64" > size %"PRIu64"\n", | |
4b635c59 AL |
1178 | slot, offset, qxl->guest_slots[slot].size); |
1179 | return NULL; | |
1180 | } | |
a19cbfb3 | 1181 | return qxl->guest_slots[slot].ptr + offset; |
a19cbfb3 | 1182 | } |
4b635c59 | 1183 | return NULL; |
a19cbfb3 GH |
1184 | } |
1185 | ||
5ff4e36c AL |
1186 | static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl) |
1187 | { | |
1188 | /* for local rendering */ | |
1189 | qxl_render_resize(qxl); | |
1190 | } | |
1191 | ||
1192 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, | |
1193 | qxl_async_io async) | |
a19cbfb3 GH |
1194 | { |
1195 | QXLDevSurfaceCreate surface; | |
1196 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
1197 | ||
ddf9f4b7 | 1198 | if (qxl->mode == QXL_MODE_NATIVE) { |
0a530548 | 1199 | qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE", |
ddf9f4b7 AL |
1200 | __func__); |
1201 | } | |
a19cbfb3 GH |
1202 | qxl_exit_vga_mode(qxl); |
1203 | ||
a19cbfb3 GH |
1204 | surface.format = le32_to_cpu(sc->format); |
1205 | surface.height = le32_to_cpu(sc->height); | |
1206 | surface.mem = le64_to_cpu(sc->mem); | |
1207 | surface.position = le32_to_cpu(sc->position); | |
1208 | surface.stride = le32_to_cpu(sc->stride); | |
1209 | surface.width = le32_to_cpu(sc->width); | |
1210 | surface.type = le32_to_cpu(sc->type); | |
1211 | surface.flags = le32_to_cpu(sc->flags); | |
c480bb7d AL |
1212 | trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, |
1213 | sc->format, sc->position); | |
1214 | trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, | |
1215 | sc->flags); | |
a19cbfb3 GH |
1216 | |
1217 | surface.mouse_mode = true; | |
1218 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
1219 | if (loadvm) { | |
1220 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
1221 | } | |
1222 | ||
1223 | qxl->mode = QXL_MODE_NATIVE; | |
1224 | qxl->cmdflags = 0; | |
5ff4e36c | 1225 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); |
a19cbfb3 | 1226 | |
5ff4e36c AL |
1227 | if (async == QXL_SYNC) { |
1228 | qxl_create_guest_primary_complete(qxl); | |
1229 | } | |
a19cbfb3 GH |
1230 | } |
1231 | ||
5ff4e36c AL |
1232 | /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or |
1233 | * done (in QXL_SYNC case), 0 otherwise. */ | |
1234 | static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) | |
a19cbfb3 GH |
1235 | { |
1236 | if (d->mode == QXL_MODE_UNDEFINED) { | |
5ff4e36c | 1237 | return 0; |
a19cbfb3 | 1238 | } |
c480bb7d | 1239 | trace_qxl_destroy_primary(d->id); |
a19cbfb3 | 1240 | d->mode = QXL_MODE_UNDEFINED; |
5ff4e36c | 1241 | qemu_spice_destroy_primary_surface(&d->ssd, 0, async); |
30f6da66 | 1242 | qxl_spice_reset_cursor(d); |
5ff4e36c | 1243 | return 1; |
a19cbfb3 GH |
1244 | } |
1245 | ||
1246 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1247 | { | |
1248 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1249 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1250 | QXLMode *mode = d->modes->modes + modenr; | |
1251 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1252 | QXLMemSlot slot = { | |
1253 | .mem_start = start, | |
1254 | .mem_end = end | |
1255 | }; | |
1256 | QXLSurfaceCreate surface = { | |
1257 | .width = mode->x_res, | |
1258 | .height = mode->y_res, | |
1259 | .stride = -mode->x_res * 4, | |
1260 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1261 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1262 | .mouse_mode = true, | |
1263 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1264 | }; | |
1265 | ||
c480bb7d AL |
1266 | trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, |
1267 | devmem); | |
a19cbfb3 GH |
1268 | if (!loadvm) { |
1269 | qxl_hard_reset(d, 0); | |
1270 | } | |
1271 | ||
1272 | d->guest_slots[0].slot = slot; | |
e954ea28 | 1273 | assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0); |
a19cbfb3 GH |
1274 | |
1275 | d->guest_primary.surface = surface; | |
5ff4e36c | 1276 | qxl_create_guest_primary(d, 0, QXL_SYNC); |
a19cbfb3 GH |
1277 | |
1278 | d->mode = QXL_MODE_COMPAT; | |
1279 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
1280 | #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ | |
1281 | if (mode->bits == 16) { | |
1282 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1283 | } | |
1284 | #endif | |
1285 | d->shadow_rom.mode = cpu_to_le32(modenr); | |
1286 | d->rom->mode = cpu_to_le32(modenr); | |
1287 | qxl_rom_set_dirty(d); | |
1288 | } | |
1289 | ||
b1950430 AK |
1290 | static void ioport_write(void *opaque, target_phys_addr_t addr, |
1291 | uint64_t val, unsigned size) | |
a19cbfb3 GH |
1292 | { |
1293 | PCIQXLDevice *d = opaque; | |
b1950430 | 1294 | uint32_t io_port = addr; |
5ff4e36c | 1295 | qxl_async_io async = QXL_SYNC; |
5ff4e36c | 1296 | uint32_t orig_io_port = io_port; |
a19cbfb3 GH |
1297 | |
1298 | switch (io_port) { | |
1299 | case QXL_IO_RESET: | |
1300 | case QXL_IO_SET_MODE: | |
1301 | case QXL_IO_MEMSLOT_ADD: | |
1302 | case QXL_IO_MEMSLOT_DEL: | |
1303 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1304 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1305 | case QXL_IO_LOG: |
5ff4e36c AL |
1306 | case QXL_IO_MEMSLOT_ADD_ASYNC: |
1307 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
a19cbfb3 GH |
1308 | break; |
1309 | default: | |
e21a298a | 1310 | if (d->mode != QXL_MODE_VGA) { |
a19cbfb3 | 1311 | break; |
e21a298a | 1312 | } |
c480bb7d AL |
1313 | trace_qxl_io_unexpected_vga_mode(d->id, |
1314 | io_port, io_port_to_string(io_port)); | |
5ff4e36c AL |
1315 | /* be nice to buggy guest drivers */ |
1316 | if (io_port >= QXL_IO_UPDATE_AREA_ASYNC && | |
1317 | io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) { | |
1318 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1319 | } | |
a19cbfb3 GH |
1320 | return; |
1321 | } | |
1322 | ||
5ff4e36c AL |
1323 | /* we change the io_port to avoid ifdeffery in the main switch */ |
1324 | orig_io_port = io_port; | |
1325 | switch (io_port) { | |
1326 | case QXL_IO_UPDATE_AREA_ASYNC: | |
1327 | io_port = QXL_IO_UPDATE_AREA; | |
1328 | goto async_common; | |
1329 | case QXL_IO_MEMSLOT_ADD_ASYNC: | |
1330 | io_port = QXL_IO_MEMSLOT_ADD; | |
1331 | goto async_common; | |
1332 | case QXL_IO_CREATE_PRIMARY_ASYNC: | |
1333 | io_port = QXL_IO_CREATE_PRIMARY; | |
1334 | goto async_common; | |
1335 | case QXL_IO_DESTROY_PRIMARY_ASYNC: | |
1336 | io_port = QXL_IO_DESTROY_PRIMARY; | |
1337 | goto async_common; | |
1338 | case QXL_IO_DESTROY_SURFACE_ASYNC: | |
1339 | io_port = QXL_IO_DESTROY_SURFACE_WAIT; | |
1340 | goto async_common; | |
1341 | case QXL_IO_DESTROY_ALL_SURFACES_ASYNC: | |
1342 | io_port = QXL_IO_DESTROY_ALL_SURFACES; | |
3e16b9c5 AL |
1343 | goto async_common; |
1344 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
5ff4e36c AL |
1345 | async_common: |
1346 | async = QXL_ASYNC; | |
1347 | qemu_mutex_lock(&d->async_lock); | |
1348 | if (d->current_async != QXL_UNDEFINED_IO) { | |
0a530548 | 1349 | qxl_set_guest_bug(d, "%d async started before last (%d) complete", |
5ff4e36c AL |
1350 | io_port, d->current_async); |
1351 | qemu_mutex_unlock(&d->async_lock); | |
1352 | return; | |
1353 | } | |
1354 | d->current_async = orig_io_port; | |
1355 | qemu_mutex_unlock(&d->async_lock); | |
5ff4e36c AL |
1356 | break; |
1357 | default: | |
1358 | break; | |
1359 | } | |
c480bb7d AL |
1360 | trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size, |
1361 | async); | |
5ff4e36c | 1362 | |
a19cbfb3 GH |
1363 | switch (io_port) { |
1364 | case QXL_IO_UPDATE_AREA: | |
1365 | { | |
81fb6f15 | 1366 | QXLCookie *cookie = NULL; |
a19cbfb3 | 1367 | QXLRect update = d->ram->update_area; |
81fb6f15 AL |
1368 | |
1369 | if (async == QXL_ASYNC) { | |
1370 | cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO, | |
1371 | QXL_IO_UPDATE_AREA_ASYNC); | |
1372 | cookie->u.area = update; | |
1373 | } | |
aee32bf3 | 1374 | qxl_spice_update_area(d, d->ram->update_surface, |
81fb6f15 AL |
1375 | cookie ? &cookie->u.area : &update, |
1376 | NULL, 0, 0, async, cookie); | |
a19cbfb3 GH |
1377 | break; |
1378 | } | |
1379 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1380 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1381 | break; |
1382 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1383 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1384 | break; |
1385 | case QXL_IO_UPDATE_IRQ: | |
40010aea | 1386 | qxl_update_irq(d); |
a19cbfb3 GH |
1387 | break; |
1388 | case QXL_IO_NOTIFY_OOM: | |
a19cbfb3 GH |
1389 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { |
1390 | break; | |
1391 | } | |
1392 | d->oom_running = 1; | |
aee32bf3 | 1393 | qxl_spice_oom(d); |
a19cbfb3 GH |
1394 | d->oom_running = 0; |
1395 | break; | |
1396 | case QXL_IO_SET_MODE: | |
a19cbfb3 GH |
1397 | qxl_set_mode(d, val, 0); |
1398 | break; | |
1399 | case QXL_IO_LOG: | |
1400 | if (d->guestdebug) { | |
a680f7e7 | 1401 | fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id, |
6ebebb55 | 1402 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); |
a19cbfb3 GH |
1403 | } |
1404 | break; | |
1405 | case QXL_IO_RESET: | |
a19cbfb3 GH |
1406 | qxl_hard_reset(d, 0); |
1407 | break; | |
1408 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 | 1409 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1410 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); |
2bce0400 GH |
1411 | break; |
1412 | } | |
1413 | if (d->guest_slots[val].active) { | |
0a530548 AL |
1414 | qxl_set_guest_bug(d, |
1415 | "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
2bce0400 GH |
1416 | break; |
1417 | } | |
a19cbfb3 | 1418 | d->guest_slots[val].slot = d->ram->mem_slot; |
5ff4e36c | 1419 | qxl_add_memslot(d, val, 0, async); |
a19cbfb3 GH |
1420 | break; |
1421 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 | 1422 | if (val >= NUM_MEMSLOTS) { |
0a530548 | 1423 | qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); |
2bce0400 GH |
1424 | break; |
1425 | } | |
a19cbfb3 GH |
1426 | qxl_del_memslot(d, val); |
1427 | break; | |
1428 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 | 1429 | if (val != 0) { |
0a530548 | 1430 | qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1431 | async); |
1432 | goto cancel_async; | |
2bce0400 | 1433 | } |
a19cbfb3 | 1434 | d->guest_primary.surface = d->ram->create_surface; |
5ff4e36c | 1435 | qxl_create_guest_primary(d, 0, async); |
a19cbfb3 GH |
1436 | break; |
1437 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 | 1438 | if (val != 0) { |
0a530548 | 1439 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0", |
5ff4e36c AL |
1440 | async); |
1441 | goto cancel_async; | |
1442 | } | |
5ff4e36c | 1443 | if (!qxl_destroy_primary(d, async)) { |
c480bb7d AL |
1444 | trace_qxl_io_destroy_primary_ignored(d->id, |
1445 | qxl_mode_to_string(d->mode)); | |
5ff4e36c | 1446 | goto cancel_async; |
2bce0400 | 1447 | } |
a19cbfb3 GH |
1448 | break; |
1449 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
5ff4e36c | 1450 | if (val >= NUM_SURFACES) { |
0a530548 | 1451 | qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):" |
5f8daf2e | 1452 | "%" PRIu64 " >= NUM_SURFACES", async, val); |
5ff4e36c AL |
1453 | goto cancel_async; |
1454 | } | |
1455 | qxl_spice_destroy_surface_wait(d, val, async); | |
a19cbfb3 | 1456 | break; |
3e16b9c5 AL |
1457 | case QXL_IO_FLUSH_RELEASE: { |
1458 | QXLReleaseRing *ring = &d->ram->release_ring; | |
1459 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
1460 | fprintf(stderr, | |
1461 | "ERROR: no flush, full release ring [p%d,%dc]\n", | |
1462 | ring->prod, ring->cons); | |
1463 | } | |
1464 | qxl_push_free_res(d, 1 /* flush */); | |
3e16b9c5 AL |
1465 | break; |
1466 | } | |
1467 | case QXL_IO_FLUSH_SURFACES_ASYNC: | |
3e16b9c5 AL |
1468 | qxl_spice_flush_surfaces_async(d); |
1469 | break; | |
a19cbfb3 | 1470 | case QXL_IO_DESTROY_ALL_SURFACES: |
5ff4e36c AL |
1471 | d->mode = QXL_MODE_UNDEFINED; |
1472 | qxl_spice_destroy_surfaces(d, async); | |
a19cbfb3 GH |
1473 | break; |
1474 | default: | |
0a530548 | 1475 | qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port); |
a19cbfb3 | 1476 | } |
5ff4e36c AL |
1477 | return; |
1478 | cancel_async: | |
5ff4e36c AL |
1479 | if (async) { |
1480 | qxl_send_events(d, QXL_INTERRUPT_IO_CMD); | |
1481 | qemu_mutex_lock(&d->async_lock); | |
1482 | d->current_async = QXL_UNDEFINED_IO; | |
1483 | qemu_mutex_unlock(&d->async_lock); | |
1484 | } | |
a19cbfb3 GH |
1485 | } |
1486 | ||
b1950430 AK |
1487 | static uint64_t ioport_read(void *opaque, target_phys_addr_t addr, |
1488 | unsigned size) | |
a19cbfb3 GH |
1489 | { |
1490 | PCIQXLDevice *d = opaque; | |
1491 | ||
c480bb7d | 1492 | trace_qxl_io_read_unexpected(d->id); |
a19cbfb3 GH |
1493 | return 0xff; |
1494 | } | |
1495 | ||
b1950430 AK |
1496 | static const MemoryRegionOps qxl_io_ops = { |
1497 | .read = ioport_read, | |
1498 | .write = ioport_write, | |
1499 | .valid = { | |
1500 | .min_access_size = 1, | |
1501 | .max_access_size = 1, | |
1502 | }, | |
1503 | }; | |
a19cbfb3 GH |
1504 | |
1505 | static void pipe_read(void *opaque) | |
1506 | { | |
1507 | PCIQXLDevice *d = opaque; | |
1508 | char dummy; | |
1509 | int len; | |
1510 | ||
1511 | do { | |
1512 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1513 | } while (len == sizeof(dummy)); | |
40010aea | 1514 | qxl_update_irq(d); |
a19cbfb3 GH |
1515 | } |
1516 | ||
a19cbfb3 GH |
1517 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) |
1518 | { | |
1519 | uint32_t old_pending; | |
1520 | uint32_t le_events = cpu_to_le32(events); | |
1521 | ||
1522 | assert(d->ssd.running); | |
1523 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); | |
1524 | if ((old_pending & le_events) == le_events) { | |
1525 | return; | |
1526 | } | |
691f5c7b | 1527 | if (qemu_thread_is_self(&d->main)) { |
40010aea | 1528 | qxl_update_irq(d); |
a19cbfb3 GH |
1529 | } else { |
1530 | if (write(d->pipe[1], d, 1) != 1) { | |
75fe0d7b | 1531 | dprint(d, 1, "%s: write to pipe failed\n", __func__); |
a19cbfb3 GH |
1532 | } |
1533 | } | |
1534 | } | |
1535 | ||
1536 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1537 | { | |
aa3db423 AL |
1538 | if (pipe(d->pipe) < 0) { |
1539 | fprintf(stderr, "%s:%s: qxl pipe creation failed\n", | |
1540 | __FILE__, __func__); | |
1541 | exit(1); | |
1542 | } | |
1543 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); | |
1544 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); | |
1545 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1546 | ||
1547 | qemu_thread_get_self(&d->main); | |
1548 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); | |
a19cbfb3 GH |
1549 | } |
1550 | ||
1551 | /* graphics console */ | |
1552 | ||
1553 | static void qxl_hw_update(void *opaque) | |
1554 | { | |
1555 | PCIQXLDevice *qxl = opaque; | |
1556 | VGACommonState *vga = &qxl->vga; | |
1557 | ||
1558 | switch (qxl->mode) { | |
1559 | case QXL_MODE_VGA: | |
1560 | vga->update(vga); | |
1561 | break; | |
1562 | case QXL_MODE_COMPAT: | |
1563 | case QXL_MODE_NATIVE: | |
1564 | qxl_render_update(qxl); | |
1565 | break; | |
1566 | default: | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | ||
1571 | static void qxl_hw_invalidate(void *opaque) | |
1572 | { | |
1573 | PCIQXLDevice *qxl = opaque; | |
1574 | VGACommonState *vga = &qxl->vga; | |
1575 | ||
1576 | vga->invalidate(vga); | |
1577 | } | |
1578 | ||
45efb161 | 1579 | static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch) |
a19cbfb3 GH |
1580 | { |
1581 | PCIQXLDevice *qxl = opaque; | |
1582 | VGACommonState *vga = &qxl->vga; | |
1583 | ||
1584 | switch (qxl->mode) { | |
1585 | case QXL_MODE_COMPAT: | |
1586 | case QXL_MODE_NATIVE: | |
1587 | qxl_render_update(qxl); | |
1588 | ppm_save(filename, qxl->ssd.ds->surface); | |
1589 | break; | |
1590 | case QXL_MODE_VGA: | |
45efb161 | 1591 | vga->screen_dump(vga, filename, cswitch); |
a19cbfb3 GH |
1592 | break; |
1593 | default: | |
1594 | break; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) | |
1599 | { | |
1600 | PCIQXLDevice *qxl = opaque; | |
1601 | VGACommonState *vga = &qxl->vga; | |
1602 | ||
1603 | if (qxl->mode == QXL_MODE_VGA) { | |
1604 | vga->text_update(vga, chardata); | |
1605 | return; | |
1606 | } | |
1607 | } | |
1608 | ||
e25139b3 YH |
1609 | static void qxl_dirty_surfaces(PCIQXLDevice *qxl) |
1610 | { | |
1611 | intptr_t vram_start; | |
1612 | int i; | |
1613 | ||
2aa9e85c | 1614 | if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) { |
e25139b3 YH |
1615 | return; |
1616 | } | |
1617 | ||
1618 | /* dirty the primary surface */ | |
1619 | qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset, | |
1620 | qxl->shadow_rom.surface0_area_size); | |
1621 | ||
1622 | vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar); | |
1623 | ||
1624 | /* dirty the off-screen surfaces */ | |
1625 | for (i = 0; i < NUM_SURFACES; i++) { | |
1626 | QXLSurfaceCmd *cmd; | |
1627 | intptr_t surface_offset; | |
1628 | int surface_size; | |
1629 | ||
1630 | if (qxl->guest_surfaces.cmds[i] == 0) { | |
1631 | continue; | |
1632 | } | |
1633 | ||
1634 | cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i], | |
1635 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1636 | assert(cmd); |
e25139b3 YH |
1637 | assert(cmd->type == QXL_SURFACE_CMD_CREATE); |
1638 | surface_offset = (intptr_t)qxl_phys2virt(qxl, | |
1639 | cmd->u.surface_create.data, | |
1640 | MEMSLOT_GROUP_GUEST); | |
fae2afb1 | 1641 | assert(surface_offset); |
e25139b3 YH |
1642 | surface_offset -= vram_start; |
1643 | surface_size = cmd->u.surface_create.height * | |
1644 | abs(cmd->u.surface_create.stride); | |
c480bb7d | 1645 | trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size); |
e25139b3 YH |
1646 | qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size); |
1647 | } | |
1648 | } | |
1649 | ||
1dfb4dd9 LC |
1650 | static void qxl_vm_change_state_handler(void *opaque, int running, |
1651 | RunState state) | |
a19cbfb3 GH |
1652 | { |
1653 | PCIQXLDevice *qxl = opaque; | |
1dfb4dd9 | 1654 | qemu_spice_vm_change_state_handler(&qxl->ssd, running, state); |
a19cbfb3 | 1655 | |
efbf2950 YH |
1656 | if (running) { |
1657 | /* | |
1658 | * if qxl_send_events was called from spice server context before | |
40010aea | 1659 | * migration ended, qxl_update_irq for these events might not have been |
efbf2950 YH |
1660 | * called |
1661 | */ | |
40010aea | 1662 | qxl_update_irq(qxl); |
e25139b3 YH |
1663 | } else { |
1664 | /* make sure surfaces are saved before migration */ | |
1665 | qxl_dirty_surfaces(qxl); | |
a19cbfb3 GH |
1666 | } |
1667 | } | |
1668 | ||
1669 | /* display change listener */ | |
1670 | ||
1671 | static void display_update(struct DisplayState *ds, int x, int y, int w, int h) | |
1672 | { | |
1673 | if (qxl0->mode == QXL_MODE_VGA) { | |
1674 | qemu_spice_display_update(&qxl0->ssd, x, y, w, h); | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | static void display_resize(struct DisplayState *ds) | |
1679 | { | |
1680 | if (qxl0->mode == QXL_MODE_VGA) { | |
1681 | qemu_spice_display_resize(&qxl0->ssd); | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | static void display_refresh(struct DisplayState *ds) | |
1686 | { | |
1687 | if (qxl0->mode == QXL_MODE_VGA) { | |
1688 | qemu_spice_display_refresh(&qxl0->ssd); | |
bb5a8cd5 AL |
1689 | } else { |
1690 | qemu_mutex_lock(&qxl0->ssd.lock); | |
1691 | qemu_spice_cursor_refresh_unlocked(&qxl0->ssd); | |
1692 | qemu_mutex_unlock(&qxl0->ssd.lock); | |
a19cbfb3 GH |
1693 | } |
1694 | } | |
1695 | ||
1696 | static DisplayChangeListener display_listener = { | |
1697 | .dpy_update = display_update, | |
1698 | .dpy_resize = display_resize, | |
1699 | .dpy_refresh = display_refresh, | |
1700 | }; | |
1701 | ||
a974192c GH |
1702 | static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb) |
1703 | { | |
1704 | /* vga ram (bar 0) */ | |
017438ee GH |
1705 | if (qxl->ram_size_mb != -1) { |
1706 | qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024; | |
1707 | } | |
a974192c GH |
1708 | if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) { |
1709 | qxl->vga.vram_size = ram_min_mb * 1024 * 1024; | |
1710 | } | |
1711 | ||
6f2b175a GH |
1712 | /* vram32 (surfaces, 32bit, bar 1) */ |
1713 | if (qxl->vram32_size_mb != -1) { | |
1714 | qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024; | |
1715 | } | |
1716 | if (qxl->vram32_size < 4096) { | |
1717 | qxl->vram32_size = 4096; | |
1718 | } | |
1719 | ||
1720 | /* vram (surfaces, 64bit, bar 4+5) */ | |
017438ee GH |
1721 | if (qxl->vram_size_mb != -1) { |
1722 | qxl->vram_size = qxl->vram_size_mb * 1024 * 1024; | |
1723 | } | |
6f2b175a GH |
1724 | if (qxl->vram_size < qxl->vram32_size) { |
1725 | qxl->vram_size = qxl->vram32_size; | |
a974192c | 1726 | } |
6f2b175a | 1727 | |
a974192c | 1728 | if (qxl->revision == 1) { |
6f2b175a | 1729 | qxl->vram32_size = 4096; |
a974192c GH |
1730 | qxl->vram_size = 4096; |
1731 | } | |
a974192c | 1732 | qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1); |
6f2b175a | 1733 | qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1); |
a974192c GH |
1734 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); |
1735 | } | |
1736 | ||
a19cbfb3 GH |
1737 | static int qxl_init_common(PCIQXLDevice *qxl) |
1738 | { | |
1739 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1740 | uint32_t pci_device_rev; |
1741 | uint32_t io_size; | |
1742 | ||
1743 | qxl->mode = QXL_MODE_UNDEFINED; | |
1744 | qxl->generation = 1; | |
1745 | qxl->num_memslots = NUM_MEMSLOTS; | |
1746 | qxl->num_surfaces = NUM_SURFACES; | |
14898cf6 | 1747 | qemu_mutex_init(&qxl->track_lock); |
5ff4e36c AL |
1748 | qemu_mutex_init(&qxl->async_lock); |
1749 | qxl->current_async = QXL_UNDEFINED_IO; | |
a19cbfb3 GH |
1750 | |
1751 | switch (qxl->revision) { | |
1752 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 | 1753 | pci_device_rev = QXL_REVISION_STABLE_V04; |
3f6297b9 | 1754 | io_size = 8; |
a19cbfb3 GH |
1755 | break; |
1756 | case 2: /* spice 0.6 -- qxl-2 */ | |
a19cbfb3 | 1757 | pci_device_rev = QXL_REVISION_STABLE_V06; |
3f6297b9 | 1758 | io_size = 16; |
a19cbfb3 | 1759 | break; |
9197a7c8 | 1760 | case 3: /* qxl-3 */ |
9197a7c8 GH |
1761 | default: |
1762 | pci_device_rev = QXL_DEFAULT_REVISION; | |
3f6297b9 | 1763 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); |
9197a7c8 | 1764 | break; |
a19cbfb3 GH |
1765 | } |
1766 | ||
a19cbfb3 GH |
1767 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1768 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1769 | ||
1770 | qxl->rom_size = qxl_rom_size(); | |
c5705a77 AK |
1771 | memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size); |
1772 | vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); | |
a19cbfb3 GH |
1773 | init_qxl_rom(qxl); |
1774 | init_qxl_ram(qxl); | |
1775 | ||
c5705a77 AK |
1776 | memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size); |
1777 | vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); | |
6f2b175a GH |
1778 | memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar, |
1779 | 0, qxl->vram32_size); | |
a19cbfb3 | 1780 | |
b1950430 AK |
1781 | memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl, |
1782 | "qxl-ioports", io_size); | |
1783 | if (qxl->id == 0) { | |
1784 | vga_dirty_log_start(&qxl->vga); | |
1785 | } | |
1786 | ||
1787 | ||
e824b2cc AK |
1788 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, |
1789 | PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar); | |
a19cbfb3 | 1790 | |
e824b2cc AK |
1791 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, |
1792 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar); | |
a19cbfb3 | 1793 | |
e824b2cc AK |
1794 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, |
1795 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram); | |
a19cbfb3 | 1796 | |
e824b2cc | 1797 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, |
6f2b175a GH |
1798 | PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar); |
1799 | ||
1800 | if (qxl->vram32_size < qxl->vram_size) { | |
1801 | /* | |
1802 | * Make the 64bit vram bar show up only in case it is | |
1803 | * configured to be larger than the 32bit vram bar. | |
1804 | */ | |
1805 | pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX, | |
1806 | PCI_BASE_ADDRESS_SPACE_MEMORY | | |
1807 | PCI_BASE_ADDRESS_MEM_TYPE_64 | | |
1808 | PCI_BASE_ADDRESS_MEM_PREFETCH, | |
1809 | &qxl->vram_bar); | |
1810 | } | |
1811 | ||
1812 | /* print pci bar details */ | |
1813 | dprint(qxl, 1, "ram/%s: %d MB [region 0]\n", | |
1814 | qxl->id == 0 ? "pri" : "sec", | |
1815 | qxl->vga.vram_size / (1024*1024)); | |
1816 | dprint(qxl, 1, "vram/32: %d MB [region 1]\n", | |
1817 | qxl->vram32_size / (1024*1024)); | |
1818 | dprint(qxl, 1, "vram/64: %d MB %s\n", | |
1819 | qxl->vram_size / (1024*1024), | |
1820 | qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]"); | |
a19cbfb3 GH |
1821 | |
1822 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
1823 | qxl->ssd.qxl.id = qxl->id; | |
1824 | qemu_spice_add_interface(&qxl->ssd.qxl.base); | |
1825 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); | |
1826 | ||
1827 | init_pipe_signaling(qxl); | |
1828 | qxl_reset_state(qxl); | |
1829 | ||
81fb6f15 AL |
1830 | qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl); |
1831 | ||
a19cbfb3 GH |
1832 | return 0; |
1833 | } | |
1834 | ||
1835 | static int qxl_init_primary(PCIDevice *dev) | |
1836 | { | |
1837 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
1838 | VGACommonState *vga = &qxl->vga; | |
f67ab77a | 1839 | PortioList *qxl_vga_port_list = g_new(PortioList, 1); |
a19cbfb3 GH |
1840 | |
1841 | qxl->id = 0; | |
a974192c GH |
1842 | qxl_init_ramsize(qxl, 32); |
1843 | vga_common_init(vga, qxl->vga.vram_size); | |
0a039dc7 | 1844 | vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false); |
f67ab77a GH |
1845 | portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga"); |
1846 | portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0); | |
a19cbfb3 GH |
1847 | |
1848 | vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, | |
1849 | qxl_hw_screen_dump, qxl_hw_text_update, qxl); | |
a963f876 | 1850 | qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
a19cbfb3 GH |
1851 | |
1852 | qxl0 = qxl; | |
1853 | register_displaychangelistener(vga->ds, &display_listener); | |
1854 | ||
a19cbfb3 GH |
1855 | return qxl_init_common(qxl); |
1856 | } | |
1857 | ||
1858 | static int qxl_init_secondary(PCIDevice *dev) | |
1859 | { | |
1860 | static int device_id = 1; | |
1861 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
a19cbfb3 GH |
1862 | |
1863 | qxl->id = device_id++; | |
a974192c | 1864 | qxl_init_ramsize(qxl, 16); |
c5705a77 AK |
1865 | memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size); |
1866 | vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); | |
b1950430 | 1867 | qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); |
a19cbfb3 | 1868 | |
a19cbfb3 GH |
1869 | return qxl_init_common(qxl); |
1870 | } | |
1871 | ||
1872 | static void qxl_pre_save(void *opaque) | |
1873 | { | |
1874 | PCIQXLDevice* d = opaque; | |
1875 | uint8_t *ram_start = d->vga.vram_ptr; | |
1876 | ||
c480bb7d | 1877 | trace_qxl_pre_save(d->id); |
a19cbfb3 GH |
1878 | if (d->last_release == NULL) { |
1879 | d->last_release_offset = 0; | |
1880 | } else { | |
1881 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
1882 | } | |
1883 | assert(d->last_release_offset < d->vga.vram_size); | |
1884 | } | |
1885 | ||
1886 | static int qxl_pre_load(void *opaque) | |
1887 | { | |
1888 | PCIQXLDevice* d = opaque; | |
1889 | ||
c480bb7d | 1890 | trace_qxl_pre_load(d->id); |
a19cbfb3 GH |
1891 | qxl_hard_reset(d, 1); |
1892 | qxl_exit_vga_mode(d); | |
a19cbfb3 GH |
1893 | return 0; |
1894 | } | |
1895 | ||
54825d2e AL |
1896 | static void qxl_create_memslots(PCIQXLDevice *d) |
1897 | { | |
1898 | int i; | |
1899 | ||
1900 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
1901 | if (!d->guest_slots[i].active) { | |
1902 | continue; | |
1903 | } | |
54825d2e AL |
1904 | qxl_add_memslot(d, i, 0, QXL_SYNC); |
1905 | } | |
1906 | } | |
1907 | ||
a19cbfb3 GH |
1908 | static int qxl_post_load(void *opaque, int version) |
1909 | { | |
1910 | PCIQXLDevice* d = opaque; | |
1911 | uint8_t *ram_start = d->vga.vram_ptr; | |
1912 | QXLCommandExt *cmds; | |
54825d2e | 1913 | int in, out, newmode; |
a19cbfb3 | 1914 | |
a19cbfb3 GH |
1915 | assert(d->last_release_offset < d->vga.vram_size); |
1916 | if (d->last_release_offset == 0) { | |
1917 | d->last_release = NULL; | |
1918 | } else { | |
1919 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
1920 | } | |
1921 | ||
1922 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
1923 | ||
c480bb7d | 1924 | trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode)); |
a19cbfb3 GH |
1925 | newmode = d->mode; |
1926 | d->mode = QXL_MODE_UNDEFINED; | |
54825d2e | 1927 | |
a19cbfb3 GH |
1928 | switch (newmode) { |
1929 | case QXL_MODE_UNDEFINED: | |
1930 | break; | |
1931 | case QXL_MODE_VGA: | |
54825d2e | 1932 | qxl_create_memslots(d); |
a19cbfb3 GH |
1933 | qxl_enter_vga_mode(d); |
1934 | break; | |
1935 | case QXL_MODE_NATIVE: | |
54825d2e | 1936 | qxl_create_memslots(d); |
5ff4e36c | 1937 | qxl_create_guest_primary(d, 1, QXL_SYNC); |
a19cbfb3 GH |
1938 | |
1939 | /* replay surface-create and cursor-set commands */ | |
7267c094 | 1940 | cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); |
a19cbfb3 GH |
1941 | for (in = 0, out = 0; in < NUM_SURFACES; in++) { |
1942 | if (d->guest_surfaces.cmds[in] == 0) { | |
1943 | continue; | |
1944 | } | |
1945 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
1946 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
1947 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1948 | out++; | |
1949 | } | |
30f6da66 YH |
1950 | if (d->guest_cursor) { |
1951 | cmds[out].cmd.data = d->guest_cursor; | |
1952 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
1953 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1954 | out++; | |
1955 | } | |
aee32bf3 | 1956 | qxl_spice_loadvm_commands(d, cmds, out); |
7267c094 | 1957 | g_free(cmds); |
a19cbfb3 GH |
1958 | |
1959 | break; | |
1960 | case QXL_MODE_COMPAT: | |
54825d2e AL |
1961 | /* note: no need to call qxl_create_memslots, qxl_set_mode |
1962 | * creates the mem slot. */ | |
a19cbfb3 GH |
1963 | qxl_set_mode(d, d->shadow_rom.mode, 1); |
1964 | break; | |
1965 | } | |
a19cbfb3 GH |
1966 | return 0; |
1967 | } | |
1968 | ||
b67737a6 | 1969 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 GH |
1970 | |
1971 | static VMStateDescription qxl_memslot = { | |
1972 | .name = "qxl-memslot", | |
1973 | .version_id = QXL_SAVE_VERSION, | |
1974 | .minimum_version_id = QXL_SAVE_VERSION, | |
1975 | .fields = (VMStateField[]) { | |
1976 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
1977 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
1978 | VMSTATE_UINT32(active, struct guest_slots), | |
1979 | VMSTATE_END_OF_LIST() | |
1980 | } | |
1981 | }; | |
1982 | ||
1983 | static VMStateDescription qxl_surface = { | |
1984 | .name = "qxl-surface", | |
1985 | .version_id = QXL_SAVE_VERSION, | |
1986 | .minimum_version_id = QXL_SAVE_VERSION, | |
1987 | .fields = (VMStateField[]) { | |
1988 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
1989 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
1990 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
1991 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
1992 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
1993 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
1994 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
1995 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
1996 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
1997 | VMSTATE_END_OF_LIST() | |
1998 | } | |
1999 | }; | |
2000 | ||
a19cbfb3 GH |
2001 | static VMStateDescription qxl_vmstate = { |
2002 | .name = "qxl", | |
2003 | .version_id = QXL_SAVE_VERSION, | |
2004 | .minimum_version_id = QXL_SAVE_VERSION, | |
2005 | .pre_save = qxl_pre_save, | |
2006 | .pre_load = qxl_pre_load, | |
2007 | .post_load = qxl_post_load, | |
2008 | .fields = (VMStateField []) { | |
2009 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), | |
2010 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
2011 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
2012 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
2013 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
2014 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
2015 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
2016 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
2017 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
2018 | qxl_memslot, struct guest_slots), | |
2019 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
2020 | qxl_surface, QXLSurfaceCreate), | |
2021 | VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), | |
2022 | VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0, | |
2023 | vmstate_info_uint64, uint64_t), | |
2024 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), | |
a19cbfb3 GH |
2025 | VMSTATE_END_OF_LIST() |
2026 | }, | |
a19cbfb3 GH |
2027 | }; |
2028 | ||
78e60ba5 GH |
2029 | static Property qxl_properties[] = { |
2030 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, | |
2031 | 64 * 1024 * 1024), | |
6f2b175a | 2032 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size, |
78e60ba5 GH |
2033 | 64 * 1024 * 1024), |
2034 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, | |
2035 | QXL_DEFAULT_REVISION), | |
2036 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
2037 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
2038 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
017438ee | 2039 | DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1), |
79ce3567 AL |
2040 | DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1), |
2041 | DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1), | |
78e60ba5 GH |
2042 | DEFINE_PROP_END_OF_LIST(), |
2043 | }; | |
2044 | ||
40021f08 AL |
2045 | static void qxl_primary_class_init(ObjectClass *klass, void *data) |
2046 | { | |
39bffca2 | 2047 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2048 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2049 | ||
2050 | k->no_hotplug = 1; | |
2051 | k->init = qxl_init_primary; | |
2052 | k->romfile = "vgabios-qxl.bin"; | |
2053 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2054 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2055 | k->class_id = PCI_CLASS_DISPLAY_VGA; | |
39bffca2 AL |
2056 | dc->desc = "Spice QXL GPU (primary, vga compatible)"; |
2057 | dc->reset = qxl_reset_handler; | |
2058 | dc->vmsd = &qxl_vmstate; | |
2059 | dc->props = qxl_properties; | |
40021f08 AL |
2060 | } |
2061 | ||
39bffca2 AL |
2062 | static TypeInfo qxl_primary_info = { |
2063 | .name = "qxl-vga", | |
2064 | .parent = TYPE_PCI_DEVICE, | |
2065 | .instance_size = sizeof(PCIQXLDevice), | |
2066 | .class_init = qxl_primary_class_init, | |
a19cbfb3 GH |
2067 | }; |
2068 | ||
40021f08 AL |
2069 | static void qxl_secondary_class_init(ObjectClass *klass, void *data) |
2070 | { | |
39bffca2 | 2071 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2072 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2073 | ||
2074 | k->init = qxl_init_secondary; | |
2075 | k->vendor_id = REDHAT_PCI_VENDOR_ID; | |
2076 | k->device_id = QXL_DEVICE_ID_STABLE; | |
2077 | k->class_id = PCI_CLASS_DISPLAY_OTHER; | |
39bffca2 AL |
2078 | dc->desc = "Spice QXL GPU (secondary)"; |
2079 | dc->reset = qxl_reset_handler; | |
2080 | dc->vmsd = &qxl_vmstate; | |
2081 | dc->props = qxl_properties; | |
40021f08 AL |
2082 | } |
2083 | ||
39bffca2 AL |
2084 | static TypeInfo qxl_secondary_info = { |
2085 | .name = "qxl", | |
2086 | .parent = TYPE_PCI_DEVICE, | |
2087 | .instance_size = sizeof(PCIQXLDevice), | |
2088 | .class_init = qxl_secondary_class_init, | |
a19cbfb3 GH |
2089 | }; |
2090 | ||
83f7d43a | 2091 | static void qxl_register_types(void) |
a19cbfb3 | 2092 | { |
39bffca2 AL |
2093 | type_register_static(&qxl_primary_info); |
2094 | type_register_static(&qxl_secondary_info); | |
a19cbfb3 GH |
2095 | } |
2096 | ||
83f7d43a | 2097 | type_init(qxl_register_types) |