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qxl: introduce QXLCookie
[qemu.git] / hw / qxl.c
CommitLineData
a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a19cbfb3
GH		 21#include "qemu-common.h"
22#include "qemu-timer.h"
23#include "qemu-queue.h"
24#include "monitor.h"
25#include "sysemu.h"
26
27#include "qxl.h"
28
29#undef SPICE_RING_PROD_ITEM
30#define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
36 abort(); \
37 } \
38 ret = &m_item->el; \
39 }
40
41#undef SPICE_RING_CONS_ITEM
42#define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 abort(); \
49 } \
50 ret = &m_item->el; \
51 }
52
53#undef ALIGN
54#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
55
56#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
57
58#define QXL_MODE(_x, _y, _b, _o) \
59 { .x_res = _x, \
60 .y_res = _y, \
61 .bits = _b, \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
65 .orientation = _o, \
66 }
67
68#define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
71
72#define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
77
78static QXLMode qxl_modes[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102#if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
109#endif
110#if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
115#endif
116};
117
118static PCIQXLDevice *qxl0;
119
120static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
5ff4e36c 121static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
a19cbfb3
GH		 122static void qxl_reset_memslots(PCIQXLDevice *d);
123static void qxl_reset_surfaces(PCIQXLDevice *d);
124static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
125
7635392c 126void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
2bce0400 127{
2bce0400 128 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
2bce0400 129 if (qxl->guestdebug) {
7635392c
AL		 130 va_list ap;
131 va_start(ap, msg);
132 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
133 vfprintf(stderr, msg, ap);
134 fprintf(stderr, "\n");
135 va_end(ap);
2bce0400
GH		 136 }
137}
138
aee32bf3
GH		 139
140void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
141 struct QXLRect *area, struct QXLRect *dirty_rects,
142 uint32_t num_dirty_rects,
5ff4e36c 143 uint32_t clear_dirty_region,
2e1a98c9 144 qxl_async_io async, struct QXLCookie *cookie)
aee32bf3 145{
5ff4e36c
AL		 146 if (async == QXL_SYNC) {
147 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
148 dirty_rects, num_dirty_rects, clear_dirty_region);
149 } else {
2e1a98c9 150 assert(cookie != NULL);
5ff4e36c 151 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
2e1a98c9 152 clear_dirty_region, (uint64_t)cookie);
5ff4e36c 153 }
aee32bf3
GH		 154}
155
5ff4e36c
AL		 156static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
157 uint32_t id)
aee32bf3 158{
14898cf6 159 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 160 qxl->guest_surfaces.cmds[id] = 0;
161 qxl->guest_surfaces.count--;
162 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 163}
164
5ff4e36c
AL		 165static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
166 qxl_async_io async)
167{
2e1a98c9
AL		 168 QXLCookie *cookie;
169
5ff4e36c 170 if (async) {
2e1a98c9
AL		 171 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
172 QXL_IO_DESTROY_SURFACE_ASYNC);
173 cookie->u.surface_id = id;
174 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uint64_t)cookie);
5ff4e36c
AL		 175 } else {
176 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
177 qxl_spice_destroy_surface_wait_complete(qxl, id);
178 }
179}
180
3e16b9c5
AL		 181static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
182{
2e1a98c9
AL		 183 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
184 (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
185 QXL_IO_FLUSH_SURFACES_ASYNC));
3e16b9c5 186}
3e16b9c5 187
aee32bf3
GH		 188void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
189 uint32_t count)
190{
191 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
192}
193
194void qxl_spice_oom(PCIQXLDevice *qxl)
195{
196 qxl->ssd.worker->oom(qxl->ssd.worker);
197}
198
199void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
200{
201 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
202}
203
5ff4e36c 204static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
aee32bf3 205{
14898cf6 206 qemu_mutex_lock(&qxl->track_lock);
14898cf6
GH		 207 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
208 qxl->guest_surfaces.count = 0;
209 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 210}
211
5ff4e36c
AL		 212static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
213{
214 if (async) {
2e1a98c9
AL		 215 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
216 (uint64_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
217 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
5ff4e36c
AL		 218 } else {
219 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
220 qxl_spice_destroy_surfaces_complete(qxl);
221 }
222}
223
aee32bf3
GH		 224void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
225{
226 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
227}
228
229void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
230{
231 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
30f6da66
YH		 232 qemu_mutex_lock(&qxl->track_lock);
233 qxl->guest_cursor = 0;
234 qemu_mutex_unlock(&qxl->track_lock);
aee32bf3
GH		 235}
236
237
a19cbfb3
GH		 238static inline uint32_t msb_mask(uint32_t val)
239{
240 uint32_t mask;
241
242 do {
243 mask = ~(val - 1) & val;
244 val &= ~mask;
245 } while (mask < val);
246
247 return mask;
248}
249
250static ram_addr_t qxl_rom_size(void)
251{
252 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
253 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
254 rom_size = msb_mask(rom_size * 2 - 1);
255 return rom_size;
256}
257
258static void init_qxl_rom(PCIQXLDevice *d)
259{
b1950430 260 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
a19cbfb3
GH		 261 QXLModes *modes = (QXLModes *)(rom + 1);
262 uint32_t ram_header_size;
263 uint32_t surface0_area_size;
264 uint32_t num_pages;
265 uint32_t fb, maxfb = 0;
266 int i;
267
268 memset(rom, 0, d->rom_size);
269
270 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
271 rom->id = cpu_to_le32(d->id);
272 rom->log_level = cpu_to_le32(d->guestdebug);
273 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
274
275 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
276 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
277 rom->slots_start = 1;
278 rom->slots_end = NUM_MEMSLOTS - 1;
279 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
280
281 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
282 for (i = 0; i < modes->n_modes; i++) {
283 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
284 if (maxfb < fb) {
285 maxfb = fb;
286 }
287 modes->modes[i].id = cpu_to_le32(i);
288 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
289 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
290 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
291 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
292 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
293 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
294 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
295 }
296 if (maxfb < VGA_RAM_SIZE && d->id == 0)
297 maxfb = VGA_RAM_SIZE;
298
299 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
300 surface0_area_size = ALIGN(maxfb, 4096);
301 num_pages = d->vga.vram_size;
302 num_pages -= ram_header_size;
303 num_pages -= surface0_area_size;
304 num_pages = num_pages / TARGET_PAGE_SIZE;
305
306 rom->draw_area_offset = cpu_to_le32(0);
307 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
308 rom->pages_offset = cpu_to_le32(surface0_area_size);
309 rom->num_pages = cpu_to_le32(num_pages);
310 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
311
312 d->shadow_rom = *rom;
313 d->rom = rom;
314 d->modes = modes;
315}
316
317static void init_qxl_ram(PCIQXLDevice *d)
318{
319 uint8_t *buf;
320 uint64_t *item;
321
322 buf = d->vga.vram_ptr;
323 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
324 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
325 d->ram->int_pending = cpu_to_le32(0);
326 d->ram->int_mask = cpu_to_le32(0);
9f0f352d 327 d->ram->update_surface = 0;
a19cbfb3
GH		 328 SPICE_RING_INIT(&d->ram->cmd_ring);
329 SPICE_RING_INIT(&d->ram->cursor_ring);
330 SPICE_RING_INIT(&d->ram->release_ring);
331 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
332 *item = 0;
333 qxl_ring_set_dirty(d);
334}
335
336/* can be called from spice server thread context */
b1950430 337static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
a19cbfb3 338{
fd4aa979 339 memory_region_set_dirty(mr, addr, end - addr);
a19cbfb3
GH		 340}
341
342static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
343{
b1950430 344 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
a19cbfb3
GH		 345}
346
347/* called from spice server thread context only */
348static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
349{
a19cbfb3
GH		 350 void *base = qxl->vga.vram_ptr;
351 intptr_t offset;
352
353 offset = ptr - base;
354 offset &= ~(TARGET_PAGE_SIZE-1);
355 assert(offset < qxl->vga.vram_size);
b1950430 356 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
a19cbfb3
GH		 357}
358
359/* can be called from spice server thread context */
360static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
361{
b1950430
AK		 362 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
363 ram_addr_t end = qxl->vga.vram_size;
364 qxl_set_dirty(&qxl->vga.vram, addr, end);
a19cbfb3
GH		 365}
366
367/*
368 * keep track of some command state, for savevm/loadvm.
369 * called from spice server thread context only
370 */
371static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
372{
373 switch (le32_to_cpu(ext->cmd.type)) {
374 case QXL_CMD_SURFACE:
375 {
376 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
377 uint32_t id = le32_to_cpu(cmd->surface_id);
378 PANIC_ON(id >= NUM_SURFACES);
14898cf6 379 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3
GH		 380 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
381 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
382 qxl->guest_surfaces.count++;
383 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
384 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
385 }
386 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
387 qxl->guest_surfaces.cmds[id] = 0;
388 qxl->guest_surfaces.count--;
389 }
14898cf6 390 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 391 break;
392 }
393 case QXL_CMD_CURSOR:
394 {
395 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
396 if (cmd->type == QXL_CURSOR_SET) {
30f6da66 397 qemu_mutex_lock(&qxl->track_lock);
a19cbfb3 398 qxl->guest_cursor = ext->cmd.data;
30f6da66 399 qemu_mutex_unlock(&qxl->track_lock);
a19cbfb3
GH		 400 }
401 break;
402 }
403 }
404}
405
406/* spice display interface callbacks */
407
408static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
409{
410 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
411
412 dprint(qxl, 1, "%s:\n", __FUNCTION__);
413 qxl->ssd.worker = qxl_worker;
414}
415
416static void interface_set_compression_level(QXLInstance *sin, int level)
417{
418 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
419
420 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
421 qxl->shadow_rom.compression_level = cpu_to_le32(level);
422 qxl->rom->compression_level = cpu_to_le32(level);
423 qxl_rom_set_dirty(qxl);
424}
425
426static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
427{
428 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
429
430 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
431 qxl->rom->mm_clock = cpu_to_le32(mm_time);
432 qxl_rom_set_dirty(qxl);
433}
434
435static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
436{
437 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
438
439 dprint(qxl, 1, "%s:\n", __FUNCTION__);
440 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
441 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
442 info->num_memslots = NUM_MEMSLOTS;
443 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
444 info->internal_groupslot_id = 0;
445 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
446 info->n_surfaces = NUM_SURFACES;
447}
448
5b77870c
AL		 449static const char *qxl_mode_to_string(int mode)
450{
451 switch (mode) {
452 case QXL_MODE_COMPAT:
453 return "compat";
454 case QXL_MODE_NATIVE:
455 return "native";
456 case QXL_MODE_UNDEFINED:
457 return "undefined";
458 case QXL_MODE_VGA:
459 return "vga";
460 }
461 return "INVALID";
462}
463
8b92e298
AL		 464static const char *io_port_to_string(uint32_t io_port)
465{
466 if (io_port >= QXL_IO_RANGE_SIZE) {
467 return "out of range";
468 }
469 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
470 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
471 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
472 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
473 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
474 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
475 [QXL_IO_RESET] = "QXL_IO_RESET",
476 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
477 [QXL_IO_LOG] = "QXL_IO_LOG",
478 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
479 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
480 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
481 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
482 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
483 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
484 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
485 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
8b92e298
AL		 486 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
487 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
488 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
489 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
490 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
491 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
492 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
493 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
494 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
8b92e298
AL		 495 };
496 return io_port_to_string[io_port];
497}
498
a19cbfb3
GH		 499/* called from spice server thread context only */
500static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
501{
502 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
503 SimpleSpiceUpdate *update;
504 QXLCommandRing *ring;
505 QXLCommand *cmd;
e0c64d08 506 int notify, ret;
a19cbfb3
GH		 507
508 switch (qxl->mode) {
509 case QXL_MODE_VGA:
510 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
e0c64d08
GH		 511 ret = false;
512 qemu_mutex_lock(&qxl->ssd.lock);
513 if (qxl->ssd.update != NULL) {
514 update = qxl->ssd.update;
515 qxl->ssd.update = NULL;
516 *ext = update->ext;
517 ret = true;
a19cbfb3 518 }
e0c64d08 519 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 520 if (ret) {
5b77870c 521 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
212496c9
AL		 522 qxl_log_command(qxl, "vga", ext);
523 }
e0c64d08 524 return ret;
a19cbfb3
GH		 525 case QXL_MODE_COMPAT:
526 case QXL_MODE_NATIVE:
527 case QXL_MODE_UNDEFINED:
5b77870c 528 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 529 ring = &qxl->ram->cmd_ring;
530 if (SPICE_RING_IS_EMPTY(ring)) {
531 return false;
532 }
5b77870c 533 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 534 SPICE_RING_CONS_ITEM(ring, cmd);
535 ext->cmd = *cmd;
536 ext->group_id = MEMSLOT_GROUP_GUEST;
537 ext->flags = qxl->cmdflags;
538 SPICE_RING_POP(ring, notify);
539 qxl_ring_set_dirty(qxl);
540 if (notify) {
541 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
542 }
543 qxl->guest_primary.commands++;
544 qxl_track_command(qxl, ext);
545 qxl_log_command(qxl, "cmd", ext);
546 return true;
547 default:
548 return false;
549 }
550}
551
552/* called from spice server thread context only */
553static int interface_req_cmd_notification(QXLInstance *sin)
554{
555 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
556 int wait = 1;
557
558 switch (qxl->mode) {
559 case QXL_MODE_COMPAT:
560 case QXL_MODE_NATIVE:
561 case QXL_MODE_UNDEFINED:
562 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
563 qxl_ring_set_dirty(qxl);
564 break;
565 default:
566 /* nothing */
567 break;
568 }
569 return wait;
570}
571
572/* called from spice server thread context only */
573static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
574{
575 QXLReleaseRing *ring = &d->ram->release_ring;
576 uint64_t *item;
577 int notify;
578
579#define QXL_FREE_BUNCH_SIZE 32
580
581 if (ring->prod - ring->cons + 1 == ring->num_items) {
582 /* ring full -- can't push */
583 return;
584 }
585 if (!flush && d->oom_running) {
586 /* collect everything from oom handler before pushing */
587 return;
588 }
589 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
590 /* collect a bit more before pushing */
591 return;
592 }
593
594 SPICE_RING_PUSH(ring, notify);
595 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
596 d->num_free_res, notify ? "yes" : "no",
597 ring->prod - ring->cons, ring->num_items,
598 ring->prod, ring->cons);
599 if (notify) {
600 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
601 }
602 SPICE_RING_PROD_ITEM(ring, item);
603 *item = 0;
604 d->num_free_res = 0;
605 d->last_release = NULL;
606 qxl_ring_set_dirty(d);
607}
608
609/* called from spice server thread context only */
610static void interface_release_resource(QXLInstance *sin,
611 struct QXLReleaseInfoExt ext)
612{
613 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
614 QXLReleaseRing *ring;
615 uint64_t *item, id;
616
617 if (ext.group_id == MEMSLOT_GROUP_HOST) {
618 /* host group -> vga mode update request */
f4a8a424 619 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
a19cbfb3
GH		 620 return;
621 }
622
623 /*
624 * ext->info points into guest-visible memory
625 * pci bar 0, $command.release_info
626 */
627 ring = &qxl->ram->release_ring;
628 SPICE_RING_PROD_ITEM(ring, item);
629 if (*item == 0) {
630 /* stick head into the ring */
631 id = ext.info->id;
632 ext.info->next = 0;
633 qxl_ram_set_dirty(qxl, &ext.info->next);
634 *item = id;
635 qxl_ring_set_dirty(qxl);
636 } else {
637 /* append item to the list */
638 qxl->last_release->next = ext.info->id;
639 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
640 ext.info->next = 0;
641 qxl_ram_set_dirty(qxl, &ext.info->next);
642 }
643 qxl->last_release = ext.info;
644 qxl->num_free_res++;
645 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
646 qxl_push_free_res(qxl, 0);
647}
648
649/* called from spice server thread context only */
650static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
651{
652 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
653 QXLCursorRing *ring;
654 QXLCommand *cmd;
655 int notify;
656
657 switch (qxl->mode) {
658 case QXL_MODE_COMPAT:
659 case QXL_MODE_NATIVE:
660 case QXL_MODE_UNDEFINED:
661 ring = &qxl->ram->cursor_ring;
662 if (SPICE_RING_IS_EMPTY(ring)) {
663 return false;
664 }
665 SPICE_RING_CONS_ITEM(ring, cmd);
666 ext->cmd = *cmd;
667 ext->group_id = MEMSLOT_GROUP_GUEST;
668 ext->flags = qxl->cmdflags;
669 SPICE_RING_POP(ring, notify);
670 qxl_ring_set_dirty(qxl);
671 if (notify) {
672 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
673 }
674 qxl->guest_primary.commands++;
675 qxl_track_command(qxl, ext);
676 qxl_log_command(qxl, "csr", ext);
677 if (qxl->id == 0) {
678 qxl_render_cursor(qxl, ext);
679 }
680 return true;
681 default:
682 return false;
683 }
684}
685
686/* called from spice server thread context only */
687static int interface_req_cursor_notification(QXLInstance *sin)
688{
689 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
690 int wait = 1;
691
692 switch (qxl->mode) {
693 case QXL_MODE_COMPAT:
694 case QXL_MODE_NATIVE:
695 case QXL_MODE_UNDEFINED:
696 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
697 qxl_ring_set_dirty(qxl);
698 break;
699 default:
700 /* nothing */
701 break;
702 }
703 return wait;
704}
705
706/* called from spice server thread context */
707static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
708{
709 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
710 abort();
711}
712
713/* called from spice server thread context only */
714static int interface_flush_resources(QXLInstance *sin)
715{
716 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
717 int ret;
718
719 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
720 ret = qxl->num_free_res;
721 if (ret) {
722 qxl_push_free_res(qxl, 1);
723 }
724 return ret;
725}
726
5ff4e36c
AL		 727static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
728
5ff4e36c 729/* called from spice server thread context only */
2e1a98c9 730static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
5ff4e36c 731{
5ff4e36c
AL		 732 uint32_t current_async;
733
734 qemu_mutex_lock(&qxl->async_lock);
735 current_async = qxl->current_async;
736 qxl->current_async = QXL_UNDEFINED_IO;
737 qemu_mutex_unlock(&qxl->async_lock);
738
2e1a98c9
AL		 739 dprint(qxl, 2, "async_complete: %d (%p) done\n", current_async, cookie);
740 if (!cookie) {
741 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
742 return;
743 }
744 if (cookie && current_async != cookie->io) {
745 fprintf(stderr,
746 "qxl: %s: error: current_async = %d != %ld = cookie->io\n",
747 __func__, current_async, cookie->io);
748 }
5ff4e36c
AL		 749 switch (current_async) {
750 case QXL_IO_CREATE_PRIMARY_ASYNC:
751 qxl_create_guest_primary_complete(qxl);
752 break;
753 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
754 qxl_spice_destroy_surfaces_complete(qxl);
755 break;
756 case QXL_IO_DESTROY_SURFACE_ASYNC:
2e1a98c9 757 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
5ff4e36c
AL		 758 break;
759 }
760 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
761}
762
2e1a98c9
AL		 763/* called from spice server thread context only */
764static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
765{
766 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
767 QXLCookie *cookie = (QXLCookie *)cookie_token;
768
769 switch (cookie->type) {
770 case QXL_COOKIE_TYPE_IO:
771 interface_async_complete_io(qxl, cookie);
772 break;
773 default:
774 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
775 __func__, cookie->type);
776 }
777 g_free(cookie);
778}
779
a19cbfb3
GH		 780static const QXLInterface qxl_interface = {
781 .base.type = SPICE_INTERFACE_QXL,
782 .base.description = "qxl gpu",
783 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
784 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
785
786 .attache_worker = interface_attach_worker,
787 .set_compression_level = interface_set_compression_level,
788 .set_mm_time = interface_set_mm_time,
789 .get_init_info = interface_get_init_info,
790
791 /* the callbacks below are called from spice server thread context */
792 .get_command = interface_get_command,
793 .req_cmd_notification = interface_req_cmd_notification,
794 .release_resource = interface_release_resource,
795 .get_cursor_command = interface_get_cursor_command,
796 .req_cursor_notification = interface_req_cursor_notification,
797 .notify_update = interface_notify_update,
798 .flush_resources = interface_flush_resources,
5ff4e36c 799 .async_complete = interface_async_complete,
a19cbfb3
GH		 800};
801
802static void qxl_enter_vga_mode(PCIQXLDevice *d)
803{
804 if (d->mode == QXL_MODE_VGA) {
805 return;
806 }
807 dprint(d, 1, "%s\n", __FUNCTION__);
808 qemu_spice_create_host_primary(&d->ssd);
809 d->mode = QXL_MODE_VGA;
810 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
811}
812
813static void qxl_exit_vga_mode(PCIQXLDevice *d)
814{
815 if (d->mode != QXL_MODE_VGA) {
816 return;
817 }
818 dprint(d, 1, "%s\n", __FUNCTION__);
5ff4e36c 819 qxl_destroy_primary(d, QXL_SYNC);
a19cbfb3
GH		 820}
821
40010aea 822static void qxl_update_irq(PCIQXLDevice *d)
a19cbfb3
GH		 823{
824 uint32_t pending = le32_to_cpu(d->ram->int_pending);
825 uint32_t mask = le32_to_cpu(d->ram->int_mask);
826 int level = !!(pending & mask);
827 qemu_set_irq(d->pci.irq[0], level);
828 qxl_ring_set_dirty(d);
829}
830
a19cbfb3
GH		 831static void qxl_check_state(PCIQXLDevice *d)
832{
833 QXLRam *ram = d->ram;
834
be48e995
YH		 835 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
836 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 837}
838
839static void qxl_reset_state(PCIQXLDevice *d)
840{
a19cbfb3
GH		 841 QXLRom *rom = d->rom;
842
be48e995 843 qxl_check_state(d);
a19cbfb3
GH		 844 d->shadow_rom.update_id = cpu_to_le32(0);
845 *rom = d->shadow_rom;
846 qxl_rom_set_dirty(d);
847 init_qxl_ram(d);
848 d->num_free_res = 0;
849 d->last_release = NULL;
850 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
851}
852
853static void qxl_soft_reset(PCIQXLDevice *d)
854{
855 dprint(d, 1, "%s:\n", __FUNCTION__);
856 qxl_check_state(d);
857
858 if (d->id == 0) {
859 qxl_enter_vga_mode(d);
860 } else {
861 d->mode = QXL_MODE_UNDEFINED;
862 }
863}
864
865static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
866{
867 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
868 loadvm ? " (loadvm)" : "");
869
aee32bf3
GH		 870 qxl_spice_reset_cursor(d);
871 qxl_spice_reset_image_cache(d);
a19cbfb3
GH		 872 qxl_reset_surfaces(d);
873 qxl_reset_memslots(d);
874
875 /* pre loadvm reset must not touch QXLRam. This lives in
876 * device memory, is migrated together with RAM and thus
877 * already loaded at this point */
878 if (!loadvm) {
879 qxl_reset_state(d);
880 }
881 qemu_spice_create_host_memslot(&d->ssd);
882 qxl_soft_reset(d);
883
884 dprint(d, 1, "%s: done\n", __FUNCTION__);
885}
886
887static void qxl_reset_handler(DeviceState *dev)
888{
889 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
890 qxl_hard_reset(d, 0);
891}
892
893static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
894{
895 VGACommonState *vga = opaque;
896 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
897
898 if (qxl->mode != QXL_MODE_VGA) {
899 dprint(qxl, 1, "%s\n", __FUNCTION__);
5ff4e36c 900 qxl_destroy_primary(qxl, QXL_SYNC);
a19cbfb3
GH		 901 qxl_soft_reset(qxl);
902 }
903 vga_ioport_write(opaque, addr, val);
904}
905
f67ab77a
GH		 906static const MemoryRegionPortio qxl_vga_portio_list[] = {
907 { 0x04, 2, 1, .read = vga_ioport_read,
908 .write = qxl_vga_ioport_write }, /* 3b4 */
909 { 0x0a, 1, 1, .read = vga_ioport_read,
910 .write = qxl_vga_ioport_write }, /* 3ba */
911 { 0x10, 16, 1, .read = vga_ioport_read,
912 .write = qxl_vga_ioport_write }, /* 3c0 */
913 { 0x24, 2, 1, .read = vga_ioport_read,
914 .write = qxl_vga_ioport_write }, /* 3d4 */
915 { 0x2a, 1, 1, .read = vga_ioport_read,
916 .write = qxl_vga_ioport_write }, /* 3da */
917 PORTIO_END_OF_LIST(),
918};
919
5ff4e36c
AL		 920static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
921 qxl_async_io async)
a19cbfb3
GH		 922{
923 static const int regions[] = {
924 QXL_RAM_RANGE_INDEX,
925 QXL_VRAM_RANGE_INDEX,
926 };
927 uint64_t guest_start;
928 uint64_t guest_end;
929 int pci_region;
930 pcibus_t pci_start;
931 pcibus_t pci_end;
932 intptr_t virt_start;
933 QXLDevMemSlot memslot;
934 int i;
935
936 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
937 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
938
939 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
940 __FUNCTION__, slot_id,
941 guest_start, guest_end);
942
943 PANIC_ON(slot_id >= NUM_MEMSLOTS);
944 PANIC_ON(guest_start > guest_end);
945
946 for (i = 0; i < ARRAY_SIZE(regions); i++) {
947 pci_region = regions[i];
948 pci_start = d->pci.io_regions[pci_region].addr;
949 pci_end = pci_start + d->pci.io_regions[pci_region].size;
950 /* mapped? */
951 if (pci_start == -1) {
952 continue;
953 }
954 /* start address in range ? */
955 if (guest_start < pci_start || guest_start > pci_end) {
956 continue;
957 }
958 /* end address in range ? */
959 if (guest_end > pci_end) {
960 continue;
961 }
962 /* passed */
963 break;
964 }
965 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
966
967 switch (pci_region) {
968 case QXL_RAM_RANGE_INDEX:
b1950430 969 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
a19cbfb3
GH		 970 break;
971 case QXL_VRAM_RANGE_INDEX:
b1950430 972 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
a19cbfb3
GH		 973 break;
974 default:
975 /* should not happen */
976 abort();
977 }
978
979 memslot.slot_id = slot_id;
980 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
981 memslot.virt_start = virt_start + (guest_start - pci_start);
982 memslot.virt_end = virt_start + (guest_end - pci_start);
983 memslot.addr_delta = memslot.virt_start - delta;
984 memslot.generation = d->rom->slot_generation = 0;
985 qxl_rom_set_dirty(d);
986
a680f7e7 987 dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
a19cbfb3
GH		 988 __FUNCTION__, memslot.slot_id,
989 memslot.virt_start, memslot.virt_end);
990
5ff4e36c 991 qemu_spice_add_memslot(&d->ssd, &memslot, async);
a19cbfb3
GH		 992 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
993 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
994 d->guest_slots[slot_id].delta = delta;
995 d->guest_slots[slot_id].active = 1;
996}
997
998static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
999{
1000 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
5c59d118 1001 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 1002 d->guest_slots[slot_id].active = 0;
1003}
1004
1005static void qxl_reset_memslots(PCIQXLDevice *d)
1006{
1007 dprint(d, 1, "%s:\n", __FUNCTION__);
aee32bf3 1008 qxl_spice_reset_memslots(d);
a19cbfb3
GH		 1009 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1010}
1011
1012static void qxl_reset_surfaces(PCIQXLDevice *d)
1013{
1014 dprint(d, 1, "%s:\n", __FUNCTION__);
1015 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1016 qxl_spice_destroy_surfaces(d, QXL_SYNC);
a19cbfb3
GH		 1017}
1018
e25139b3 1019/* can be also called from spice server thread context */
a19cbfb3
GH		 1020void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1021{
1022 uint64_t phys = le64_to_cpu(pqxl);
1023 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1024 uint64_t offset = phys & 0xffffffffffff;
1025
1026 switch (group_id) {
1027 case MEMSLOT_GROUP_HOST:
f4a8a424 1028 return (void *)(intptr_t)offset;
a19cbfb3 1029 case MEMSLOT_GROUP_GUEST:
6b7332eb 1030 PANIC_ON(slot >= NUM_MEMSLOTS);
a19cbfb3
GH		 1031 PANIC_ON(!qxl->guest_slots[slot].active);
1032 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1033 offset -= qxl->guest_slots[slot].delta;
1034 PANIC_ON(offset > qxl->guest_slots[slot].size)
1035 return qxl->guest_slots[slot].ptr + offset;
1036 default:
1037 PANIC_ON(1);
1038 }
1039}
1040
5ff4e36c
AL		 1041static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1042{
1043 /* for local rendering */
1044 qxl_render_resize(qxl);
1045}
1046
1047static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1048 qxl_async_io async)
a19cbfb3
GH		 1049{
1050 QXLDevSurfaceCreate surface;
1051 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1052
1053 assert(qxl->mode != QXL_MODE_NATIVE);
1054 qxl_exit_vga_mode(qxl);
1055
1056 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1057 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1058
1059 surface.format = le32_to_cpu(sc->format);
1060 surface.height = le32_to_cpu(sc->height);
1061 surface.mem = le64_to_cpu(sc->mem);
1062 surface.position = le32_to_cpu(sc->position);
1063 surface.stride = le32_to_cpu(sc->stride);
1064 surface.width = le32_to_cpu(sc->width);
1065 surface.type = le32_to_cpu(sc->type);
1066 surface.flags = le32_to_cpu(sc->flags);
1067
1068 surface.mouse_mode = true;
1069 surface.group_id = MEMSLOT_GROUP_GUEST;
1070 if (loadvm) {
1071 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1072 }
1073
1074 qxl->mode = QXL_MODE_NATIVE;
1075 qxl->cmdflags = 0;
5ff4e36c 1076 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
a19cbfb3 1077
5ff4e36c
AL		 1078 if (async == QXL_SYNC) {
1079 qxl_create_guest_primary_complete(qxl);
1080 }
a19cbfb3
GH		 1081}
1082
5ff4e36c
AL		 1083/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1084 * done (in QXL_SYNC case), 0 otherwise. */
1085static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
a19cbfb3
GH		 1086{
1087 if (d->mode == QXL_MODE_UNDEFINED) {
5ff4e36c 1088 return 0;
a19cbfb3 1089 }
a19cbfb3 1090 dprint(d, 1, "%s\n", __FUNCTION__);
a19cbfb3 1091 d->mode = QXL_MODE_UNDEFINED;
5ff4e36c 1092 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
30f6da66 1093 qxl_spice_reset_cursor(d);
5ff4e36c 1094 return 1;
a19cbfb3
GH		 1095}
1096
1097static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1098{
1099 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1100 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1101 QXLMode *mode = d->modes->modes + modenr;
1102 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1103 QXLMemSlot slot = {
1104 .mem_start = start,
1105 .mem_end = end
1106 };
1107 QXLSurfaceCreate surface = {
1108 .width = mode->x_res,
1109 .height = mode->y_res,
1110 .stride = -mode->x_res * 4,
1111 .format = SPICE_SURFACE_FMT_32_xRGB,
1112 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1113 .mouse_mode = true,
1114 .mem = devmem + d->shadow_rom.draw_area_offset,
1115 };
1116
a680f7e7
PM		 1117 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n",
1118 __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem);
a19cbfb3
GH		 1119 if (!loadvm) {
1120 qxl_hard_reset(d, 0);
1121 }
1122
1123 d->guest_slots[0].slot = slot;
5ff4e36c 1124 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
a19cbfb3
GH		 1125
1126 d->guest_primary.surface = surface;
5ff4e36c 1127 qxl_create_guest_primary(d, 0, QXL_SYNC);
a19cbfb3
GH		 1128
1129 d->mode = QXL_MODE_COMPAT;
1130 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1131#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1132 if (mode->bits == 16) {
1133 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1134 }
1135#endif
1136 d->shadow_rom.mode = cpu_to_le32(modenr);
1137 d->rom->mode = cpu_to_le32(modenr);
1138 qxl_rom_set_dirty(d);
1139}
1140
b1950430
AK		 1141static void ioport_write(void *opaque, target_phys_addr_t addr,
1142 uint64_t val, unsigned size)
a19cbfb3
GH		 1143{
1144 PCIQXLDevice *d = opaque;
b1950430 1145 uint32_t io_port = addr;
5ff4e36c 1146 qxl_async_io async = QXL_SYNC;
5ff4e36c 1147 uint32_t orig_io_port = io_port;
a19cbfb3
GH		 1148
1149 switch (io_port) {
1150 case QXL_IO_RESET:
1151 case QXL_IO_SET_MODE:
1152 case QXL_IO_MEMSLOT_ADD:
1153 case QXL_IO_MEMSLOT_DEL:
1154 case QXL_IO_CREATE_PRIMARY:
81144d1a 1155 case QXL_IO_UPDATE_IRQ:
a3d14054 1156 case QXL_IO_LOG:
5ff4e36c
AL		 1157 case QXL_IO_MEMSLOT_ADD_ASYNC:
1158 case QXL_IO_CREATE_PRIMARY_ASYNC:
a19cbfb3
GH		 1159 break;
1160 default:
e21a298a 1161 if (d->mode != QXL_MODE_VGA) {
a19cbfb3 1162 break;
e21a298a 1163 }
8b92e298
AL		 1164 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1165 __func__, io_port, io_port_to_string(io_port));
5ff4e36c
AL		 1166 /* be nice to buggy guest drivers */
1167 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1168 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1169 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1170 }
a19cbfb3
GH		 1171 return;
1172 }
1173
5ff4e36c
AL		 1174 /* we change the io_port to avoid ifdeffery in the main switch */
1175 orig_io_port = io_port;
1176 switch (io_port) {
1177 case QXL_IO_UPDATE_AREA_ASYNC:
1178 io_port = QXL_IO_UPDATE_AREA;
1179 goto async_common;
1180 case QXL_IO_MEMSLOT_ADD_ASYNC:
1181 io_port = QXL_IO_MEMSLOT_ADD;
1182 goto async_common;
1183 case QXL_IO_CREATE_PRIMARY_ASYNC:
1184 io_port = QXL_IO_CREATE_PRIMARY;
1185 goto async_common;
1186 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1187 io_port = QXL_IO_DESTROY_PRIMARY;
1188 goto async_common;
1189 case QXL_IO_DESTROY_SURFACE_ASYNC:
1190 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1191 goto async_common;
1192 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1193 io_port = QXL_IO_DESTROY_ALL_SURFACES;
3e16b9c5
AL		 1194 goto async_common;
1195 case QXL_IO_FLUSH_SURFACES_ASYNC:
5ff4e36c
AL		 1196async_common:
1197 async = QXL_ASYNC;
1198 qemu_mutex_lock(&d->async_lock);
1199 if (d->current_async != QXL_UNDEFINED_IO) {
1200 qxl_guest_bug(d, "%d async started before last (%d) complete",
1201 io_port, d->current_async);
1202 qemu_mutex_unlock(&d->async_lock);
1203 return;
1204 }
1205 d->current_async = orig_io_port;
1206 qemu_mutex_unlock(&d->async_lock);
c5f3dabb 1207 dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
5ff4e36c
AL		 1208 break;
1209 default:
1210 break;
1211 }
5ff4e36c 1212
a19cbfb3
GH		 1213 switch (io_port) {
1214 case QXL_IO_UPDATE_AREA:
1215 {
1216 QXLRect update = d->ram->update_area;
aee32bf3 1217 qxl_spice_update_area(d, d->ram->update_surface,
2e1a98c9
AL		 1218 &update, NULL, 0, 0, async,
1219 qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1220 QXL_IO_UPDATE_AREA_ASYNC));
a19cbfb3
GH		 1221 break;
1222 }
1223 case QXL_IO_NOTIFY_CMD:
5c59d118 1224 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1225 break;
1226 case QXL_IO_NOTIFY_CURSOR:
5c59d118 1227 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 1228 break;
1229 case QXL_IO_UPDATE_IRQ:
40010aea 1230 qxl_update_irq(d);
a19cbfb3
GH		 1231 break;
1232 case QXL_IO_NOTIFY_OOM:
a19cbfb3
GH		 1233 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1234 break;
1235 }
1236 d->oom_running = 1;
aee32bf3 1237 qxl_spice_oom(d);
a19cbfb3
GH		 1238 d->oom_running = 0;
1239 break;
1240 case QXL_IO_SET_MODE:
b1950430 1241 dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
a19cbfb3
GH		 1242 qxl_set_mode(d, val, 0);
1243 break;
1244 case QXL_IO_LOG:
1245 if (d->guestdebug) {
a680f7e7 1246 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
6ebebb55 1247 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
a19cbfb3
GH		 1248 }
1249 break;
1250 case QXL_IO_RESET:
1251 dprint(d, 1, "QXL_IO_RESET\n");
1252 qxl_hard_reset(d, 0);
1253 break;
1254 case QXL_IO_MEMSLOT_ADD:
2bce0400
GH		 1255 if (val >= NUM_MEMSLOTS) {
1256 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1257 break;
1258 }
1259 if (d->guest_slots[val].active) {
1260 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1261 break;
1262 }
a19cbfb3 1263 d->guest_slots[val].slot = d->ram->mem_slot;
5ff4e36c 1264 qxl_add_memslot(d, val, 0, async);
a19cbfb3
GH		 1265 break;
1266 case QXL_IO_MEMSLOT_DEL:
2bce0400
GH		 1267 if (val >= NUM_MEMSLOTS) {
1268 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1269 break;
1270 }
a19cbfb3
GH		 1271 qxl_del_memslot(d, val);
1272 break;
1273 case QXL_IO_CREATE_PRIMARY:
2bce0400 1274 if (val != 0) {
5ff4e36c
AL		 1275 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1276 async);
1277 goto cancel_async;
2bce0400 1278 }
5ff4e36c 1279 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
a19cbfb3 1280 d->guest_primary.surface = d->ram->create_surface;
5ff4e36c 1281 qxl_create_guest_primary(d, 0, async);
a19cbfb3
GH		 1282 break;
1283 case QXL_IO_DESTROY_PRIMARY:
2bce0400 1284 if (val != 0) {
5ff4e36c
AL		 1285 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1286 async);
1287 goto cancel_async;
1288 }
1289 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1290 qxl_mode_to_string(d->mode));
1291 if (!qxl_destroy_primary(d, async)) {
1292 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1293 qxl_mode_to_string(d->mode));
1294 goto cancel_async;
2bce0400 1295 }
a19cbfb3
GH		 1296 break;
1297 case QXL_IO_DESTROY_SURFACE_WAIT:
5ff4e36c
AL		 1298 if (val >= NUM_SURFACES) {
1299 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1300 "%d >= NUM_SURFACES", async, val);
1301 goto cancel_async;
1302 }
1303 qxl_spice_destroy_surface_wait(d, val, async);
a19cbfb3 1304 break;
3e16b9c5
AL		 1305 case QXL_IO_FLUSH_RELEASE: {
1306 QXLReleaseRing *ring = &d->ram->release_ring;
1307 if (ring->prod - ring->cons + 1 == ring->num_items) {
1308 fprintf(stderr,
1309 "ERROR: no flush, full release ring [p%d,%dc]\n",
1310 ring->prod, ring->cons);
1311 }
1312 qxl_push_free_res(d, 1 /* flush */);
1313 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1314 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1315 d->num_free_res, d->last_release);
1316 break;
1317 }
1318 case QXL_IO_FLUSH_SURFACES_ASYNC:
c5f3dabb
AL		 1319 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1320 " (%"PRId64") (%s, s#=%d, res#=%d)\n",
3e16b9c5
AL		 1321 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1322 d->num_free_res);
1323 qxl_spice_flush_surfaces_async(d);
1324 break;
a19cbfb3 1325 case QXL_IO_DESTROY_ALL_SURFACES:
5ff4e36c
AL		 1326 d->mode = QXL_MODE_UNDEFINED;
1327 qxl_spice_destroy_surfaces(d, async);
a19cbfb3
GH		 1328 break;
1329 default:
1330 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1331 abort();
1332 }
5ff4e36c
AL		 1333 return;
1334cancel_async:
5ff4e36c
AL		 1335 if (async) {
1336 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1337 qemu_mutex_lock(&d->async_lock);
1338 d->current_async = QXL_UNDEFINED_IO;
1339 qemu_mutex_unlock(&d->async_lock);
1340 }
a19cbfb3
GH		 1341}
1342
b1950430
AK		 1343static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1344 unsigned size)
a19cbfb3
GH		 1345{
1346 PCIQXLDevice *d = opaque;
1347
1348 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1349 return 0xff;
1350}
1351
b1950430
AK		 1352static const MemoryRegionOps qxl_io_ops = {
1353 .read = ioport_read,
1354 .write = ioport_write,
1355 .valid = {
1356 .min_access_size = 1,
1357 .max_access_size = 1,
1358 },
1359};
a19cbfb3
GH		 1360
1361static void pipe_read(void *opaque)
1362{
1363 PCIQXLDevice *d = opaque;
1364 char dummy;
1365 int len;
1366
1367 do {
1368 len = read(d->pipe[0], &dummy, sizeof(dummy));
1369 } while (len == sizeof(dummy));
40010aea 1370 qxl_update_irq(d);
a19cbfb3
GH		 1371}
1372
a19cbfb3
GH		 1373static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1374{
1375 uint32_t old_pending;
1376 uint32_t le_events = cpu_to_le32(events);
1377
1378 assert(d->ssd.running);
1379 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1380 if ((old_pending & le_events) == le_events) {
1381 return;
1382 }
691f5c7b 1383 if (qemu_thread_is_self(&d->main)) {
40010aea 1384 qxl_update_irq(d);
a19cbfb3
GH		 1385 } else {
1386 if (write(d->pipe[1], d, 1) != 1) {
1387 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1388 }
1389 }
1390}
1391
1392static void init_pipe_signaling(PCIQXLDevice *d)
1393{
1394 if (pipe(d->pipe) < 0) {
1395 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1396 return;
1397 }
a19cbfb3 1398 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
a19cbfb3
GH		 1399 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1400 fcntl(d->pipe[0], F_SETOWN, getpid());
1401
691f5c7b 1402 qemu_thread_get_self(&d->main);
a19cbfb3
GH		 1403 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1404}
1405
1406/* graphics console */
1407
1408static void qxl_hw_update(void *opaque)
1409{
1410 PCIQXLDevice *qxl = opaque;
1411 VGACommonState *vga = &qxl->vga;
1412
1413 switch (qxl->mode) {
1414 case QXL_MODE_VGA:
1415 vga->update(vga);
1416 break;
1417 case QXL_MODE_COMPAT:
1418 case QXL_MODE_NATIVE:
1419 qxl_render_update(qxl);
1420 break;
1421 default:
1422 break;
1423 }
1424}
1425
1426static void qxl_hw_invalidate(void *opaque)
1427{
1428 PCIQXLDevice *qxl = opaque;
1429 VGACommonState *vga = &qxl->vga;
1430
1431 vga->invalidate(vga);
1432}
1433
45efb161 1434static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch)
a19cbfb3
GH		 1435{
1436 PCIQXLDevice *qxl = opaque;
1437 VGACommonState *vga = &qxl->vga;
1438
1439 switch (qxl->mode) {
1440 case QXL_MODE_COMPAT:
1441 case QXL_MODE_NATIVE:
1442 qxl_render_update(qxl);
1443 ppm_save(filename, qxl->ssd.ds->surface);
1444 break;
1445 case QXL_MODE_VGA:
45efb161 1446 vga->screen_dump(vga, filename, cswitch);
a19cbfb3
GH		 1447 break;
1448 default:
1449 break;
1450 }
1451}
1452
1453static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1454{
1455 PCIQXLDevice *qxl = opaque;
1456 VGACommonState *vga = &qxl->vga;
1457
1458 if (qxl->mode == QXL_MODE_VGA) {
1459 vga->text_update(vga, chardata);
1460 return;
1461 }
1462}
1463
e25139b3
YH		 1464static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1465{
1466 intptr_t vram_start;
1467 int i;
1468
2aa9e85c 1469 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
e25139b3
YH		 1470 return;
1471 }
1472
1473 /* dirty the primary surface */
1474 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1475 qxl->shadow_rom.surface0_area_size);
1476
1477 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1478
1479 /* dirty the off-screen surfaces */
1480 for (i = 0; i < NUM_SURFACES; i++) {
1481 QXLSurfaceCmd *cmd;
1482 intptr_t surface_offset;
1483 int surface_size;
1484
1485 if (qxl->guest_surfaces.cmds[i] == 0) {
1486 continue;
1487 }
1488
1489 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1490 MEMSLOT_GROUP_GUEST);
1491 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1492 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1493 cmd->u.surface_create.data,
1494 MEMSLOT_GROUP_GUEST);
1495 surface_offset -= vram_start;
1496 surface_size = cmd->u.surface_create.height *
1497 abs(cmd->u.surface_create.stride);
1498 dprint(qxl, 3, "%s: dirty surface %d, offset %d, size %d\n", __func__,
1499 i, (int)surface_offset, surface_size);
1500 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1501 }
1502}
1503
1dfb4dd9
LC		 1504static void qxl_vm_change_state_handler(void *opaque, int running,
1505 RunState state)
a19cbfb3
GH		 1506{
1507 PCIQXLDevice *qxl = opaque;
1dfb4dd9 1508 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
a19cbfb3 1509
efbf2950
YH		 1510 if (running) {
1511 /*
1512 * if qxl_send_events was called from spice server context before
40010aea 1513 * migration ended, qxl_update_irq for these events might not have been
efbf2950
YH		 1514 * called
1515 */
40010aea 1516 qxl_update_irq(qxl);
e25139b3
YH		 1517 } else {
1518 /* make sure surfaces are saved before migration */
1519 qxl_dirty_surfaces(qxl);
a19cbfb3
GH		 1520 }
1521}
1522
1523/* display change listener */
1524
1525static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1526{
1527 if (qxl0->mode == QXL_MODE_VGA) {
1528 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1529 }
1530}
1531
1532static void display_resize(struct DisplayState *ds)
1533{
1534 if (qxl0->mode == QXL_MODE_VGA) {
1535 qemu_spice_display_resize(&qxl0->ssd);
1536 }
1537}
1538
1539static void display_refresh(struct DisplayState *ds)
1540{
1541 if (qxl0->mode == QXL_MODE_VGA) {
1542 qemu_spice_display_refresh(&qxl0->ssd);
bb5a8cd5
AL		 1543 } else {
1544 qemu_mutex_lock(&qxl0->ssd.lock);
1545 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1546 qemu_mutex_unlock(&qxl0->ssd.lock);
a19cbfb3
GH		 1547 }
1548}
1549
1550static DisplayChangeListener display_listener = {
1551 .dpy_update = display_update,
1552 .dpy_resize = display_resize,
1553 .dpy_refresh = display_refresh,
1554};
1555
a974192c
GH		 1556static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb)
1557{
1558 /* vga ram (bar 0) */
017438ee
GH		 1559 if (qxl->ram_size_mb != -1) {
1560 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1561 }
a974192c
GH		 1562 if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) {
1563 qxl->vga.vram_size = ram_min_mb * 1024 * 1024;
1564 }
1565
1566 /* vram (surfaces, bar 1) */
017438ee
GH		 1567 if (qxl->vram_size_mb != -1) {
1568 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1569 }
a974192c
GH		 1570 if (qxl->vram_size < 4096) {
1571 qxl->vram_size = 4096;
1572 }
1573 if (qxl->revision == 1) {
1574 qxl->vram_size = 4096;
1575 }
1576
1577 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1578 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1579}
1580
a19cbfb3
GH		 1581static int qxl_init_common(PCIQXLDevice *qxl)
1582{
1583 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1584 uint32_t pci_device_rev;
1585 uint32_t io_size;
1586
1587 qxl->mode = QXL_MODE_UNDEFINED;
1588 qxl->generation = 1;
1589 qxl->num_memslots = NUM_MEMSLOTS;
1590 qxl->num_surfaces = NUM_SURFACES;
14898cf6 1591 qemu_mutex_init(&qxl->track_lock);
5ff4e36c
AL		 1592 qemu_mutex_init(&qxl->async_lock);
1593 qxl->current_async = QXL_UNDEFINED_IO;
a19cbfb3
GH		 1594
1595 switch (qxl->revision) {
1596 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3
GH		 1597 pci_device_rev = QXL_REVISION_STABLE_V04;
1598 break;
1599 case 2: /* spice 0.6 -- qxl-2 */
a19cbfb3
GH		 1600 pci_device_rev = QXL_REVISION_STABLE_V06;
1601 break;
9197a7c8 1602 case 3: /* qxl-3 */
9197a7c8
GH		 1603 default:
1604 pci_device_rev = QXL_DEFAULT_REVISION;
1605 break;
a19cbfb3
GH		 1606 }
1607
a19cbfb3
GH		 1608 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1609 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1610
1611 qxl->rom_size = qxl_rom_size();
c5705a77
AK		 1612 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1613 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1614 init_qxl_rom(qxl);
1615 init_qxl_ram(qxl);
1616
c5705a77
AK		 1617 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1618 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
a19cbfb3
GH		 1619
1620 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1621 if (qxl->revision == 1) {
1622 io_size = 8;
1623 }
1624
b1950430
AK		 1625 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1626 "qxl-ioports", io_size);
1627 if (qxl->id == 0) {
1628 vga_dirty_log_start(&qxl->vga);
1629 }
1630
1631
e824b2cc
AK		 1632 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1633 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
a19cbfb3 1634
e824b2cc
AK		 1635 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1636 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
a19cbfb3 1637
e824b2cc
AK		 1638 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1639 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
a19cbfb3 1640
e824b2cc
AK		 1641 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1642 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
a19cbfb3
GH		 1643
1644 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1645 qxl->ssd.qxl.id = qxl->id;
1646 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1647 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1648
1649 init_pipe_signaling(qxl);
1650 qxl_reset_state(qxl);
1651
1652 return 0;
1653}
1654
1655static int qxl_init_primary(PCIDevice *dev)
1656{
1657 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1658 VGACommonState *vga = &qxl->vga;
f67ab77a 1659 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
a19cbfb3
GH		 1660
1661 qxl->id = 0;
a974192c
GH		 1662 qxl_init_ramsize(qxl, 32);
1663 vga_common_init(vga, qxl->vga.vram_size);
0a039dc7 1664 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
f67ab77a
GH		 1665 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1666 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
a19cbfb3
GH		 1667
1668 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1669 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
a963f876 1670 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
a19cbfb3
GH		 1671
1672 qxl0 = qxl;
1673 register_displaychangelistener(vga->ds, &display_listener);
1674
a19cbfb3
GH		 1675 return qxl_init_common(qxl);
1676}
1677
1678static int qxl_init_secondary(PCIDevice *dev)
1679{
1680 static int device_id = 1;
1681 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
a19cbfb3
GH		 1682
1683 qxl->id = device_id++;
a974192c 1684 qxl_init_ramsize(qxl, 16);
c5705a77
AK		 1685 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1686 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
b1950430 1687 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
a19cbfb3 1688
a19cbfb3
GH		 1689 return qxl_init_common(qxl);
1690}
1691
1692static void qxl_pre_save(void *opaque)
1693{
1694 PCIQXLDevice* d = opaque;
1695 uint8_t *ram_start = d->vga.vram_ptr;
1696
1697 dprint(d, 1, "%s:\n", __FUNCTION__);
1698 if (d->last_release == NULL) {
1699 d->last_release_offset = 0;
1700 } else {
1701 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1702 }
1703 assert(d->last_release_offset < d->vga.vram_size);
1704}
1705
1706static int qxl_pre_load(void *opaque)
1707{
1708 PCIQXLDevice* d = opaque;
1709
1710 dprint(d, 1, "%s: start\n", __FUNCTION__);
1711 qxl_hard_reset(d, 1);
1712 qxl_exit_vga_mode(d);
1713 dprint(d, 1, "%s: done\n", __FUNCTION__);
1714 return 0;
1715}
1716
54825d2e
AL		 1717static void qxl_create_memslots(PCIQXLDevice *d)
1718{
1719 int i;
1720
1721 for (i = 0; i < NUM_MEMSLOTS; i++) {
1722 if (!d->guest_slots[i].active) {
1723 continue;
1724 }
1725 dprint(d, 1, "%s: restoring guest slot %d\n", __func__, i);
1726 qxl_add_memslot(d, i, 0, QXL_SYNC);
1727 }
1728}
1729
a19cbfb3
GH		 1730static int qxl_post_load(void *opaque, int version)
1731{
1732 PCIQXLDevice* d = opaque;
1733 uint8_t *ram_start = d->vga.vram_ptr;
1734 QXLCommandExt *cmds;
54825d2e 1735 int in, out, newmode;
a19cbfb3
GH		 1736
1737 dprint(d, 1, "%s: start\n", __FUNCTION__);
1738
1739 assert(d->last_release_offset < d->vga.vram_size);
1740 if (d->last_release_offset == 0) {
1741 d->last_release = NULL;
1742 } else {
1743 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1744 }
1745
1746 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1747
5b77870c
AL		 1748 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1749 qxl_mode_to_string(d->mode));
a19cbfb3
GH		 1750 newmode = d->mode;
1751 d->mode = QXL_MODE_UNDEFINED;
54825d2e 1752
a19cbfb3
GH		 1753 switch (newmode) {
1754 case QXL_MODE_UNDEFINED:
1755 break;
1756 case QXL_MODE_VGA:
54825d2e 1757 qxl_create_memslots(d);
a19cbfb3
GH		 1758 qxl_enter_vga_mode(d);
1759 break;
1760 case QXL_MODE_NATIVE:
54825d2e 1761 qxl_create_memslots(d);
5ff4e36c 1762 qxl_create_guest_primary(d, 1, QXL_SYNC);
a19cbfb3
GH		 1763
1764 /* replay surface-create and cursor-set commands */
7267c094 1765 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
a19cbfb3
GH		 1766 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1767 if (d->guest_surfaces.cmds[in] == 0) {
1768 continue;
1769 }
1770 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1771 cmds[out].cmd.type = QXL_CMD_SURFACE;
1772 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1773 out++;
1774 }
30f6da66
YH		 1775 if (d->guest_cursor) {
1776 cmds[out].cmd.data = d->guest_cursor;
1777 cmds[out].cmd.type = QXL_CMD_CURSOR;
1778 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1779 out++;
1780 }
aee32bf3 1781 qxl_spice_loadvm_commands(d, cmds, out);
7267c094 1782 g_free(cmds);
a19cbfb3
GH		 1783
1784 break;
1785 case QXL_MODE_COMPAT:
54825d2e
AL		 1786 /* note: no need to call qxl_create_memslots, qxl_set_mode
1787 * creates the mem slot. */
a19cbfb3
GH		 1788 qxl_set_mode(d, d->shadow_rom.mode, 1);
1789 break;
1790 }
1791 dprint(d, 1, "%s: done\n", __FUNCTION__);
1792
a19cbfb3
GH		 1793 return 0;
1794}
1795
b67737a6 1796#define QXL_SAVE_VERSION 21
a19cbfb3
GH		 1797
1798static VMStateDescription qxl_memslot = {
1799 .name = "qxl-memslot",
1800 .version_id = QXL_SAVE_VERSION,
1801 .minimum_version_id = QXL_SAVE_VERSION,
1802 .fields = (VMStateField[]) {
1803 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1804 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1805 VMSTATE_UINT32(active, struct guest_slots),
1806 VMSTATE_END_OF_LIST()
1807 }
1808};
1809
1810static VMStateDescription qxl_surface = {
1811 .name = "qxl-surface",
1812 .version_id = QXL_SAVE_VERSION,
1813 .minimum_version_id = QXL_SAVE_VERSION,
1814 .fields = (VMStateField[]) {
1815 VMSTATE_UINT32(width, QXLSurfaceCreate),
1816 VMSTATE_UINT32(height, QXLSurfaceCreate),
1817 VMSTATE_INT32(stride, QXLSurfaceCreate),
1818 VMSTATE_UINT32(format, QXLSurfaceCreate),
1819 VMSTATE_UINT32(position, QXLSurfaceCreate),
1820 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1821 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1822 VMSTATE_UINT32(type, QXLSurfaceCreate),
1823 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1824 VMSTATE_END_OF_LIST()
1825 }
1826};
1827
a19cbfb3
GH		 1828static VMStateDescription qxl_vmstate = {
1829 .name = "qxl",
1830 .version_id = QXL_SAVE_VERSION,
1831 .minimum_version_id = QXL_SAVE_VERSION,
1832 .pre_save = qxl_pre_save,
1833 .pre_load = qxl_pre_load,
1834 .post_load = qxl_post_load,
1835 .fields = (VMStateField []) {
1836 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1837 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1838 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1839 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1840 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1841 VMSTATE_UINT32(mode, PCIQXLDevice),
1842 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 1843 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1844 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1845 qxl_memslot, struct guest_slots),
1846 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1847 qxl_surface, QXLSurfaceCreate),
1848 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1849 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1850 vmstate_info_uint64, uint64_t),
1851 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 1852 VMSTATE_END_OF_LIST()
1853 },
a19cbfb3
GH		 1854};
1855
78e60ba5
GH		 1856static Property qxl_properties[] = {
1857 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1858 64 * 1024 * 1024),
1859 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1860 64 * 1024 * 1024),
1861 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1862 QXL_DEFAULT_REVISION),
1863 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1864 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1865 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
017438ee
GH		 1866 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
1867 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram_size_mb, -1),
78e60ba5
GH		 1868 DEFINE_PROP_END_OF_LIST(),
1869};
1870
40021f08
AL		 1871static void qxl_primary_class_init(ObjectClass *klass, void *data)
1872{
39bffca2 1873 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1874 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1875
1876 k->no_hotplug = 1;
1877 k->init = qxl_init_primary;
1878 k->romfile = "vgabios-qxl.bin";
1879 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1880 k->device_id = QXL_DEVICE_ID_STABLE;
1881 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 1882 dc->desc = "Spice QXL GPU (primary, vga compatible)";
1883 dc->reset = qxl_reset_handler;
1884 dc->vmsd = &qxl_vmstate;
1885 dc->props = qxl_properties;
40021f08
AL		 1886}
1887
39bffca2
AL		 1888static TypeInfo qxl_primary_info = {
1889 .name = "qxl-vga",
1890 .parent = TYPE_PCI_DEVICE,
1891 .instance_size = sizeof(PCIQXLDevice),
1892 .class_init = qxl_primary_class_init,
a19cbfb3
GH		 1893};
1894
40021f08
AL		 1895static void qxl_secondary_class_init(ObjectClass *klass, void *data)
1896{
39bffca2 1897 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1898 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1899
1900 k->init = qxl_init_secondary;
1901 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1902 k->device_id = QXL_DEVICE_ID_STABLE;
1903 k->class_id = PCI_CLASS_DISPLAY_OTHER;
39bffca2
AL		 1904 dc->desc = "Spice QXL GPU (secondary)";
1905 dc->reset = qxl_reset_handler;
1906 dc->vmsd = &qxl_vmstate;
1907 dc->props = qxl_properties;
40021f08
AL		 1908}
1909
39bffca2
AL		 1910static TypeInfo qxl_secondary_info = {
1911 .name = "qxl",
1912 .parent = TYPE_PCI_DEVICE,
1913 .instance_size = sizeof(PCIQXLDevice),
1914 .class_init = qxl_secondary_class_init,
a19cbfb3
GH		 1915};
1916
83f7d43a 1917static void qxl_register_types(void)
a19cbfb3 1918{
39bffca2
AL		 1919 type_register_static(&qxl_primary_info);
1920 type_register_static(&qxl_secondary_info);
a19cbfb3
GH		 1921}
1922
83f7d43a 1923type_init(qxl_register_types)
Qemu copy for testing