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a19cbfb3 GH |
1 | /* |
2 | * Copyright (C) 2010 Red Hat, Inc. | |
3 | * | |
4 | * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann | |
5 | * maintained by Gerd Hoffmann <kraxel@redhat.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <pthread.h> | |
22 | ||
23 | #include "qemu-common.h" | |
24 | #include "qemu-timer.h" | |
25 | #include "qemu-queue.h" | |
26 | #include "monitor.h" | |
27 | #include "sysemu.h" | |
28 | ||
29 | #include "qxl.h" | |
30 | ||
31 | #undef SPICE_RING_PROD_ITEM | |
32 | #define SPICE_RING_PROD_ITEM(r, ret) { \ | |
33 | typeof(r) start = r; \ | |
34 | typeof(r) end = r + 1; \ | |
35 | uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \ | |
36 | typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \ | |
37 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
38 | abort(); \ | |
39 | } \ | |
40 | ret = &m_item->el; \ | |
41 | } | |
42 | ||
43 | #undef SPICE_RING_CONS_ITEM | |
44 | #define SPICE_RING_CONS_ITEM(r, ret) { \ | |
45 | typeof(r) start = r; \ | |
46 | typeof(r) end = r + 1; \ | |
47 | uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \ | |
48 | typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \ | |
49 | if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \ | |
50 | abort(); \ | |
51 | } \ | |
52 | ret = &m_item->el; \ | |
53 | } | |
54 | ||
55 | #undef ALIGN | |
56 | #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1)) | |
57 | ||
58 | #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9" | |
59 | ||
60 | #define QXL_MODE(_x, _y, _b, _o) \ | |
61 | { .x_res = _x, \ | |
62 | .y_res = _y, \ | |
63 | .bits = _b, \ | |
64 | .stride = (_x) * (_b) / 8, \ | |
65 | .x_mili = PIXEL_SIZE * (_x), \ | |
66 | .y_mili = PIXEL_SIZE * (_y), \ | |
67 | .orientation = _o, \ | |
68 | } | |
69 | ||
70 | #define QXL_MODE_16_32(x_res, y_res, orientation) \ | |
71 | QXL_MODE(x_res, y_res, 16, orientation), \ | |
72 | QXL_MODE(x_res, y_res, 32, orientation) | |
73 | ||
74 | #define QXL_MODE_EX(x_res, y_res) \ | |
75 | QXL_MODE_16_32(x_res, y_res, 0), \ | |
76 | QXL_MODE_16_32(y_res, x_res, 1), \ | |
77 | QXL_MODE_16_32(x_res, y_res, 2), \ | |
78 | QXL_MODE_16_32(y_res, x_res, 3) | |
79 | ||
80 | static QXLMode qxl_modes[] = { | |
81 | QXL_MODE_EX(640, 480), | |
82 | QXL_MODE_EX(800, 480), | |
83 | QXL_MODE_EX(800, 600), | |
84 | QXL_MODE_EX(832, 624), | |
85 | QXL_MODE_EX(960, 640), | |
86 | QXL_MODE_EX(1024, 600), | |
87 | QXL_MODE_EX(1024, 768), | |
88 | QXL_MODE_EX(1152, 864), | |
89 | QXL_MODE_EX(1152, 870), | |
90 | QXL_MODE_EX(1280, 720), | |
91 | QXL_MODE_EX(1280, 760), | |
92 | QXL_MODE_EX(1280, 768), | |
93 | QXL_MODE_EX(1280, 800), | |
94 | QXL_MODE_EX(1280, 960), | |
95 | QXL_MODE_EX(1280, 1024), | |
96 | QXL_MODE_EX(1360, 768), | |
97 | QXL_MODE_EX(1366, 768), | |
98 | QXL_MODE_EX(1400, 1050), | |
99 | QXL_MODE_EX(1440, 900), | |
100 | QXL_MODE_EX(1600, 900), | |
101 | QXL_MODE_EX(1600, 1200), | |
102 | QXL_MODE_EX(1680, 1050), | |
103 | QXL_MODE_EX(1920, 1080), | |
104 | #if VGA_RAM_SIZE >= (16 * 1024 * 1024) | |
105 | /* these modes need more than 8 MB video memory */ | |
106 | QXL_MODE_EX(1920, 1200), | |
107 | QXL_MODE_EX(1920, 1440), | |
108 | QXL_MODE_EX(2048, 1536), | |
109 | QXL_MODE_EX(2560, 1440), | |
110 | QXL_MODE_EX(2560, 1600), | |
111 | #endif | |
112 | #if VGA_RAM_SIZE >= (32 * 1024 * 1024) | |
113 | /* these modes need more than 16 MB video memory */ | |
114 | QXL_MODE_EX(2560, 2048), | |
115 | QXL_MODE_EX(2800, 2100), | |
116 | QXL_MODE_EX(3200, 2400), | |
117 | #endif | |
118 | }; | |
119 | ||
120 | static PCIQXLDevice *qxl0; | |
121 | ||
122 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events); | |
123 | static void qxl_destroy_primary(PCIQXLDevice *d); | |
124 | static void qxl_reset_memslots(PCIQXLDevice *d); | |
125 | static void qxl_reset_surfaces(PCIQXLDevice *d); | |
126 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl); | |
127 | ||
7635392c | 128 | void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
2bce0400 GH |
129 | { |
130 | #if SPICE_INTERFACE_QXL_MINOR >= 1 | |
131 | qxl_send_events(qxl, QXL_INTERRUPT_ERROR); | |
132 | #endif | |
133 | if (qxl->guestdebug) { | |
7635392c AL |
134 | va_list ap; |
135 | va_start(ap, msg); | |
136 | fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); | |
137 | vfprintf(stderr, msg, ap); | |
138 | fprintf(stderr, "\n"); | |
139 | va_end(ap); | |
2bce0400 GH |
140 | } |
141 | } | |
142 | ||
aee32bf3 GH |
143 | |
144 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, | |
145 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
146 | uint32_t num_dirty_rects, | |
147 | uint32_t clear_dirty_region) | |
148 | { | |
149 | qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area, dirty_rects, | |
150 | num_dirty_rects, clear_dirty_region); | |
151 | } | |
152 | ||
153 | void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id) | |
154 | { | |
14898cf6 GH |
155 | qemu_mutex_lock(&qxl->track_lock); |
156 | PANIC_ON(id >= NUM_SURFACES); | |
aee32bf3 | 157 | qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id); |
14898cf6 GH |
158 | qxl->guest_surfaces.cmds[id] = 0; |
159 | qxl->guest_surfaces.count--; | |
160 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
161 | } |
162 | ||
163 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, | |
164 | uint32_t count) | |
165 | { | |
166 | qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count); | |
167 | } | |
168 | ||
169 | void qxl_spice_oom(PCIQXLDevice *qxl) | |
170 | { | |
171 | qxl->ssd.worker->oom(qxl->ssd.worker); | |
172 | } | |
173 | ||
174 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl) | |
175 | { | |
176 | qxl->ssd.worker->reset_memslots(qxl->ssd.worker); | |
177 | } | |
178 | ||
179 | void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl) | |
180 | { | |
14898cf6 | 181 | qemu_mutex_lock(&qxl->track_lock); |
aee32bf3 | 182 | qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker); |
14898cf6 GH |
183 | memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds)); |
184 | qxl->guest_surfaces.count = 0; | |
185 | qemu_mutex_unlock(&qxl->track_lock); | |
aee32bf3 GH |
186 | } |
187 | ||
188 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl) | |
189 | { | |
190 | qxl->ssd.worker->reset_image_cache(qxl->ssd.worker); | |
191 | } | |
192 | ||
193 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl) | |
194 | { | |
195 | qxl->ssd.worker->reset_cursor(qxl->ssd.worker); | |
196 | } | |
197 | ||
198 | ||
a19cbfb3 GH |
199 | static inline uint32_t msb_mask(uint32_t val) |
200 | { | |
201 | uint32_t mask; | |
202 | ||
203 | do { | |
204 | mask = ~(val - 1) & val; | |
205 | val &= ~mask; | |
206 | } while (mask < val); | |
207 | ||
208 | return mask; | |
209 | } | |
210 | ||
211 | static ram_addr_t qxl_rom_size(void) | |
212 | { | |
213 | uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes); | |
214 | rom_size = MAX(rom_size, TARGET_PAGE_SIZE); | |
215 | rom_size = msb_mask(rom_size * 2 - 1); | |
216 | return rom_size; | |
217 | } | |
218 | ||
219 | static void init_qxl_rom(PCIQXLDevice *d) | |
220 | { | |
221 | QXLRom *rom = qemu_get_ram_ptr(d->rom_offset); | |
222 | QXLModes *modes = (QXLModes *)(rom + 1); | |
223 | uint32_t ram_header_size; | |
224 | uint32_t surface0_area_size; | |
225 | uint32_t num_pages; | |
226 | uint32_t fb, maxfb = 0; | |
227 | int i; | |
228 | ||
229 | memset(rom, 0, d->rom_size); | |
230 | ||
231 | rom->magic = cpu_to_le32(QXL_ROM_MAGIC); | |
232 | rom->id = cpu_to_le32(d->id); | |
233 | rom->log_level = cpu_to_le32(d->guestdebug); | |
234 | rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); | |
235 | ||
236 | rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; | |
237 | rom->slot_id_bits = MEMSLOT_SLOT_BITS; | |
238 | rom->slots_start = 1; | |
239 | rom->slots_end = NUM_MEMSLOTS - 1; | |
240 | rom->n_surfaces = cpu_to_le32(NUM_SURFACES); | |
241 | ||
242 | modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes)); | |
243 | for (i = 0; i < modes->n_modes; i++) { | |
244 | fb = qxl_modes[i].y_res * qxl_modes[i].stride; | |
245 | if (maxfb < fb) { | |
246 | maxfb = fb; | |
247 | } | |
248 | modes->modes[i].id = cpu_to_le32(i); | |
249 | modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res); | |
250 | modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res); | |
251 | modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits); | |
252 | modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride); | |
253 | modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili); | |
254 | modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili); | |
255 | modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation); | |
256 | } | |
257 | if (maxfb < VGA_RAM_SIZE && d->id == 0) | |
258 | maxfb = VGA_RAM_SIZE; | |
259 | ||
260 | ram_header_size = ALIGN(sizeof(QXLRam), 4096); | |
261 | surface0_area_size = ALIGN(maxfb, 4096); | |
262 | num_pages = d->vga.vram_size; | |
263 | num_pages -= ram_header_size; | |
264 | num_pages -= surface0_area_size; | |
265 | num_pages = num_pages / TARGET_PAGE_SIZE; | |
266 | ||
267 | rom->draw_area_offset = cpu_to_le32(0); | |
268 | rom->surface0_area_size = cpu_to_le32(surface0_area_size); | |
269 | rom->pages_offset = cpu_to_le32(surface0_area_size); | |
270 | rom->num_pages = cpu_to_le32(num_pages); | |
271 | rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); | |
272 | ||
273 | d->shadow_rom = *rom; | |
274 | d->rom = rom; | |
275 | d->modes = modes; | |
276 | } | |
277 | ||
278 | static void init_qxl_ram(PCIQXLDevice *d) | |
279 | { | |
280 | uint8_t *buf; | |
281 | uint64_t *item; | |
282 | ||
283 | buf = d->vga.vram_ptr; | |
284 | d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); | |
285 | d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); | |
286 | d->ram->int_pending = cpu_to_le32(0); | |
287 | d->ram->int_mask = cpu_to_le32(0); | |
288 | SPICE_RING_INIT(&d->ram->cmd_ring); | |
289 | SPICE_RING_INIT(&d->ram->cursor_ring); | |
290 | SPICE_RING_INIT(&d->ram->release_ring); | |
291 | SPICE_RING_PROD_ITEM(&d->ram->release_ring, item); | |
292 | *item = 0; | |
293 | qxl_ring_set_dirty(d); | |
294 | } | |
295 | ||
296 | /* can be called from spice server thread context */ | |
297 | static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end) | |
298 | { | |
299 | while (addr < end) { | |
300 | cpu_physical_memory_set_dirty(addr); | |
301 | addr += TARGET_PAGE_SIZE; | |
302 | } | |
303 | } | |
304 | ||
305 | static void qxl_rom_set_dirty(PCIQXLDevice *qxl) | |
306 | { | |
307 | ram_addr_t addr = qxl->rom_offset; | |
308 | qxl_set_dirty(addr, addr + qxl->rom_size); | |
309 | } | |
310 | ||
311 | /* called from spice server thread context only */ | |
312 | static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr) | |
313 | { | |
314 | ram_addr_t addr = qxl->vga.vram_offset; | |
315 | void *base = qxl->vga.vram_ptr; | |
316 | intptr_t offset; | |
317 | ||
318 | offset = ptr - base; | |
319 | offset &= ~(TARGET_PAGE_SIZE-1); | |
320 | assert(offset < qxl->vga.vram_size); | |
321 | qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE); | |
322 | } | |
323 | ||
324 | /* can be called from spice server thread context */ | |
325 | static void qxl_ring_set_dirty(PCIQXLDevice *qxl) | |
326 | { | |
327 | ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset; | |
328 | ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size; | |
329 | qxl_set_dirty(addr, end); | |
330 | } | |
331 | ||
332 | /* | |
333 | * keep track of some command state, for savevm/loadvm. | |
334 | * called from spice server thread context only | |
335 | */ | |
336 | static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) | |
337 | { | |
338 | switch (le32_to_cpu(ext->cmd.type)) { | |
339 | case QXL_CMD_SURFACE: | |
340 | { | |
341 | QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
342 | uint32_t id = le32_to_cpu(cmd->surface_id); | |
343 | PANIC_ON(id >= NUM_SURFACES); | |
14898cf6 | 344 | qemu_mutex_lock(&qxl->track_lock); |
a19cbfb3 GH |
345 | if (cmd->type == QXL_SURFACE_CMD_CREATE) { |
346 | qxl->guest_surfaces.cmds[id] = ext->cmd.data; | |
347 | qxl->guest_surfaces.count++; | |
348 | if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) | |
349 | qxl->guest_surfaces.max = qxl->guest_surfaces.count; | |
350 | } | |
351 | if (cmd->type == QXL_SURFACE_CMD_DESTROY) { | |
352 | qxl->guest_surfaces.cmds[id] = 0; | |
353 | qxl->guest_surfaces.count--; | |
354 | } | |
14898cf6 | 355 | qemu_mutex_unlock(&qxl->track_lock); |
a19cbfb3 GH |
356 | break; |
357 | } | |
358 | case QXL_CMD_CURSOR: | |
359 | { | |
360 | QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id); | |
361 | if (cmd->type == QXL_CURSOR_SET) { | |
362 | qxl->guest_cursor = ext->cmd.data; | |
363 | } | |
364 | break; | |
365 | } | |
366 | } | |
367 | } | |
368 | ||
369 | /* spice display interface callbacks */ | |
370 | ||
371 | static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker) | |
372 | { | |
373 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
374 | ||
375 | dprint(qxl, 1, "%s:\n", __FUNCTION__); | |
376 | qxl->ssd.worker = qxl_worker; | |
377 | } | |
378 | ||
379 | static void interface_set_compression_level(QXLInstance *sin, int level) | |
380 | { | |
381 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
382 | ||
383 | dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level); | |
384 | qxl->shadow_rom.compression_level = cpu_to_le32(level); | |
385 | qxl->rom->compression_level = cpu_to_le32(level); | |
386 | qxl_rom_set_dirty(qxl); | |
387 | } | |
388 | ||
389 | static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time) | |
390 | { | |
391 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
392 | ||
393 | qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time); | |
394 | qxl->rom->mm_clock = cpu_to_le32(mm_time); | |
395 | qxl_rom_set_dirty(qxl); | |
396 | } | |
397 | ||
398 | static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info) | |
399 | { | |
400 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
401 | ||
402 | dprint(qxl, 1, "%s:\n", __FUNCTION__); | |
403 | info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; | |
404 | info->memslot_id_bits = MEMSLOT_SLOT_BITS; | |
405 | info->num_memslots = NUM_MEMSLOTS; | |
406 | info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; | |
407 | info->internal_groupslot_id = 0; | |
408 | info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS; | |
409 | info->n_surfaces = NUM_SURFACES; | |
410 | } | |
411 | ||
5b77870c AL |
412 | static const char *qxl_mode_to_string(int mode) |
413 | { | |
414 | switch (mode) { | |
415 | case QXL_MODE_COMPAT: | |
416 | return "compat"; | |
417 | case QXL_MODE_NATIVE: | |
418 | return "native"; | |
419 | case QXL_MODE_UNDEFINED: | |
420 | return "undefined"; | |
421 | case QXL_MODE_VGA: | |
422 | return "vga"; | |
423 | } | |
424 | return "INVALID"; | |
425 | } | |
426 | ||
8b92e298 AL |
427 | static const char *io_port_to_string(uint32_t io_port) |
428 | { | |
429 | if (io_port >= QXL_IO_RANGE_SIZE) { | |
430 | return "out of range"; | |
431 | } | |
432 | static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = { | |
433 | [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD", | |
434 | [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR", | |
435 | [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA", | |
436 | [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ", | |
437 | [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM", | |
438 | [QXL_IO_RESET] = "QXL_IO_RESET", | |
439 | [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE", | |
440 | [QXL_IO_LOG] = "QXL_IO_LOG", | |
441 | [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD", | |
442 | [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL", | |
443 | [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY", | |
444 | [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY", | |
445 | [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY", | |
446 | [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY", | |
447 | [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT", | |
448 | [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES", | |
449 | #if SPICE_INTERFACE_QXL_MINOR >= 1 | |
450 | [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC", | |
451 | [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC", | |
452 | [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC", | |
453 | [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC", | |
454 | [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC", | |
455 | [QXL_IO_DESTROY_ALL_SURFACES_ASYNC] | |
456 | = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC", | |
457 | [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC", | |
458 | [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE", | |
459 | #endif | |
460 | }; | |
461 | return io_port_to_string[io_port]; | |
462 | } | |
463 | ||
a19cbfb3 GH |
464 | /* called from spice server thread context only */ |
465 | static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
466 | { | |
467 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
468 | SimpleSpiceUpdate *update; | |
469 | QXLCommandRing *ring; | |
470 | QXLCommand *cmd; | |
e0c64d08 | 471 | int notify, ret; |
a19cbfb3 GH |
472 | |
473 | switch (qxl->mode) { | |
474 | case QXL_MODE_VGA: | |
475 | dprint(qxl, 2, "%s: vga\n", __FUNCTION__); | |
e0c64d08 GH |
476 | ret = false; |
477 | qemu_mutex_lock(&qxl->ssd.lock); | |
478 | if (qxl->ssd.update != NULL) { | |
479 | update = qxl->ssd.update; | |
480 | qxl->ssd.update = NULL; | |
481 | *ext = update->ext; | |
482 | ret = true; | |
a19cbfb3 | 483 | } |
e0c64d08 | 484 | qemu_mutex_unlock(&qxl->ssd.lock); |
212496c9 | 485 | if (ret) { |
5b77870c | 486 | dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
212496c9 AL |
487 | qxl_log_command(qxl, "vga", ext); |
488 | } | |
e0c64d08 | 489 | return ret; |
a19cbfb3 GH |
490 | case QXL_MODE_COMPAT: |
491 | case QXL_MODE_NATIVE: | |
492 | case QXL_MODE_UNDEFINED: | |
5b77870c | 493 | dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
494 | ring = &qxl->ram->cmd_ring; |
495 | if (SPICE_RING_IS_EMPTY(ring)) { | |
496 | return false; | |
497 | } | |
5b77870c | 498 | dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode)); |
a19cbfb3 GH |
499 | SPICE_RING_CONS_ITEM(ring, cmd); |
500 | ext->cmd = *cmd; | |
501 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
502 | ext->flags = qxl->cmdflags; | |
503 | SPICE_RING_POP(ring, notify); | |
504 | qxl_ring_set_dirty(qxl); | |
505 | if (notify) { | |
506 | qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY); | |
507 | } | |
508 | qxl->guest_primary.commands++; | |
509 | qxl_track_command(qxl, ext); | |
510 | qxl_log_command(qxl, "cmd", ext); | |
511 | return true; | |
512 | default: | |
513 | return false; | |
514 | } | |
515 | } | |
516 | ||
517 | /* called from spice server thread context only */ | |
518 | static int interface_req_cmd_notification(QXLInstance *sin) | |
519 | { | |
520 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
521 | int wait = 1; | |
522 | ||
523 | switch (qxl->mode) { | |
524 | case QXL_MODE_COMPAT: | |
525 | case QXL_MODE_NATIVE: | |
526 | case QXL_MODE_UNDEFINED: | |
527 | SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); | |
528 | qxl_ring_set_dirty(qxl); | |
529 | break; | |
530 | default: | |
531 | /* nothing */ | |
532 | break; | |
533 | } | |
534 | return wait; | |
535 | } | |
536 | ||
537 | /* called from spice server thread context only */ | |
538 | static inline void qxl_push_free_res(PCIQXLDevice *d, int flush) | |
539 | { | |
540 | QXLReleaseRing *ring = &d->ram->release_ring; | |
541 | uint64_t *item; | |
542 | int notify; | |
543 | ||
544 | #define QXL_FREE_BUNCH_SIZE 32 | |
545 | ||
546 | if (ring->prod - ring->cons + 1 == ring->num_items) { | |
547 | /* ring full -- can't push */ | |
548 | return; | |
549 | } | |
550 | if (!flush && d->oom_running) { | |
551 | /* collect everything from oom handler before pushing */ | |
552 | return; | |
553 | } | |
554 | if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { | |
555 | /* collect a bit more before pushing */ | |
556 | return; | |
557 | } | |
558 | ||
559 | SPICE_RING_PUSH(ring, notify); | |
560 | dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n", | |
561 | d->num_free_res, notify ? "yes" : "no", | |
562 | ring->prod - ring->cons, ring->num_items, | |
563 | ring->prod, ring->cons); | |
564 | if (notify) { | |
565 | qxl_send_events(d, QXL_INTERRUPT_DISPLAY); | |
566 | } | |
567 | SPICE_RING_PROD_ITEM(ring, item); | |
568 | *item = 0; | |
569 | d->num_free_res = 0; | |
570 | d->last_release = NULL; | |
571 | qxl_ring_set_dirty(d); | |
572 | } | |
573 | ||
574 | /* called from spice server thread context only */ | |
575 | static void interface_release_resource(QXLInstance *sin, | |
576 | struct QXLReleaseInfoExt ext) | |
577 | { | |
578 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
579 | QXLReleaseRing *ring; | |
580 | uint64_t *item, id; | |
581 | ||
582 | if (ext.group_id == MEMSLOT_GROUP_HOST) { | |
583 | /* host group -> vga mode update request */ | |
584 | qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id); | |
585 | return; | |
586 | } | |
587 | ||
588 | /* | |
589 | * ext->info points into guest-visible memory | |
590 | * pci bar 0, $command.release_info | |
591 | */ | |
592 | ring = &qxl->ram->release_ring; | |
593 | SPICE_RING_PROD_ITEM(ring, item); | |
594 | if (*item == 0) { | |
595 | /* stick head into the ring */ | |
596 | id = ext.info->id; | |
597 | ext.info->next = 0; | |
598 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
599 | *item = id; | |
600 | qxl_ring_set_dirty(qxl); | |
601 | } else { | |
602 | /* append item to the list */ | |
603 | qxl->last_release->next = ext.info->id; | |
604 | qxl_ram_set_dirty(qxl, &qxl->last_release->next); | |
605 | ext.info->next = 0; | |
606 | qxl_ram_set_dirty(qxl, &ext.info->next); | |
607 | } | |
608 | qxl->last_release = ext.info; | |
609 | qxl->num_free_res++; | |
610 | dprint(qxl, 3, "%4d\r", qxl->num_free_res); | |
611 | qxl_push_free_res(qxl, 0); | |
612 | } | |
613 | ||
614 | /* called from spice server thread context only */ | |
615 | static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) | |
616 | { | |
617 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
618 | QXLCursorRing *ring; | |
619 | QXLCommand *cmd; | |
620 | int notify; | |
621 | ||
622 | switch (qxl->mode) { | |
623 | case QXL_MODE_COMPAT: | |
624 | case QXL_MODE_NATIVE: | |
625 | case QXL_MODE_UNDEFINED: | |
626 | ring = &qxl->ram->cursor_ring; | |
627 | if (SPICE_RING_IS_EMPTY(ring)) { | |
628 | return false; | |
629 | } | |
630 | SPICE_RING_CONS_ITEM(ring, cmd); | |
631 | ext->cmd = *cmd; | |
632 | ext->group_id = MEMSLOT_GROUP_GUEST; | |
633 | ext->flags = qxl->cmdflags; | |
634 | SPICE_RING_POP(ring, notify); | |
635 | qxl_ring_set_dirty(qxl); | |
636 | if (notify) { | |
637 | qxl_send_events(qxl, QXL_INTERRUPT_CURSOR); | |
638 | } | |
639 | qxl->guest_primary.commands++; | |
640 | qxl_track_command(qxl, ext); | |
641 | qxl_log_command(qxl, "csr", ext); | |
642 | if (qxl->id == 0) { | |
643 | qxl_render_cursor(qxl, ext); | |
644 | } | |
645 | return true; | |
646 | default: | |
647 | return false; | |
648 | } | |
649 | } | |
650 | ||
651 | /* called from spice server thread context only */ | |
652 | static int interface_req_cursor_notification(QXLInstance *sin) | |
653 | { | |
654 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
655 | int wait = 1; | |
656 | ||
657 | switch (qxl->mode) { | |
658 | case QXL_MODE_COMPAT: | |
659 | case QXL_MODE_NATIVE: | |
660 | case QXL_MODE_UNDEFINED: | |
661 | SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); | |
662 | qxl_ring_set_dirty(qxl); | |
663 | break; | |
664 | default: | |
665 | /* nothing */ | |
666 | break; | |
667 | } | |
668 | return wait; | |
669 | } | |
670 | ||
671 | /* called from spice server thread context */ | |
672 | static void interface_notify_update(QXLInstance *sin, uint32_t update_id) | |
673 | { | |
674 | fprintf(stderr, "%s: abort()\n", __FUNCTION__); | |
675 | abort(); | |
676 | } | |
677 | ||
678 | /* called from spice server thread context only */ | |
679 | static int interface_flush_resources(QXLInstance *sin) | |
680 | { | |
681 | PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl); | |
682 | int ret; | |
683 | ||
684 | dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res); | |
685 | ret = qxl->num_free_res; | |
686 | if (ret) { | |
687 | qxl_push_free_res(qxl, 1); | |
688 | } | |
689 | return ret; | |
690 | } | |
691 | ||
692 | static const QXLInterface qxl_interface = { | |
693 | .base.type = SPICE_INTERFACE_QXL, | |
694 | .base.description = "qxl gpu", | |
695 | .base.major_version = SPICE_INTERFACE_QXL_MAJOR, | |
696 | .base.minor_version = SPICE_INTERFACE_QXL_MINOR, | |
697 | ||
698 | .attache_worker = interface_attach_worker, | |
699 | .set_compression_level = interface_set_compression_level, | |
700 | .set_mm_time = interface_set_mm_time, | |
701 | .get_init_info = interface_get_init_info, | |
702 | ||
703 | /* the callbacks below are called from spice server thread context */ | |
704 | .get_command = interface_get_command, | |
705 | .req_cmd_notification = interface_req_cmd_notification, | |
706 | .release_resource = interface_release_resource, | |
707 | .get_cursor_command = interface_get_cursor_command, | |
708 | .req_cursor_notification = interface_req_cursor_notification, | |
709 | .notify_update = interface_notify_update, | |
710 | .flush_resources = interface_flush_resources, | |
711 | }; | |
712 | ||
713 | static void qxl_enter_vga_mode(PCIQXLDevice *d) | |
714 | { | |
715 | if (d->mode == QXL_MODE_VGA) { | |
716 | return; | |
717 | } | |
718 | dprint(d, 1, "%s\n", __FUNCTION__); | |
719 | qemu_spice_create_host_primary(&d->ssd); | |
720 | d->mode = QXL_MODE_VGA; | |
721 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
722 | } | |
723 | ||
724 | static void qxl_exit_vga_mode(PCIQXLDevice *d) | |
725 | { | |
726 | if (d->mode != QXL_MODE_VGA) { | |
727 | return; | |
728 | } | |
729 | dprint(d, 1, "%s\n", __FUNCTION__); | |
730 | qxl_destroy_primary(d); | |
731 | } | |
732 | ||
733 | static void qxl_set_irq(PCIQXLDevice *d) | |
734 | { | |
735 | uint32_t pending = le32_to_cpu(d->ram->int_pending); | |
736 | uint32_t mask = le32_to_cpu(d->ram->int_mask); | |
737 | int level = !!(pending & mask); | |
738 | qemu_set_irq(d->pci.irq[0], level); | |
739 | qxl_ring_set_dirty(d); | |
740 | } | |
741 | ||
742 | static void qxl_write_config(PCIDevice *d, uint32_t address, | |
743 | uint32_t val, int len) | |
744 | { | |
745 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d); | |
746 | VGACommonState *vga = &qxl->vga; | |
747 | ||
748 | vga_dirty_log_stop(vga); | |
749 | pci_default_write_config(d, address, val, len); | |
750 | if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) { | |
751 | vga->map_addr = 0; | |
752 | } | |
753 | vga_dirty_log_start(vga); | |
754 | } | |
755 | ||
756 | static void qxl_check_state(PCIQXLDevice *d) | |
757 | { | |
758 | QXLRam *ram = d->ram; | |
759 | ||
760 | assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring)); | |
761 | assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
762 | } | |
763 | ||
764 | static void qxl_reset_state(PCIQXLDevice *d) | |
765 | { | |
766 | QXLRam *ram = d->ram; | |
767 | QXLRom *rom = d->rom; | |
768 | ||
8927cfbb YH |
769 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); |
770 | assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); | |
a19cbfb3 GH |
771 | d->shadow_rom.update_id = cpu_to_le32(0); |
772 | *rom = d->shadow_rom; | |
773 | qxl_rom_set_dirty(d); | |
774 | init_qxl_ram(d); | |
775 | d->num_free_res = 0; | |
776 | d->last_release = NULL; | |
777 | memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); | |
778 | } | |
779 | ||
780 | static void qxl_soft_reset(PCIQXLDevice *d) | |
781 | { | |
782 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
783 | qxl_check_state(d); | |
784 | ||
785 | if (d->id == 0) { | |
786 | qxl_enter_vga_mode(d); | |
787 | } else { | |
788 | d->mode = QXL_MODE_UNDEFINED; | |
789 | } | |
790 | } | |
791 | ||
792 | static void qxl_hard_reset(PCIQXLDevice *d, int loadvm) | |
793 | { | |
794 | dprint(d, 1, "%s: start%s\n", __FUNCTION__, | |
795 | loadvm ? " (loadvm)" : ""); | |
796 | ||
aee32bf3 GH |
797 | qxl_spice_reset_cursor(d); |
798 | qxl_spice_reset_image_cache(d); | |
a19cbfb3 GH |
799 | qxl_reset_surfaces(d); |
800 | qxl_reset_memslots(d); | |
801 | ||
802 | /* pre loadvm reset must not touch QXLRam. This lives in | |
803 | * device memory, is migrated together with RAM and thus | |
804 | * already loaded at this point */ | |
805 | if (!loadvm) { | |
806 | qxl_reset_state(d); | |
807 | } | |
808 | qemu_spice_create_host_memslot(&d->ssd); | |
809 | qxl_soft_reset(d); | |
810 | ||
811 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
812 | } | |
813 | ||
814 | static void qxl_reset_handler(DeviceState *dev) | |
815 | { | |
816 | PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev); | |
817 | qxl_hard_reset(d, 0); | |
818 | } | |
819 | ||
820 | static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
821 | { | |
822 | VGACommonState *vga = opaque; | |
823 | PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga); | |
824 | ||
825 | if (qxl->mode != QXL_MODE_VGA) { | |
826 | dprint(qxl, 1, "%s\n", __FUNCTION__); | |
827 | qxl_destroy_primary(qxl); | |
828 | qxl_soft_reset(qxl); | |
829 | } | |
830 | vga_ioport_write(opaque, addr, val); | |
831 | } | |
832 | ||
833 | static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta) | |
834 | { | |
835 | static const int regions[] = { | |
836 | QXL_RAM_RANGE_INDEX, | |
837 | QXL_VRAM_RANGE_INDEX, | |
838 | }; | |
839 | uint64_t guest_start; | |
840 | uint64_t guest_end; | |
841 | int pci_region; | |
842 | pcibus_t pci_start; | |
843 | pcibus_t pci_end; | |
844 | intptr_t virt_start; | |
845 | QXLDevMemSlot memslot; | |
846 | int i; | |
847 | ||
848 | guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); | |
849 | guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); | |
850 | ||
851 | dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n", | |
852 | __FUNCTION__, slot_id, | |
853 | guest_start, guest_end); | |
854 | ||
855 | PANIC_ON(slot_id >= NUM_MEMSLOTS); | |
856 | PANIC_ON(guest_start > guest_end); | |
857 | ||
858 | for (i = 0; i < ARRAY_SIZE(regions); i++) { | |
859 | pci_region = regions[i]; | |
860 | pci_start = d->pci.io_regions[pci_region].addr; | |
861 | pci_end = pci_start + d->pci.io_regions[pci_region].size; | |
862 | /* mapped? */ | |
863 | if (pci_start == -1) { | |
864 | continue; | |
865 | } | |
866 | /* start address in range ? */ | |
867 | if (guest_start < pci_start || guest_start > pci_end) { | |
868 | continue; | |
869 | } | |
870 | /* end address in range ? */ | |
871 | if (guest_end > pci_end) { | |
872 | continue; | |
873 | } | |
874 | /* passed */ | |
875 | break; | |
876 | } | |
877 | PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */ | |
878 | ||
879 | switch (pci_region) { | |
880 | case QXL_RAM_RANGE_INDEX: | |
881 | virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset); | |
882 | break; | |
883 | case QXL_VRAM_RANGE_INDEX: | |
884 | virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset); | |
885 | break; | |
886 | default: | |
887 | /* should not happen */ | |
888 | abort(); | |
889 | } | |
890 | ||
891 | memslot.slot_id = slot_id; | |
892 | memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */ | |
893 | memslot.virt_start = virt_start + (guest_start - pci_start); | |
894 | memslot.virt_end = virt_start + (guest_end - pci_start); | |
895 | memslot.addr_delta = memslot.virt_start - delta; | |
896 | memslot.generation = d->rom->slot_generation = 0; | |
897 | qxl_rom_set_dirty(d); | |
898 | ||
899 | dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n", | |
900 | __FUNCTION__, memslot.slot_id, | |
901 | memslot.virt_start, memslot.virt_end); | |
902 | ||
5c59d118 | 903 | qemu_spice_add_memslot(&d->ssd, &memslot); |
a19cbfb3 GH |
904 | d->guest_slots[slot_id].ptr = (void*)memslot.virt_start; |
905 | d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; | |
906 | d->guest_slots[slot_id].delta = delta; | |
907 | d->guest_slots[slot_id].active = 1; | |
908 | } | |
909 | ||
910 | static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id) | |
911 | { | |
912 | dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id); | |
5c59d118 | 913 | qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); |
a19cbfb3 GH |
914 | d->guest_slots[slot_id].active = 0; |
915 | } | |
916 | ||
917 | static void qxl_reset_memslots(PCIQXLDevice *d) | |
918 | { | |
919 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
aee32bf3 | 920 | qxl_spice_reset_memslots(d); |
a19cbfb3 GH |
921 | memset(&d->guest_slots, 0, sizeof(d->guest_slots)); |
922 | } | |
923 | ||
924 | static void qxl_reset_surfaces(PCIQXLDevice *d) | |
925 | { | |
926 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
927 | d->mode = QXL_MODE_UNDEFINED; | |
aee32bf3 | 928 | qxl_spice_destroy_surfaces(d); |
a19cbfb3 GH |
929 | } |
930 | ||
931 | /* called from spice server thread context only */ | |
932 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id) | |
933 | { | |
934 | uint64_t phys = le64_to_cpu(pqxl); | |
935 | uint32_t slot = (phys >> (64 - 8)) & 0xff; | |
936 | uint64_t offset = phys & 0xffffffffffff; | |
937 | ||
938 | switch (group_id) { | |
939 | case MEMSLOT_GROUP_HOST: | |
940 | return (void*)offset; | |
941 | case MEMSLOT_GROUP_GUEST: | |
942 | PANIC_ON(slot > NUM_MEMSLOTS); | |
943 | PANIC_ON(!qxl->guest_slots[slot].active); | |
944 | PANIC_ON(offset < qxl->guest_slots[slot].delta); | |
945 | offset -= qxl->guest_slots[slot].delta; | |
946 | PANIC_ON(offset > qxl->guest_slots[slot].size) | |
947 | return qxl->guest_slots[slot].ptr + offset; | |
948 | default: | |
949 | PANIC_ON(1); | |
950 | } | |
951 | } | |
952 | ||
953 | static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm) | |
954 | { | |
955 | QXLDevSurfaceCreate surface; | |
956 | QXLSurfaceCreate *sc = &qxl->guest_primary.surface; | |
957 | ||
958 | assert(qxl->mode != QXL_MODE_NATIVE); | |
959 | qxl_exit_vga_mode(qxl); | |
960 | ||
961 | dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__, | |
962 | le32_to_cpu(sc->width), le32_to_cpu(sc->height)); | |
963 | ||
964 | surface.format = le32_to_cpu(sc->format); | |
965 | surface.height = le32_to_cpu(sc->height); | |
966 | surface.mem = le64_to_cpu(sc->mem); | |
967 | surface.position = le32_to_cpu(sc->position); | |
968 | surface.stride = le32_to_cpu(sc->stride); | |
969 | surface.width = le32_to_cpu(sc->width); | |
970 | surface.type = le32_to_cpu(sc->type); | |
971 | surface.flags = le32_to_cpu(sc->flags); | |
972 | ||
973 | surface.mouse_mode = true; | |
974 | surface.group_id = MEMSLOT_GROUP_GUEST; | |
975 | if (loadvm) { | |
976 | surface.flags |= QXL_SURF_FLAG_KEEP_DATA; | |
977 | } | |
978 | ||
979 | qxl->mode = QXL_MODE_NATIVE; | |
980 | qxl->cmdflags = 0; | |
5c59d118 | 981 | qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface); |
a19cbfb3 GH |
982 | |
983 | /* for local rendering */ | |
984 | qxl_render_resize(qxl); | |
985 | } | |
986 | ||
987 | static void qxl_destroy_primary(PCIQXLDevice *d) | |
988 | { | |
989 | if (d->mode == QXL_MODE_UNDEFINED) { | |
990 | return; | |
991 | } | |
992 | ||
993 | dprint(d, 1, "%s\n", __FUNCTION__); | |
994 | ||
995 | d->mode = QXL_MODE_UNDEFINED; | |
5c59d118 | 996 | qemu_spice_destroy_primary_surface(&d->ssd, 0); |
a19cbfb3 GH |
997 | } |
998 | ||
999 | static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm) | |
1000 | { | |
1001 | pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1002 | pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; | |
1003 | QXLMode *mode = d->modes->modes + modenr; | |
1004 | uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; | |
1005 | QXLMemSlot slot = { | |
1006 | .mem_start = start, | |
1007 | .mem_end = end | |
1008 | }; | |
1009 | QXLSurfaceCreate surface = { | |
1010 | .width = mode->x_res, | |
1011 | .height = mode->y_res, | |
1012 | .stride = -mode->x_res * 4, | |
1013 | .format = SPICE_SURFACE_FMT_32_xRGB, | |
1014 | .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0, | |
1015 | .mouse_mode = true, | |
1016 | .mem = devmem + d->shadow_rom.draw_area_offset, | |
1017 | }; | |
1018 | ||
1019 | dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__, | |
1020 | modenr, mode->x_res, mode->y_res, mode->bits, devmem); | |
1021 | if (!loadvm) { | |
1022 | qxl_hard_reset(d, 0); | |
1023 | } | |
1024 | ||
1025 | d->guest_slots[0].slot = slot; | |
1026 | qxl_add_memslot(d, 0, devmem); | |
1027 | ||
1028 | d->guest_primary.surface = surface; | |
1029 | qxl_create_guest_primary(d, 0); | |
1030 | ||
1031 | d->mode = QXL_MODE_COMPAT; | |
1032 | d->cmdflags = QXL_COMMAND_FLAG_COMPAT; | |
1033 | #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */ | |
1034 | if (mode->bits == 16) { | |
1035 | d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; | |
1036 | } | |
1037 | #endif | |
1038 | d->shadow_rom.mode = cpu_to_le32(modenr); | |
1039 | d->rom->mode = cpu_to_le32(modenr); | |
1040 | qxl_rom_set_dirty(d); | |
1041 | } | |
1042 | ||
1043 | static void ioport_write(void *opaque, uint32_t addr, uint32_t val) | |
1044 | { | |
1045 | PCIQXLDevice *d = opaque; | |
1046 | uint32_t io_port = addr - d->io_base; | |
1047 | ||
1048 | switch (io_port) { | |
1049 | case QXL_IO_RESET: | |
1050 | case QXL_IO_SET_MODE: | |
1051 | case QXL_IO_MEMSLOT_ADD: | |
1052 | case QXL_IO_MEMSLOT_DEL: | |
1053 | case QXL_IO_CREATE_PRIMARY: | |
81144d1a | 1054 | case QXL_IO_UPDATE_IRQ: |
a3d14054 | 1055 | case QXL_IO_LOG: |
a19cbfb3 GH |
1056 | break; |
1057 | default: | |
1058 | if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT) | |
1059 | break; | |
8b92e298 AL |
1060 | dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n", |
1061 | __func__, io_port, io_port_to_string(io_port)); | |
a19cbfb3 GH |
1062 | return; |
1063 | } | |
1064 | ||
1065 | switch (io_port) { | |
1066 | case QXL_IO_UPDATE_AREA: | |
1067 | { | |
1068 | QXLRect update = d->ram->update_area; | |
aee32bf3 GH |
1069 | qxl_spice_update_area(d, d->ram->update_surface, |
1070 | &update, NULL, 0, 0); | |
a19cbfb3 GH |
1071 | break; |
1072 | } | |
1073 | case QXL_IO_NOTIFY_CMD: | |
5c59d118 | 1074 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1075 | break; |
1076 | case QXL_IO_NOTIFY_CURSOR: | |
5c59d118 | 1077 | qemu_spice_wakeup(&d->ssd); |
a19cbfb3 GH |
1078 | break; |
1079 | case QXL_IO_UPDATE_IRQ: | |
1080 | qxl_set_irq(d); | |
1081 | break; | |
1082 | case QXL_IO_NOTIFY_OOM: | |
1083 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { | |
1084 | break; | |
1085 | } | |
1086 | pthread_yield(); | |
1087 | if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) { | |
1088 | break; | |
1089 | } | |
1090 | d->oom_running = 1; | |
aee32bf3 | 1091 | qxl_spice_oom(d); |
a19cbfb3 GH |
1092 | d->oom_running = 0; |
1093 | break; | |
1094 | case QXL_IO_SET_MODE: | |
1095 | dprint(d, 1, "QXL_SET_MODE %d\n", val); | |
1096 | qxl_set_mode(d, val, 0); | |
1097 | break; | |
1098 | case QXL_IO_LOG: | |
1099 | if (d->guestdebug) { | |
6ebebb55 AL |
1100 | fprintf(stderr, "qxl/guest-%d: %ld: %s", d->id, |
1101 | qemu_get_clock_ns(vm_clock), d->ram->log_buf); | |
a19cbfb3 GH |
1102 | } |
1103 | break; | |
1104 | case QXL_IO_RESET: | |
1105 | dprint(d, 1, "QXL_IO_RESET\n"); | |
1106 | qxl_hard_reset(d, 0); | |
1107 | break; | |
1108 | case QXL_IO_MEMSLOT_ADD: | |
2bce0400 GH |
1109 | if (val >= NUM_MEMSLOTS) { |
1110 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range"); | |
1111 | break; | |
1112 | } | |
1113 | if (d->guest_slots[val].active) { | |
1114 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active"); | |
1115 | break; | |
1116 | } | |
a19cbfb3 GH |
1117 | d->guest_slots[val].slot = d->ram->mem_slot; |
1118 | qxl_add_memslot(d, val, 0); | |
1119 | break; | |
1120 | case QXL_IO_MEMSLOT_DEL: | |
2bce0400 GH |
1121 | if (val >= NUM_MEMSLOTS) { |
1122 | qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range"); | |
1123 | break; | |
1124 | } | |
a19cbfb3 GH |
1125 | qxl_del_memslot(d, val); |
1126 | break; | |
1127 | case QXL_IO_CREATE_PRIMARY: | |
2bce0400 GH |
1128 | if (val != 0) { |
1129 | qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY: val != 0"); | |
1130 | break; | |
1131 | } | |
a19cbfb3 GH |
1132 | dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n"); |
1133 | d->guest_primary.surface = d->ram->create_surface; | |
1134 | qxl_create_guest_primary(d, 0); | |
1135 | break; | |
1136 | case QXL_IO_DESTROY_PRIMARY: | |
2bce0400 GH |
1137 | if (val != 0) { |
1138 | qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY: val != 0"); | |
1139 | break; | |
1140 | } | |
5b77870c | 1141 | dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (%s)\n", qxl_mode_to_string(d->mode)); |
a19cbfb3 GH |
1142 | qxl_destroy_primary(d); |
1143 | break; | |
1144 | case QXL_IO_DESTROY_SURFACE_WAIT: | |
aee32bf3 | 1145 | qxl_spice_destroy_surface_wait(d, val); |
a19cbfb3 GH |
1146 | break; |
1147 | case QXL_IO_DESTROY_ALL_SURFACES: | |
aee32bf3 | 1148 | qxl_spice_destroy_surfaces(d); |
a19cbfb3 GH |
1149 | break; |
1150 | default: | |
1151 | fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port); | |
1152 | abort(); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | static uint32_t ioport_read(void *opaque, uint32_t addr) | |
1157 | { | |
1158 | PCIQXLDevice *d = opaque; | |
1159 | ||
1160 | dprint(d, 1, "%s: unexpected\n", __FUNCTION__); | |
1161 | return 0xff; | |
1162 | } | |
1163 | ||
1164 | static void qxl_map(PCIDevice *pci, int region_num, | |
1165 | pcibus_t addr, pcibus_t size, int type) | |
1166 | { | |
1167 | static const char *names[] = { | |
1168 | [ QXL_IO_RANGE_INDEX ] = "ioports", | |
1169 | [ QXL_RAM_RANGE_INDEX ] = "devram", | |
1170 | [ QXL_ROM_RANGE_INDEX ] = "rom", | |
1171 | [ QXL_VRAM_RANGE_INDEX ] = "vram", | |
1172 | }; | |
1173 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci); | |
1174 | ||
1175 | dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__, | |
1176 | region_num, names[region_num], addr, size); | |
1177 | ||
1178 | switch (region_num) { | |
1179 | case QXL_IO_RANGE_INDEX: | |
1180 | register_ioport_write(addr, size, 1, ioport_write, pci); | |
1181 | register_ioport_read(addr, size, 1, ioport_read, pci); | |
1182 | qxl->io_base = addr; | |
1183 | break; | |
1184 | case QXL_RAM_RANGE_INDEX: | |
1185 | cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM); | |
1186 | qxl->vga.map_addr = addr; | |
1187 | qxl->vga.map_end = addr + size; | |
1188 | if (qxl->id == 0) { | |
1189 | vga_dirty_log_start(&qxl->vga); | |
1190 | } | |
1191 | break; | |
1192 | case QXL_ROM_RANGE_INDEX: | |
1193 | cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM); | |
1194 | break; | |
1195 | case QXL_VRAM_RANGE_INDEX: | |
1196 | cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM); | |
1197 | break; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | static void pipe_read(void *opaque) | |
1202 | { | |
1203 | PCIQXLDevice *d = opaque; | |
1204 | char dummy; | |
1205 | int len; | |
1206 | ||
1207 | do { | |
1208 | len = read(d->pipe[0], &dummy, sizeof(dummy)); | |
1209 | } while (len == sizeof(dummy)); | |
1210 | qxl_set_irq(d); | |
1211 | } | |
1212 | ||
1213 | /* called from spice server thread context only */ | |
1214 | static void qxl_send_events(PCIQXLDevice *d, uint32_t events) | |
1215 | { | |
1216 | uint32_t old_pending; | |
1217 | uint32_t le_events = cpu_to_le32(events); | |
1218 | ||
1219 | assert(d->ssd.running); | |
1220 | old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events); | |
1221 | if ((old_pending & le_events) == le_events) { | |
1222 | return; | |
1223 | } | |
1224 | if (pthread_self() == d->main) { | |
1225 | qxl_set_irq(d); | |
1226 | } else { | |
1227 | if (write(d->pipe[1], d, 1) != 1) { | |
1228 | dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__); | |
1229 | } | |
1230 | } | |
1231 | } | |
1232 | ||
1233 | static void init_pipe_signaling(PCIQXLDevice *d) | |
1234 | { | |
1235 | if (pipe(d->pipe) < 0) { | |
1236 | dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__); | |
1237 | return; | |
1238 | } | |
1239 | #ifdef CONFIG_IOTHREAD | |
1240 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK); | |
1241 | #else | |
1242 | fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */); | |
1243 | #endif | |
1244 | fcntl(d->pipe[1], F_SETFL, O_NONBLOCK); | |
1245 | fcntl(d->pipe[0], F_SETOWN, getpid()); | |
1246 | ||
1247 | d->main = pthread_self(); | |
1248 | qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d); | |
1249 | } | |
1250 | ||
1251 | /* graphics console */ | |
1252 | ||
1253 | static void qxl_hw_update(void *opaque) | |
1254 | { | |
1255 | PCIQXLDevice *qxl = opaque; | |
1256 | VGACommonState *vga = &qxl->vga; | |
1257 | ||
1258 | switch (qxl->mode) { | |
1259 | case QXL_MODE_VGA: | |
1260 | vga->update(vga); | |
1261 | break; | |
1262 | case QXL_MODE_COMPAT: | |
1263 | case QXL_MODE_NATIVE: | |
1264 | qxl_render_update(qxl); | |
1265 | break; | |
1266 | default: | |
1267 | break; | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | static void qxl_hw_invalidate(void *opaque) | |
1272 | { | |
1273 | PCIQXLDevice *qxl = opaque; | |
1274 | VGACommonState *vga = &qxl->vga; | |
1275 | ||
1276 | vga->invalidate(vga); | |
1277 | } | |
1278 | ||
1279 | static void qxl_hw_screen_dump(void *opaque, const char *filename) | |
1280 | { | |
1281 | PCIQXLDevice *qxl = opaque; | |
1282 | VGACommonState *vga = &qxl->vga; | |
1283 | ||
1284 | switch (qxl->mode) { | |
1285 | case QXL_MODE_COMPAT: | |
1286 | case QXL_MODE_NATIVE: | |
1287 | qxl_render_update(qxl); | |
1288 | ppm_save(filename, qxl->ssd.ds->surface); | |
1289 | break; | |
1290 | case QXL_MODE_VGA: | |
1291 | vga->screen_dump(vga, filename); | |
1292 | break; | |
1293 | default: | |
1294 | break; | |
1295 | } | |
1296 | } | |
1297 | ||
1298 | static void qxl_hw_text_update(void *opaque, console_ch_t *chardata) | |
1299 | { | |
1300 | PCIQXLDevice *qxl = opaque; | |
1301 | VGACommonState *vga = &qxl->vga; | |
1302 | ||
1303 | if (qxl->mode == QXL_MODE_VGA) { | |
1304 | vga->text_update(vga, chardata); | |
1305 | return; | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | static void qxl_vm_change_state_handler(void *opaque, int running, int reason) | |
1310 | { | |
1311 | PCIQXLDevice *qxl = opaque; | |
1312 | qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason); | |
1313 | ||
1314 | if (!running && qxl->mode == QXL_MODE_NATIVE) { | |
868379ce YH |
1315 | /* dirty all vram (which holds surfaces) and devram (primary surface) |
1316 | * to make sure they are saved */ | |
a19cbfb3 GH |
1317 | /* FIXME #1: should go out during "live" stage */ |
1318 | /* FIXME #2: we only need to save the areas which are actually used */ | |
868379ce YH |
1319 | ram_addr_t vram_addr = qxl->vram_offset; |
1320 | ram_addr_t surface0_addr = qxl->vga.vram_offset + qxl->shadow_rom.draw_area_offset; | |
1321 | qxl_set_dirty(vram_addr, vram_addr + qxl->vram_size); | |
1322 | qxl_set_dirty(surface0_addr, surface0_addr + qxl->shadow_rom.surface0_area_size); | |
a19cbfb3 GH |
1323 | } |
1324 | } | |
1325 | ||
1326 | /* display change listener */ | |
1327 | ||
1328 | static void display_update(struct DisplayState *ds, int x, int y, int w, int h) | |
1329 | { | |
1330 | if (qxl0->mode == QXL_MODE_VGA) { | |
1331 | qemu_spice_display_update(&qxl0->ssd, x, y, w, h); | |
1332 | } | |
1333 | } | |
1334 | ||
1335 | static void display_resize(struct DisplayState *ds) | |
1336 | { | |
1337 | if (qxl0->mode == QXL_MODE_VGA) { | |
1338 | qemu_spice_display_resize(&qxl0->ssd); | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | static void display_refresh(struct DisplayState *ds) | |
1343 | { | |
1344 | if (qxl0->mode == QXL_MODE_VGA) { | |
1345 | qemu_spice_display_refresh(&qxl0->ssd); | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | static DisplayChangeListener display_listener = { | |
1350 | .dpy_update = display_update, | |
1351 | .dpy_resize = display_resize, | |
1352 | .dpy_refresh = display_refresh, | |
1353 | }; | |
1354 | ||
1355 | static int qxl_init_common(PCIQXLDevice *qxl) | |
1356 | { | |
1357 | uint8_t* config = qxl->pci.config; | |
a19cbfb3 GH |
1358 | uint32_t pci_device_rev; |
1359 | uint32_t io_size; | |
1360 | ||
1361 | qxl->mode = QXL_MODE_UNDEFINED; | |
1362 | qxl->generation = 1; | |
1363 | qxl->num_memslots = NUM_MEMSLOTS; | |
1364 | qxl->num_surfaces = NUM_SURFACES; | |
14898cf6 | 1365 | qemu_mutex_init(&qxl->track_lock); |
a19cbfb3 GH |
1366 | |
1367 | switch (qxl->revision) { | |
1368 | case 1: /* spice 0.4 -- qxl-1 */ | |
a19cbfb3 GH |
1369 | pci_device_rev = QXL_REVISION_STABLE_V04; |
1370 | break; | |
1371 | case 2: /* spice 0.6 -- qxl-2 */ | |
638f4e47 | 1372 | default: |
a19cbfb3 GH |
1373 | pci_device_rev = QXL_REVISION_STABLE_V06; |
1374 | break; | |
a19cbfb3 GH |
1375 | } |
1376 | ||
a19cbfb3 GH |
1377 | pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev); |
1378 | pci_set_byte(&config[PCI_INTERRUPT_PIN], 1); | |
1379 | ||
1380 | qxl->rom_size = qxl_rom_size(); | |
1381 | qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size); | |
1382 | init_qxl_rom(qxl); | |
1383 | init_qxl_ram(qxl); | |
1384 | ||
1385 | if (qxl->vram_size < 16 * 1024 * 1024) { | |
1386 | qxl->vram_size = 16 * 1024 * 1024; | |
1387 | } | |
1388 | if (qxl->revision == 1) { | |
1389 | qxl->vram_size = 4096; | |
1390 | } | |
1391 | qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1); | |
1392 | qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size); | |
1393 | ||
1394 | io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1); | |
1395 | if (qxl->revision == 1) { | |
1396 | io_size = 8; | |
1397 | } | |
1398 | ||
1399 | pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX, | |
1400 | io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map); | |
1401 | ||
1402 | pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX, | |
1403 | qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1404 | qxl_map); | |
1405 | ||
1406 | pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX, | |
1407 | qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
1408 | qxl_map); | |
1409 | ||
1410 | pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size, | |
1411 | PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map); | |
1412 | ||
1413 | qxl->ssd.qxl.base.sif = &qxl_interface.base; | |
1414 | qxl->ssd.qxl.id = qxl->id; | |
1415 | qemu_spice_add_interface(&qxl->ssd.qxl.base); | |
1416 | qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl); | |
1417 | ||
1418 | init_pipe_signaling(qxl); | |
1419 | qxl_reset_state(qxl); | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | static int qxl_init_primary(PCIDevice *dev) | |
1425 | { | |
1426 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
1427 | VGACommonState *vga = &qxl->vga; | |
1428 | ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1); | |
1429 | ||
1430 | qxl->id = 0; | |
1431 | ||
1432 | if (ram_size < 32 * 1024 * 1024) { | |
1433 | ram_size = 32 * 1024 * 1024; | |
1434 | } | |
1435 | vga_common_init(vga, ram_size); | |
1436 | vga_init(vga); | |
1437 | register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga); | |
1438 | register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga); | |
1439 | register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga); | |
1440 | register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga); | |
1441 | register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga); | |
1442 | ||
1443 | vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate, | |
1444 | qxl_hw_screen_dump, qxl_hw_text_update, qxl); | |
a963f876 | 1445 | qemu_spice_display_init_common(&qxl->ssd, vga->ds); |
a19cbfb3 GH |
1446 | |
1447 | qxl0 = qxl; | |
1448 | register_displaychangelistener(vga->ds, &display_listener); | |
1449 | ||
a19cbfb3 GH |
1450 | return qxl_init_common(qxl); |
1451 | } | |
1452 | ||
1453 | static int qxl_init_secondary(PCIDevice *dev) | |
1454 | { | |
1455 | static int device_id = 1; | |
1456 | PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev); | |
1457 | ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1); | |
1458 | ||
1459 | qxl->id = device_id++; | |
1460 | ||
1461 | if (ram_size < 16 * 1024 * 1024) { | |
1462 | ram_size = 16 * 1024 * 1024; | |
1463 | } | |
1464 | qxl->vga.vram_size = ram_size; | |
1465 | qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram", | |
1466 | qxl->vga.vram_size); | |
1467 | qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset); | |
1468 | ||
a19cbfb3 GH |
1469 | return qxl_init_common(qxl); |
1470 | } | |
1471 | ||
1472 | static void qxl_pre_save(void *opaque) | |
1473 | { | |
1474 | PCIQXLDevice* d = opaque; | |
1475 | uint8_t *ram_start = d->vga.vram_ptr; | |
1476 | ||
1477 | dprint(d, 1, "%s:\n", __FUNCTION__); | |
1478 | if (d->last_release == NULL) { | |
1479 | d->last_release_offset = 0; | |
1480 | } else { | |
1481 | d->last_release_offset = (uint8_t *)d->last_release - ram_start; | |
1482 | } | |
1483 | assert(d->last_release_offset < d->vga.vram_size); | |
1484 | } | |
1485 | ||
1486 | static int qxl_pre_load(void *opaque) | |
1487 | { | |
1488 | PCIQXLDevice* d = opaque; | |
1489 | ||
1490 | dprint(d, 1, "%s: start\n", __FUNCTION__); | |
1491 | qxl_hard_reset(d, 1); | |
1492 | qxl_exit_vga_mode(d); | |
1493 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
1494 | return 0; | |
1495 | } | |
1496 | ||
1497 | static int qxl_post_load(void *opaque, int version) | |
1498 | { | |
1499 | PCIQXLDevice* d = opaque; | |
1500 | uint8_t *ram_start = d->vga.vram_ptr; | |
1501 | QXLCommandExt *cmds; | |
1502 | int in, out, i, newmode; | |
1503 | ||
1504 | dprint(d, 1, "%s: start\n", __FUNCTION__); | |
1505 | ||
1506 | assert(d->last_release_offset < d->vga.vram_size); | |
1507 | if (d->last_release_offset == 0) { | |
1508 | d->last_release = NULL; | |
1509 | } else { | |
1510 | d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset); | |
1511 | } | |
1512 | ||
1513 | d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset); | |
1514 | ||
5b77870c AL |
1515 | dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__, |
1516 | qxl_mode_to_string(d->mode)); | |
a19cbfb3 GH |
1517 | newmode = d->mode; |
1518 | d->mode = QXL_MODE_UNDEFINED; | |
1519 | switch (newmode) { | |
1520 | case QXL_MODE_UNDEFINED: | |
1521 | break; | |
1522 | case QXL_MODE_VGA: | |
1523 | qxl_enter_vga_mode(d); | |
1524 | break; | |
1525 | case QXL_MODE_NATIVE: | |
1526 | for (i = 0; i < NUM_MEMSLOTS; i++) { | |
1527 | if (!d->guest_slots[i].active) { | |
1528 | continue; | |
1529 | } | |
1530 | qxl_add_memslot(d, i, 0); | |
1531 | } | |
1532 | qxl_create_guest_primary(d, 1); | |
1533 | ||
1534 | /* replay surface-create and cursor-set commands */ | |
1535 | cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1)); | |
1536 | for (in = 0, out = 0; in < NUM_SURFACES; in++) { | |
1537 | if (d->guest_surfaces.cmds[in] == 0) { | |
1538 | continue; | |
1539 | } | |
1540 | cmds[out].cmd.data = d->guest_surfaces.cmds[in]; | |
1541 | cmds[out].cmd.type = QXL_CMD_SURFACE; | |
1542 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1543 | out++; | |
1544 | } | |
1545 | cmds[out].cmd.data = d->guest_cursor; | |
1546 | cmds[out].cmd.type = QXL_CMD_CURSOR; | |
1547 | cmds[out].group_id = MEMSLOT_GROUP_GUEST; | |
1548 | out++; | |
aee32bf3 | 1549 | qxl_spice_loadvm_commands(d, cmds, out); |
a19cbfb3 GH |
1550 | qemu_free(cmds); |
1551 | ||
1552 | break; | |
1553 | case QXL_MODE_COMPAT: | |
1554 | qxl_set_mode(d, d->shadow_rom.mode, 1); | |
1555 | break; | |
1556 | } | |
1557 | dprint(d, 1, "%s: done\n", __FUNCTION__); | |
1558 | ||
a19cbfb3 GH |
1559 | return 0; |
1560 | } | |
1561 | ||
b67737a6 | 1562 | #define QXL_SAVE_VERSION 21 |
a19cbfb3 GH |
1563 | |
1564 | static VMStateDescription qxl_memslot = { | |
1565 | .name = "qxl-memslot", | |
1566 | .version_id = QXL_SAVE_VERSION, | |
1567 | .minimum_version_id = QXL_SAVE_VERSION, | |
1568 | .fields = (VMStateField[]) { | |
1569 | VMSTATE_UINT64(slot.mem_start, struct guest_slots), | |
1570 | VMSTATE_UINT64(slot.mem_end, struct guest_slots), | |
1571 | VMSTATE_UINT32(active, struct guest_slots), | |
1572 | VMSTATE_END_OF_LIST() | |
1573 | } | |
1574 | }; | |
1575 | ||
1576 | static VMStateDescription qxl_surface = { | |
1577 | .name = "qxl-surface", | |
1578 | .version_id = QXL_SAVE_VERSION, | |
1579 | .minimum_version_id = QXL_SAVE_VERSION, | |
1580 | .fields = (VMStateField[]) { | |
1581 | VMSTATE_UINT32(width, QXLSurfaceCreate), | |
1582 | VMSTATE_UINT32(height, QXLSurfaceCreate), | |
1583 | VMSTATE_INT32(stride, QXLSurfaceCreate), | |
1584 | VMSTATE_UINT32(format, QXLSurfaceCreate), | |
1585 | VMSTATE_UINT32(position, QXLSurfaceCreate), | |
1586 | VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate), | |
1587 | VMSTATE_UINT32(flags, QXLSurfaceCreate), | |
1588 | VMSTATE_UINT32(type, QXLSurfaceCreate), | |
1589 | VMSTATE_UINT64(mem, QXLSurfaceCreate), | |
1590 | VMSTATE_END_OF_LIST() | |
1591 | } | |
1592 | }; | |
1593 | ||
a19cbfb3 GH |
1594 | static VMStateDescription qxl_vmstate = { |
1595 | .name = "qxl", | |
1596 | .version_id = QXL_SAVE_VERSION, | |
1597 | .minimum_version_id = QXL_SAVE_VERSION, | |
1598 | .pre_save = qxl_pre_save, | |
1599 | .pre_load = qxl_pre_load, | |
1600 | .post_load = qxl_post_load, | |
1601 | .fields = (VMStateField []) { | |
1602 | VMSTATE_PCI_DEVICE(pci, PCIQXLDevice), | |
1603 | VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState), | |
1604 | VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice), | |
1605 | VMSTATE_UINT32(num_free_res, PCIQXLDevice), | |
1606 | VMSTATE_UINT32(last_release_offset, PCIQXLDevice), | |
1607 | VMSTATE_UINT32(mode, PCIQXLDevice), | |
1608 | VMSTATE_UINT32(ssd.unique, PCIQXLDevice), | |
b67737a6 GH |
1609 | VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice), |
1610 | VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0, | |
1611 | qxl_memslot, struct guest_slots), | |
1612 | VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0, | |
1613 | qxl_surface, QXLSurfaceCreate), | |
1614 | VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice), | |
1615 | VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0, | |
1616 | vmstate_info_uint64, uint64_t), | |
1617 | VMSTATE_UINT64(guest_cursor, PCIQXLDevice), | |
a19cbfb3 GH |
1618 | VMSTATE_END_OF_LIST() |
1619 | }, | |
a19cbfb3 GH |
1620 | }; |
1621 | ||
1622 | static PCIDeviceInfo qxl_info_primary = { | |
1623 | .qdev.name = "qxl-vga", | |
1624 | .qdev.desc = "Spice QXL GPU (primary, vga compatible)", | |
1625 | .qdev.size = sizeof(PCIQXLDevice), | |
1626 | .qdev.reset = qxl_reset_handler, | |
1627 | .qdev.vmsd = &qxl_vmstate, | |
2f6bfe3b | 1628 | .no_hotplug = 1, |
a19cbfb3 GH |
1629 | .init = qxl_init_primary, |
1630 | .config_write = qxl_write_config, | |
1631 | .romfile = "vgabios-qxl.bin", | |
96c05abc | 1632 | .vendor_id = REDHAT_PCI_VENDOR_ID, |
638f4e47 | 1633 | .device_id = QXL_DEVICE_ID_STABLE, |
96c05abc | 1634 | .class_id = PCI_CLASS_DISPLAY_VGA, |
a19cbfb3 GH |
1635 | .qdev.props = (Property[]) { |
1636 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024), | |
1637 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024), | |
1638 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2), | |
1639 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
1640 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
1641 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
1642 | DEFINE_PROP_END_OF_LIST(), | |
1643 | } | |
1644 | }; | |
1645 | ||
1646 | static PCIDeviceInfo qxl_info_secondary = { | |
1647 | .qdev.name = "qxl", | |
1648 | .qdev.desc = "Spice QXL GPU (secondary)", | |
1649 | .qdev.size = sizeof(PCIQXLDevice), | |
1650 | .qdev.reset = qxl_reset_handler, | |
1651 | .qdev.vmsd = &qxl_vmstate, | |
1652 | .init = qxl_init_secondary, | |
96c05abc | 1653 | .vendor_id = REDHAT_PCI_VENDOR_ID, |
638f4e47 | 1654 | .device_id = QXL_DEVICE_ID_STABLE, |
96c05abc | 1655 | .class_id = PCI_CLASS_DISPLAY_OTHER, |
a19cbfb3 GH |
1656 | .qdev.props = (Property[]) { |
1657 | DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024), | |
1658 | DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024), | |
1659 | DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2), | |
1660 | DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0), | |
1661 | DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0), | |
1662 | DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0), | |
1663 | DEFINE_PROP_END_OF_LIST(), | |
1664 | } | |
1665 | }; | |
1666 | ||
1667 | static void qxl_register(void) | |
1668 | { | |
1669 | pci_qdev_register(&qxl_info_primary); | |
1670 | pci_qdev_register(&qxl_info_secondary); | |
1671 | } | |
1672 | ||
1673 | device_init(qxl_register); |