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spice: add qemu_spice_display_init_common
[qemu.git] / hw / qxl.c
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a19cbfb3
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <pthread.h>
22
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "qemu-queue.h"
26#include "monitor.h"
27#include "sysemu.h"
28
29#include "qxl.h"
30
31#undef SPICE_RING_PROD_ITEM
32#define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43#undef SPICE_RING_CONS_ITEM
44#define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55#undef ALIGN
56#define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58#define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60#define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70#define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74#define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104#if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111#endif
112#if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117#endif
118};
119
120static PCIQXLDevice *qxl0;
121
122static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123static void qxl_destroy_primary(PCIQXLDevice *d);
124static void qxl_reset_memslots(PCIQXLDevice *d);
125static void qxl_reset_surfaces(PCIQXLDevice *d);
126static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
128static inline uint32_t msb_mask(uint32_t val)
129{
130 uint32_t mask;
131
132 do {
133 mask = ~(val - 1) & val;
134 val &= ~mask;
135 } while (mask < val);
136
137 return mask;
138}
139
140static ram_addr_t qxl_rom_size(void)
141{
142 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
143 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
144 rom_size = msb_mask(rom_size * 2 - 1);
145 return rom_size;
146}
147
148static void init_qxl_rom(PCIQXLDevice *d)
149{
150 QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
151 QXLModes *modes = (QXLModes *)(rom + 1);
152 uint32_t ram_header_size;
153 uint32_t surface0_area_size;
154 uint32_t num_pages;
155 uint32_t fb, maxfb = 0;
156 int i;
157
158 memset(rom, 0, d->rom_size);
159
160 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
161 rom->id = cpu_to_le32(d->id);
162 rom->log_level = cpu_to_le32(d->guestdebug);
163 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
164
165 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
166 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
167 rom->slots_start = 1;
168 rom->slots_end = NUM_MEMSLOTS - 1;
169 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
170
171 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
172 for (i = 0; i < modes->n_modes; i++) {
173 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
174 if (maxfb < fb) {
175 maxfb = fb;
176 }
177 modes->modes[i].id = cpu_to_le32(i);
178 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
179 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
180 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
181 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
182 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
183 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
184 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
185 }
186 if (maxfb < VGA_RAM_SIZE && d->id == 0)
187 maxfb = VGA_RAM_SIZE;
188
189 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
190 surface0_area_size = ALIGN(maxfb, 4096);
191 num_pages = d->vga.vram_size;
192 num_pages -= ram_header_size;
193 num_pages -= surface0_area_size;
194 num_pages = num_pages / TARGET_PAGE_SIZE;
195
196 rom->draw_area_offset = cpu_to_le32(0);
197 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
198 rom->pages_offset = cpu_to_le32(surface0_area_size);
199 rom->num_pages = cpu_to_le32(num_pages);
200 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
201
202 d->shadow_rom = *rom;
203 d->rom = rom;
204 d->modes = modes;
205}
206
207static void init_qxl_ram(PCIQXLDevice *d)
208{
209 uint8_t *buf;
210 uint64_t *item;
211
212 buf = d->vga.vram_ptr;
213 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
214 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
215 d->ram->int_pending = cpu_to_le32(0);
216 d->ram->int_mask = cpu_to_le32(0);
217 SPICE_RING_INIT(&d->ram->cmd_ring);
218 SPICE_RING_INIT(&d->ram->cursor_ring);
219 SPICE_RING_INIT(&d->ram->release_ring);
220 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
221 *item = 0;
222 qxl_ring_set_dirty(d);
223}
224
225/* can be called from spice server thread context */
226static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
227{
228 while (addr < end) {
229 cpu_physical_memory_set_dirty(addr);
230 addr += TARGET_PAGE_SIZE;
231 }
232}
233
234static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
235{
236 ram_addr_t addr = qxl->rom_offset;
237 qxl_set_dirty(addr, addr + qxl->rom_size);
238}
239
240/* called from spice server thread context only */
241static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
242{
243 ram_addr_t addr = qxl->vga.vram_offset;
244 void *base = qxl->vga.vram_ptr;
245 intptr_t offset;
246
247 offset = ptr - base;
248 offset &= ~(TARGET_PAGE_SIZE-1);
249 assert(offset < qxl->vga.vram_size);
250 qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
251}
252
253/* can be called from spice server thread context */
254static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
255{
256 ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
257 ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
258 qxl_set_dirty(addr, end);
259}
260
261/*
262 * keep track of some command state, for savevm/loadvm.
263 * called from spice server thread context only
264 */
265static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
266{
267 switch (le32_to_cpu(ext->cmd.type)) {
268 case QXL_CMD_SURFACE:
269 {
270 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
271 uint32_t id = le32_to_cpu(cmd->surface_id);
272 PANIC_ON(id >= NUM_SURFACES);
273 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
274 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
275 qxl->guest_surfaces.count++;
276 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
277 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
278 }
279 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
280 qxl->guest_surfaces.cmds[id] = 0;
281 qxl->guest_surfaces.count--;
282 }
283 break;
284 }
285 case QXL_CMD_CURSOR:
286 {
287 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
288 if (cmd->type == QXL_CURSOR_SET) {
289 qxl->guest_cursor = ext->cmd.data;
290 }
291 break;
292 }
293 }
294}
295
296/* spice display interface callbacks */
297
298static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
299{
300 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
301
302 dprint(qxl, 1, "%s:\n", __FUNCTION__);
303 qxl->ssd.worker = qxl_worker;
304}
305
306static void interface_set_compression_level(QXLInstance *sin, int level)
307{
308 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
309
310 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
311 qxl->shadow_rom.compression_level = cpu_to_le32(level);
312 qxl->rom->compression_level = cpu_to_le32(level);
313 qxl_rom_set_dirty(qxl);
314}
315
316static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
317{
318 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
319
320 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
321 qxl->rom->mm_clock = cpu_to_le32(mm_time);
322 qxl_rom_set_dirty(qxl);
323}
324
325static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
326{
327 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
328
329 dprint(qxl, 1, "%s:\n", __FUNCTION__);
330 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
331 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
332 info->num_memslots = NUM_MEMSLOTS;
333 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
334 info->internal_groupslot_id = 0;
335 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
336 info->n_surfaces = NUM_SURFACES;
337}
338
5b77870c
AL		 339static const char *qxl_mode_to_string(int mode)
340{
341 switch (mode) {
342 case QXL_MODE_COMPAT:
343 return "compat";
344 case QXL_MODE_NATIVE:
345 return "native";
346 case QXL_MODE_UNDEFINED:
347 return "undefined";
348 case QXL_MODE_VGA:
349 return "vga";
350 }
351 return "INVALID";
352}
353
a19cbfb3
GH		 354/* called from spice server thread context only */
355static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
356{
357 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
358 SimpleSpiceUpdate *update;
359 QXLCommandRing *ring;
360 QXLCommand *cmd;
e0c64d08 361 int notify, ret;
a19cbfb3
GH		 362
363 switch (qxl->mode) {
364 case QXL_MODE_VGA:
365 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
e0c64d08
GH		 366 ret = false;
367 qemu_mutex_lock(&qxl->ssd.lock);
368 if (qxl->ssd.update != NULL) {
369 update = qxl->ssd.update;
370 qxl->ssd.update = NULL;
371 *ext = update->ext;
372 ret = true;
a19cbfb3 373 }
e0c64d08 374 qemu_mutex_unlock(&qxl->ssd.lock);
212496c9 375 if (ret) {
5b77870c 376 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
212496c9
AL		 377 qxl_log_command(qxl, "vga", ext);
378 }
e0c64d08 379 return ret;
a19cbfb3
GH		 380 case QXL_MODE_COMPAT:
381 case QXL_MODE_NATIVE:
382 case QXL_MODE_UNDEFINED:
5b77870c 383 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 384 ring = &qxl->ram->cmd_ring;
385 if (SPICE_RING_IS_EMPTY(ring)) {
386 return false;
387 }
5b77870c 388 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
a19cbfb3
GH		 389 SPICE_RING_CONS_ITEM(ring, cmd);
390 ext->cmd = *cmd;
391 ext->group_id = MEMSLOT_GROUP_GUEST;
392 ext->flags = qxl->cmdflags;
393 SPICE_RING_POP(ring, notify);
394 qxl_ring_set_dirty(qxl);
395 if (notify) {
396 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
397 }
398 qxl->guest_primary.commands++;
399 qxl_track_command(qxl, ext);
400 qxl_log_command(qxl, "cmd", ext);
401 return true;
402 default:
403 return false;
404 }
405}
406
407/* called from spice server thread context only */
408static int interface_req_cmd_notification(QXLInstance *sin)
409{
410 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
411 int wait = 1;
412
413 switch (qxl->mode) {
414 case QXL_MODE_COMPAT:
415 case QXL_MODE_NATIVE:
416 case QXL_MODE_UNDEFINED:
417 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
418 qxl_ring_set_dirty(qxl);
419 break;
420 default:
421 /* nothing */
422 break;
423 }
424 return wait;
425}
426
427/* called from spice server thread context only */
428static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
429{
430 QXLReleaseRing *ring = &d->ram->release_ring;
431 uint64_t *item;
432 int notify;
433
434#define QXL_FREE_BUNCH_SIZE 32
435
436 if (ring->prod - ring->cons + 1 == ring->num_items) {
437 /* ring full -- can't push */
438 return;
439 }
440 if (!flush && d->oom_running) {
441 /* collect everything from oom handler before pushing */
442 return;
443 }
444 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
445 /* collect a bit more before pushing */
446 return;
447 }
448
449 SPICE_RING_PUSH(ring, notify);
450 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
451 d->num_free_res, notify ? "yes" : "no",
452 ring->prod - ring->cons, ring->num_items,
453 ring->prod, ring->cons);
454 if (notify) {
455 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
456 }
457 SPICE_RING_PROD_ITEM(ring, item);
458 *item = 0;
459 d->num_free_res = 0;
460 d->last_release = NULL;
461 qxl_ring_set_dirty(d);
462}
463
464/* called from spice server thread context only */
465static void interface_release_resource(QXLInstance *sin,
466 struct QXLReleaseInfoExt ext)
467{
468 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
469 QXLReleaseRing *ring;
470 uint64_t *item, id;
471
472 if (ext.group_id == MEMSLOT_GROUP_HOST) {
473 /* host group -> vga mode update request */
474 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
475 return;
476 }
477
478 /*
479 * ext->info points into guest-visible memory
480 * pci bar 0, $command.release_info
481 */
482 ring = &qxl->ram->release_ring;
483 SPICE_RING_PROD_ITEM(ring, item);
484 if (*item == 0) {
485 /* stick head into the ring */
486 id = ext.info->id;
487 ext.info->next = 0;
488 qxl_ram_set_dirty(qxl, &ext.info->next);
489 *item = id;
490 qxl_ring_set_dirty(qxl);
491 } else {
492 /* append item to the list */
493 qxl->last_release->next = ext.info->id;
494 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
495 ext.info->next = 0;
496 qxl_ram_set_dirty(qxl, &ext.info->next);
497 }
498 qxl->last_release = ext.info;
499 qxl->num_free_res++;
500 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
501 qxl_push_free_res(qxl, 0);
502}
503
504/* called from spice server thread context only */
505static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
506{
507 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
508 QXLCursorRing *ring;
509 QXLCommand *cmd;
510 int notify;
511
512 switch (qxl->mode) {
513 case QXL_MODE_COMPAT:
514 case QXL_MODE_NATIVE:
515 case QXL_MODE_UNDEFINED:
516 ring = &qxl->ram->cursor_ring;
517 if (SPICE_RING_IS_EMPTY(ring)) {
518 return false;
519 }
520 SPICE_RING_CONS_ITEM(ring, cmd);
521 ext->cmd = *cmd;
522 ext->group_id = MEMSLOT_GROUP_GUEST;
523 ext->flags = qxl->cmdflags;
524 SPICE_RING_POP(ring, notify);
525 qxl_ring_set_dirty(qxl);
526 if (notify) {
527 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
528 }
529 qxl->guest_primary.commands++;
530 qxl_track_command(qxl, ext);
531 qxl_log_command(qxl, "csr", ext);
532 if (qxl->id == 0) {
533 qxl_render_cursor(qxl, ext);
534 }
535 return true;
536 default:
537 return false;
538 }
539}
540
541/* called from spice server thread context only */
542static int interface_req_cursor_notification(QXLInstance *sin)
543{
544 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
545 int wait = 1;
546
547 switch (qxl->mode) {
548 case QXL_MODE_COMPAT:
549 case QXL_MODE_NATIVE:
550 case QXL_MODE_UNDEFINED:
551 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
552 qxl_ring_set_dirty(qxl);
553 break;
554 default:
555 /* nothing */
556 break;
557 }
558 return wait;
559}
560
561/* called from spice server thread context */
562static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
563{
564 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
565 abort();
566}
567
568/* called from spice server thread context only */
569static int interface_flush_resources(QXLInstance *sin)
570{
571 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
572 int ret;
573
574 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
575 ret = qxl->num_free_res;
576 if (ret) {
577 qxl_push_free_res(qxl, 1);
578 }
579 return ret;
580}
581
582static const QXLInterface qxl_interface = {
583 .base.type = SPICE_INTERFACE_QXL,
584 .base.description = "qxl gpu",
585 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
586 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
587
588 .attache_worker = interface_attach_worker,
589 .set_compression_level = interface_set_compression_level,
590 .set_mm_time = interface_set_mm_time,
591 .get_init_info = interface_get_init_info,
592
593 /* the callbacks below are called from spice server thread context */
594 .get_command = interface_get_command,
595 .req_cmd_notification = interface_req_cmd_notification,
596 .release_resource = interface_release_resource,
597 .get_cursor_command = interface_get_cursor_command,
598 .req_cursor_notification = interface_req_cursor_notification,
599 .notify_update = interface_notify_update,
600 .flush_resources = interface_flush_resources,
601};
602
603static void qxl_enter_vga_mode(PCIQXLDevice *d)
604{
605 if (d->mode == QXL_MODE_VGA) {
606 return;
607 }
608 dprint(d, 1, "%s\n", __FUNCTION__);
609 qemu_spice_create_host_primary(&d->ssd);
610 d->mode = QXL_MODE_VGA;
611 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
612}
613
614static void qxl_exit_vga_mode(PCIQXLDevice *d)
615{
616 if (d->mode != QXL_MODE_VGA) {
617 return;
618 }
619 dprint(d, 1, "%s\n", __FUNCTION__);
620 qxl_destroy_primary(d);
621}
622
623static void qxl_set_irq(PCIQXLDevice *d)
624{
625 uint32_t pending = le32_to_cpu(d->ram->int_pending);
626 uint32_t mask = le32_to_cpu(d->ram->int_mask);
627 int level = !!(pending & mask);
628 qemu_set_irq(d->pci.irq[0], level);
629 qxl_ring_set_dirty(d);
630}
631
632static void qxl_write_config(PCIDevice *d, uint32_t address,
633 uint32_t val, int len)
634{
635 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
636 VGACommonState *vga = &qxl->vga;
637
638 vga_dirty_log_stop(vga);
639 pci_default_write_config(d, address, val, len);
640 if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
641 vga->map_addr = 0;
642 }
643 vga_dirty_log_start(vga);
644}
645
646static void qxl_check_state(PCIQXLDevice *d)
647{
648 QXLRam *ram = d->ram;
649
650 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
651 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
652}
653
654static void qxl_reset_state(PCIQXLDevice *d)
655{
656 QXLRam *ram = d->ram;
657 QXLRom *rom = d->rom;
658
8927cfbb
YH		 659 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
660 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
a19cbfb3
GH		 661 d->shadow_rom.update_id = cpu_to_le32(0);
662 *rom = d->shadow_rom;
663 qxl_rom_set_dirty(d);
664 init_qxl_ram(d);
665 d->num_free_res = 0;
666 d->last_release = NULL;
667 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
668}
669
670static void qxl_soft_reset(PCIQXLDevice *d)
671{
672 dprint(d, 1, "%s:\n", __FUNCTION__);
673 qxl_check_state(d);
674
675 if (d->id == 0) {
676 qxl_enter_vga_mode(d);
677 } else {
678 d->mode = QXL_MODE_UNDEFINED;
679 }
680}
681
682static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
683{
684 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
685 loadvm ? " (loadvm)" : "");
686
5c59d118
GH		 687 qemu_spice_reset_cursor(&d->ssd);
688 qemu_spice_reset_image_cache(&d->ssd);
a19cbfb3
GH		 689 qxl_reset_surfaces(d);
690 qxl_reset_memslots(d);
691
692 /* pre loadvm reset must not touch QXLRam. This lives in
693 * device memory, is migrated together with RAM and thus
694 * already loaded at this point */
695 if (!loadvm) {
696 qxl_reset_state(d);
697 }
698 qemu_spice_create_host_memslot(&d->ssd);
699 qxl_soft_reset(d);
700
701 dprint(d, 1, "%s: done\n", __FUNCTION__);
702}
703
704static void qxl_reset_handler(DeviceState *dev)
705{
706 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
707 qxl_hard_reset(d, 0);
708}
709
710static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
711{
712 VGACommonState *vga = opaque;
713 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
714
715 if (qxl->mode != QXL_MODE_VGA) {
716 dprint(qxl, 1, "%s\n", __FUNCTION__);
717 qxl_destroy_primary(qxl);
718 qxl_soft_reset(qxl);
719 }
720 vga_ioport_write(opaque, addr, val);
721}
722
723static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
724{
725 static const int regions[] = {
726 QXL_RAM_RANGE_INDEX,
727 QXL_VRAM_RANGE_INDEX,
728 };
729 uint64_t guest_start;
730 uint64_t guest_end;
731 int pci_region;
732 pcibus_t pci_start;
733 pcibus_t pci_end;
734 intptr_t virt_start;
735 QXLDevMemSlot memslot;
736 int i;
737
738 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
739 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
740
741 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
742 __FUNCTION__, slot_id,
743 guest_start, guest_end);
744
745 PANIC_ON(slot_id >= NUM_MEMSLOTS);
746 PANIC_ON(guest_start > guest_end);
747
748 for (i = 0; i < ARRAY_SIZE(regions); i++) {
749 pci_region = regions[i];
750 pci_start = d->pci.io_regions[pci_region].addr;
751 pci_end = pci_start + d->pci.io_regions[pci_region].size;
752 /* mapped? */
753 if (pci_start == -1) {
754 continue;
755 }
756 /* start address in range ? */
757 if (guest_start < pci_start || guest_start > pci_end) {
758 continue;
759 }
760 /* end address in range ? */
761 if (guest_end > pci_end) {
762 continue;
763 }
764 /* passed */
765 break;
766 }
767 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
768
769 switch (pci_region) {
770 case QXL_RAM_RANGE_INDEX:
771 virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
772 break;
773 case QXL_VRAM_RANGE_INDEX:
774 virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
775 break;
776 default:
777 /* should not happen */
778 abort();
779 }
780
781 memslot.slot_id = slot_id;
782 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
783 memslot.virt_start = virt_start + (guest_start - pci_start);
784 memslot.virt_end = virt_start + (guest_end - pci_start);
785 memslot.addr_delta = memslot.virt_start - delta;
786 memslot.generation = d->rom->slot_generation = 0;
787 qxl_rom_set_dirty(d);
788
789 dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
790 __FUNCTION__, memslot.slot_id,
791 memslot.virt_start, memslot.virt_end);
792
5c59d118 793 qemu_spice_add_memslot(&d->ssd, &memslot);
a19cbfb3
GH		 794 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
795 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
796 d->guest_slots[slot_id].delta = delta;
797 d->guest_slots[slot_id].active = 1;
798}
799
800static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
801{
802 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
5c59d118 803 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
a19cbfb3
GH		 804 d->guest_slots[slot_id].active = 0;
805}
806
807static void qxl_reset_memslots(PCIQXLDevice *d)
808{
809 dprint(d, 1, "%s:\n", __FUNCTION__);
5c59d118 810 qemu_spice_reset_memslots(&d->ssd);
a19cbfb3
GH		 811 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
812}
813
814static void qxl_reset_surfaces(PCIQXLDevice *d)
815{
816 dprint(d, 1, "%s:\n", __FUNCTION__);
817 d->mode = QXL_MODE_UNDEFINED;
5c59d118 818 qemu_spice_destroy_surfaces(&d->ssd);
a19cbfb3
GH		 819 memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds));
820}
821
822/* called from spice server thread context only */
823void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
824{
825 uint64_t phys = le64_to_cpu(pqxl);
826 uint32_t slot = (phys >> (64 - 8)) & 0xff;
827 uint64_t offset = phys & 0xffffffffffff;
828
829 switch (group_id) {
830 case MEMSLOT_GROUP_HOST:
831 return (void*)offset;
832 case MEMSLOT_GROUP_GUEST:
833 PANIC_ON(slot > NUM_MEMSLOTS);
834 PANIC_ON(!qxl->guest_slots[slot].active);
835 PANIC_ON(offset < qxl->guest_slots[slot].delta);
836 offset -= qxl->guest_slots[slot].delta;
837 PANIC_ON(offset > qxl->guest_slots[slot].size)
838 return qxl->guest_slots[slot].ptr + offset;
839 default:
840 PANIC_ON(1);
841 }
842}
843
844static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
845{
846 QXLDevSurfaceCreate surface;
847 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
848
849 assert(qxl->mode != QXL_MODE_NATIVE);
850 qxl_exit_vga_mode(qxl);
851
852 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
853 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
854
855 surface.format = le32_to_cpu(sc->format);
856 surface.height = le32_to_cpu(sc->height);
857 surface.mem = le64_to_cpu(sc->mem);
858 surface.position = le32_to_cpu(sc->position);
859 surface.stride = le32_to_cpu(sc->stride);
860 surface.width = le32_to_cpu(sc->width);
861 surface.type = le32_to_cpu(sc->type);
862 surface.flags = le32_to_cpu(sc->flags);
863
864 surface.mouse_mode = true;
865 surface.group_id = MEMSLOT_GROUP_GUEST;
866 if (loadvm) {
867 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
868 }
869
870 qxl->mode = QXL_MODE_NATIVE;
871 qxl->cmdflags = 0;
5c59d118 872 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface);
a19cbfb3
GH		 873
874 /* for local rendering */
875 qxl_render_resize(qxl);
876}
877
878static void qxl_destroy_primary(PCIQXLDevice *d)
879{
880 if (d->mode == QXL_MODE_UNDEFINED) {
881 return;
882 }
883
884 dprint(d, 1, "%s\n", __FUNCTION__);
885
886 d->mode = QXL_MODE_UNDEFINED;
5c59d118 887 qemu_spice_destroy_primary_surface(&d->ssd, 0);
a19cbfb3
GH		 888}
889
890static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
891{
892 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
893 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
894 QXLMode *mode = d->modes->modes + modenr;
895 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
896 QXLMemSlot slot = {
897 .mem_start = start,
898 .mem_end = end
899 };
900 QXLSurfaceCreate surface = {
901 .width = mode->x_res,
902 .height = mode->y_res,
903 .stride = -mode->x_res * 4,
904 .format = SPICE_SURFACE_FMT_32_xRGB,
905 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
906 .mouse_mode = true,
907 .mem = devmem + d->shadow_rom.draw_area_offset,
908 };
909
910 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
911 modenr, mode->x_res, mode->y_res, mode->bits, devmem);
912 if (!loadvm) {
913 qxl_hard_reset(d, 0);
914 }
915
916 d->guest_slots[0].slot = slot;
917 qxl_add_memslot(d, 0, devmem);
918
919 d->guest_primary.surface = surface;
920 qxl_create_guest_primary(d, 0);
921
922 d->mode = QXL_MODE_COMPAT;
923 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
924#ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
925 if (mode->bits == 16) {
926 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
927 }
928#endif
929 d->shadow_rom.mode = cpu_to_le32(modenr);
930 d->rom->mode = cpu_to_le32(modenr);
931 qxl_rom_set_dirty(d);
932}
933
934static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
935{
936 PCIQXLDevice *d = opaque;
937 uint32_t io_port = addr - d->io_base;
938
939 switch (io_port) {
940 case QXL_IO_RESET:
941 case QXL_IO_SET_MODE:
942 case QXL_IO_MEMSLOT_ADD:
943 case QXL_IO_MEMSLOT_DEL:
944 case QXL_IO_CREATE_PRIMARY:
81144d1a 945 case QXL_IO_UPDATE_IRQ:
a3d14054 946 case QXL_IO_LOG:
a19cbfb3
GH		 947 break;
948 default:
949 if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
950 break;
951 dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port);
952 return;
953 }
954
955 switch (io_port) {
956 case QXL_IO_UPDATE_AREA:
957 {
958 QXLRect update = d->ram->update_area;
5c59d118
GH		 959 qemu_spice_update_area(&d->ssd, d->ram->update_surface,
960 &update, NULL, 0, 0);
a19cbfb3
GH		 961 break;
962 }
963 case QXL_IO_NOTIFY_CMD:
5c59d118 964 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 965 break;
966 case QXL_IO_NOTIFY_CURSOR:
5c59d118 967 qemu_spice_wakeup(&d->ssd);
a19cbfb3
GH		 968 break;
969 case QXL_IO_UPDATE_IRQ:
970 qxl_set_irq(d);
971 break;
972 case QXL_IO_NOTIFY_OOM:
973 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
974 break;
975 }
976 pthread_yield();
977 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
978 break;
979 }
980 d->oom_running = 1;
5c59d118 981 qemu_spice_oom(&d->ssd);
a19cbfb3
GH		 982 d->oom_running = 0;
983 break;
984 case QXL_IO_SET_MODE:
985 dprint(d, 1, "QXL_SET_MODE %d\n", val);
986 qxl_set_mode(d, val, 0);
987 break;
988 case QXL_IO_LOG:
989 if (d->guestdebug) {
6ebebb55
AL		 990 fprintf(stderr, "qxl/guest-%d: %ld: %s", d->id,
991 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
a19cbfb3
GH		 992 }
993 break;
994 case QXL_IO_RESET:
995 dprint(d, 1, "QXL_IO_RESET\n");
996 qxl_hard_reset(d, 0);
997 break;
998 case QXL_IO_MEMSLOT_ADD:
999 PANIC_ON(val >= NUM_MEMSLOTS);
1000 PANIC_ON(d->guest_slots[val].active);
1001 d->guest_slots[val].slot = d->ram->mem_slot;
1002 qxl_add_memslot(d, val, 0);
1003 break;
1004 case QXL_IO_MEMSLOT_DEL:
1005 qxl_del_memslot(d, val);
1006 break;
1007 case QXL_IO_CREATE_PRIMARY:
1008 PANIC_ON(val != 0);
1009 dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
1010 d->guest_primary.surface = d->ram->create_surface;
1011 qxl_create_guest_primary(d, 0);
1012 break;
1013 case QXL_IO_DESTROY_PRIMARY:
1014 PANIC_ON(val != 0);
5b77870c 1015 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (%s)\n", qxl_mode_to_string(d->mode));
a19cbfb3
GH		 1016 qxl_destroy_primary(d);
1017 break;
1018 case QXL_IO_DESTROY_SURFACE_WAIT:
5c59d118 1019 qemu_spice_destroy_surface_wait(&d->ssd, val);
a19cbfb3
GH		 1020 break;
1021 case QXL_IO_DESTROY_ALL_SURFACES:
5c59d118 1022 qemu_spice_destroy_surfaces(&d->ssd);
a19cbfb3
GH		 1023 break;
1024 default:
1025 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1026 abort();
1027 }
1028}
1029
1030static uint32_t ioport_read(void *opaque, uint32_t addr)
1031{
1032 PCIQXLDevice *d = opaque;
1033
1034 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1035 return 0xff;
1036}
1037
1038static void qxl_map(PCIDevice *pci, int region_num,
1039 pcibus_t addr, pcibus_t size, int type)
1040{
1041 static const char *names[] = {
1042 [ QXL_IO_RANGE_INDEX ] = "ioports",
1043 [ QXL_RAM_RANGE_INDEX ] = "devram",
1044 [ QXL_ROM_RANGE_INDEX ] = "rom",
1045 [ QXL_VRAM_RANGE_INDEX ] = "vram",
1046 };
1047 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1048
1049 dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1050 region_num, names[region_num], addr, size);
1051
1052 switch (region_num) {
1053 case QXL_IO_RANGE_INDEX:
1054 register_ioport_write(addr, size, 1, ioport_write, pci);
1055 register_ioport_read(addr, size, 1, ioport_read, pci);
1056 qxl->io_base = addr;
1057 break;
1058 case QXL_RAM_RANGE_INDEX:
1059 cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1060 qxl->vga.map_addr = addr;
1061 qxl->vga.map_end = addr + size;
1062 if (qxl->id == 0) {
1063 vga_dirty_log_start(&qxl->vga);
1064 }
1065 break;
1066 case QXL_ROM_RANGE_INDEX:
1067 cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1068 break;
1069 case QXL_VRAM_RANGE_INDEX:
1070 cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1071 break;
1072 }
1073}
1074
1075static void pipe_read(void *opaque)
1076{
1077 PCIQXLDevice *d = opaque;
1078 char dummy;
1079 int len;
1080
1081 do {
1082 len = read(d->pipe[0], &dummy, sizeof(dummy));
1083 } while (len == sizeof(dummy));
1084 qxl_set_irq(d);
1085}
1086
1087/* called from spice server thread context only */
1088static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1089{
1090 uint32_t old_pending;
1091 uint32_t le_events = cpu_to_le32(events);
1092
1093 assert(d->ssd.running);
1094 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1095 if ((old_pending & le_events) == le_events) {
1096 return;
1097 }
1098 if (pthread_self() == d->main) {
1099 qxl_set_irq(d);
1100 } else {
1101 if (write(d->pipe[1], d, 1) != 1) {
1102 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1103 }
1104 }
1105}
1106
1107static void init_pipe_signaling(PCIQXLDevice *d)
1108{
1109 if (pipe(d->pipe) < 0) {
1110 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1111 return;
1112 }
1113#ifdef CONFIG_IOTHREAD
1114 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1115#else
1116 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1117#endif
1118 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1119 fcntl(d->pipe[0], F_SETOWN, getpid());
1120
1121 d->main = pthread_self();
1122 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1123}
1124
1125/* graphics console */
1126
1127static void qxl_hw_update(void *opaque)
1128{
1129 PCIQXLDevice *qxl = opaque;
1130 VGACommonState *vga = &qxl->vga;
1131
1132 switch (qxl->mode) {
1133 case QXL_MODE_VGA:
1134 vga->update(vga);
1135 break;
1136 case QXL_MODE_COMPAT:
1137 case QXL_MODE_NATIVE:
1138 qxl_render_update(qxl);
1139 break;
1140 default:
1141 break;
1142 }
1143}
1144
1145static void qxl_hw_invalidate(void *opaque)
1146{
1147 PCIQXLDevice *qxl = opaque;
1148 VGACommonState *vga = &qxl->vga;
1149
1150 vga->invalidate(vga);
1151}
1152
1153static void qxl_hw_screen_dump(void *opaque, const char *filename)
1154{
1155 PCIQXLDevice *qxl = opaque;
1156 VGACommonState *vga = &qxl->vga;
1157
1158 switch (qxl->mode) {
1159 case QXL_MODE_COMPAT:
1160 case QXL_MODE_NATIVE:
1161 qxl_render_update(qxl);
1162 ppm_save(filename, qxl->ssd.ds->surface);
1163 break;
1164 case QXL_MODE_VGA:
1165 vga->screen_dump(vga, filename);
1166 break;
1167 default:
1168 break;
1169 }
1170}
1171
1172static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1173{
1174 PCIQXLDevice *qxl = opaque;
1175 VGACommonState *vga = &qxl->vga;
1176
1177 if (qxl->mode == QXL_MODE_VGA) {
1178 vga->text_update(vga, chardata);
1179 return;
1180 }
1181}
1182
1183static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1184{
1185 PCIQXLDevice *qxl = opaque;
1186 qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1187
1188 if (!running && qxl->mode == QXL_MODE_NATIVE) {
868379ce
YH		 1189 /* dirty all vram (which holds surfaces) and devram (primary surface)
1190 * to make sure they are saved */
a19cbfb3
GH		 1191 /* FIXME #1: should go out during "live" stage */
1192 /* FIXME #2: we only need to save the areas which are actually used */
868379ce
YH		 1193 ram_addr_t vram_addr = qxl->vram_offset;
1194 ram_addr_t surface0_addr = qxl->vga.vram_offset + qxl->shadow_rom.draw_area_offset;
1195 qxl_set_dirty(vram_addr, vram_addr + qxl->vram_size);
1196 qxl_set_dirty(surface0_addr, surface0_addr + qxl->shadow_rom.surface0_area_size);
a19cbfb3
GH		 1197 }
1198}
1199
1200/* display change listener */
1201
1202static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1203{
1204 if (qxl0->mode == QXL_MODE_VGA) {
1205 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1206 }
1207}
1208
1209static void display_resize(struct DisplayState *ds)
1210{
1211 if (qxl0->mode == QXL_MODE_VGA) {
1212 qemu_spice_display_resize(&qxl0->ssd);
1213 }
1214}
1215
1216static void display_refresh(struct DisplayState *ds)
1217{
1218 if (qxl0->mode == QXL_MODE_VGA) {
1219 qemu_spice_display_refresh(&qxl0->ssd);
1220 }
1221}
1222
1223static DisplayChangeListener display_listener = {
1224 .dpy_update = display_update,
1225 .dpy_resize = display_resize,
1226 .dpy_refresh = display_refresh,
1227};
1228
1229static int qxl_init_common(PCIQXLDevice *qxl)
1230{
1231 uint8_t* config = qxl->pci.config;
a19cbfb3
GH		 1232 uint32_t pci_device_rev;
1233 uint32_t io_size;
1234
1235 qxl->mode = QXL_MODE_UNDEFINED;
1236 qxl->generation = 1;
1237 qxl->num_memslots = NUM_MEMSLOTS;
1238 qxl->num_surfaces = NUM_SURFACES;
1239
1240 switch (qxl->revision) {
1241 case 1: /* spice 0.4 -- qxl-1 */
a19cbfb3
GH		 1242 pci_device_rev = QXL_REVISION_STABLE_V04;
1243 break;
1244 case 2: /* spice 0.6 -- qxl-2 */
638f4e47 1245 default:
a19cbfb3
GH		 1246 pci_device_rev = QXL_REVISION_STABLE_V06;
1247 break;
a19cbfb3
GH		 1248 }
1249
a19cbfb3
GH		 1250 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1251 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1252
1253 qxl->rom_size = qxl_rom_size();
1254 qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1255 init_qxl_rom(qxl);
1256 init_qxl_ram(qxl);
1257
1258 if (qxl->vram_size < 16 * 1024 * 1024) {
1259 qxl->vram_size = 16 * 1024 * 1024;
1260 }
1261 if (qxl->revision == 1) {
1262 qxl->vram_size = 4096;
1263 }
1264 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1265 qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1266
1267 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1268 if (qxl->revision == 1) {
1269 io_size = 8;
1270 }
1271
1272 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1273 io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1274
1275 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1276 qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1277 qxl_map);
1278
1279 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1280 qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1281 qxl_map);
1282
1283 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1284 PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1285
1286 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1287 qxl->ssd.qxl.id = qxl->id;
1288 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1289 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1290
1291 init_pipe_signaling(qxl);
1292 qxl_reset_state(qxl);
1293
1294 return 0;
1295}
1296
1297static int qxl_init_primary(PCIDevice *dev)
1298{
1299 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1300 VGACommonState *vga = &qxl->vga;
1301 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1302
1303 qxl->id = 0;
1304
1305 if (ram_size < 32 * 1024 * 1024) {
1306 ram_size = 32 * 1024 * 1024;
1307 }
1308 vga_common_init(vga, ram_size);
1309 vga_init(vga);
1310 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1311 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1312 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1313 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1314 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1315
1316 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1317 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
a963f876 1318 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
a19cbfb3
GH		 1319
1320 qxl0 = qxl;
1321 register_displaychangelistener(vga->ds, &display_listener);
1322
a19cbfb3
GH		 1323 return qxl_init_common(qxl);
1324}
1325
1326static int qxl_init_secondary(PCIDevice *dev)
1327{
1328 static int device_id = 1;
1329 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1330 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1331
1332 qxl->id = device_id++;
1333
1334 if (ram_size < 16 * 1024 * 1024) {
1335 ram_size = 16 * 1024 * 1024;
1336 }
1337 qxl->vga.vram_size = ram_size;
1338 qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1339 qxl->vga.vram_size);
1340 qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1341
a19cbfb3
GH		 1342 return qxl_init_common(qxl);
1343}
1344
1345static void qxl_pre_save(void *opaque)
1346{
1347 PCIQXLDevice* d = opaque;
1348 uint8_t *ram_start = d->vga.vram_ptr;
1349
1350 dprint(d, 1, "%s:\n", __FUNCTION__);
1351 if (d->last_release == NULL) {
1352 d->last_release_offset = 0;
1353 } else {
1354 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1355 }
1356 assert(d->last_release_offset < d->vga.vram_size);
1357}
1358
1359static int qxl_pre_load(void *opaque)
1360{
1361 PCIQXLDevice* d = opaque;
1362
1363 dprint(d, 1, "%s: start\n", __FUNCTION__);
1364 qxl_hard_reset(d, 1);
1365 qxl_exit_vga_mode(d);
1366 dprint(d, 1, "%s: done\n", __FUNCTION__);
1367 return 0;
1368}
1369
1370static int qxl_post_load(void *opaque, int version)
1371{
1372 PCIQXLDevice* d = opaque;
1373 uint8_t *ram_start = d->vga.vram_ptr;
1374 QXLCommandExt *cmds;
1375 int in, out, i, newmode;
1376
1377 dprint(d, 1, "%s: start\n", __FUNCTION__);
1378
1379 assert(d->last_release_offset < d->vga.vram_size);
1380 if (d->last_release_offset == 0) {
1381 d->last_release = NULL;
1382 } else {
1383 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1384 }
1385
1386 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1387
5b77870c
AL		 1388 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1389 qxl_mode_to_string(d->mode));
a19cbfb3
GH		 1390 newmode = d->mode;
1391 d->mode = QXL_MODE_UNDEFINED;
1392 switch (newmode) {
1393 case QXL_MODE_UNDEFINED:
1394 break;
1395 case QXL_MODE_VGA:
1396 qxl_enter_vga_mode(d);
1397 break;
1398 case QXL_MODE_NATIVE:
1399 for (i = 0; i < NUM_MEMSLOTS; i++) {
1400 if (!d->guest_slots[i].active) {
1401 continue;
1402 }
1403 qxl_add_memslot(d, i, 0);
1404 }
1405 qxl_create_guest_primary(d, 1);
1406
1407 /* replay surface-create and cursor-set commands */
1408 cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1409 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1410 if (d->guest_surfaces.cmds[in] == 0) {
1411 continue;
1412 }
1413 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1414 cmds[out].cmd.type = QXL_CMD_SURFACE;
1415 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1416 out++;
1417 }
1418 cmds[out].cmd.data = d->guest_cursor;
1419 cmds[out].cmd.type = QXL_CMD_CURSOR;
1420 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1421 out++;
5c59d118 1422 qemu_spice_loadvm_commands(&d->ssd, cmds, out);
a19cbfb3
GH		 1423 qemu_free(cmds);
1424
1425 break;
1426 case QXL_MODE_COMPAT:
1427 qxl_set_mode(d, d->shadow_rom.mode, 1);
1428 break;
1429 }
1430 dprint(d, 1, "%s: done\n", __FUNCTION__);
1431
a19cbfb3
GH		 1432 return 0;
1433}
1434
b67737a6 1435#define QXL_SAVE_VERSION 21
a19cbfb3
GH		 1436
1437static VMStateDescription qxl_memslot = {
1438 .name = "qxl-memslot",
1439 .version_id = QXL_SAVE_VERSION,
1440 .minimum_version_id = QXL_SAVE_VERSION,
1441 .fields = (VMStateField[]) {
1442 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1443 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1444 VMSTATE_UINT32(active, struct guest_slots),
1445 VMSTATE_END_OF_LIST()
1446 }
1447};
1448
1449static VMStateDescription qxl_surface = {
1450 .name = "qxl-surface",
1451 .version_id = QXL_SAVE_VERSION,
1452 .minimum_version_id = QXL_SAVE_VERSION,
1453 .fields = (VMStateField[]) {
1454 VMSTATE_UINT32(width, QXLSurfaceCreate),
1455 VMSTATE_UINT32(height, QXLSurfaceCreate),
1456 VMSTATE_INT32(stride, QXLSurfaceCreate),
1457 VMSTATE_UINT32(format, QXLSurfaceCreate),
1458 VMSTATE_UINT32(position, QXLSurfaceCreate),
1459 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1460 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1461 VMSTATE_UINT32(type, QXLSurfaceCreate),
1462 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1463 VMSTATE_END_OF_LIST()
1464 }
1465};
1466
a19cbfb3
GH		 1467static VMStateDescription qxl_vmstate = {
1468 .name = "qxl",
1469 .version_id = QXL_SAVE_VERSION,
1470 .minimum_version_id = QXL_SAVE_VERSION,
1471 .pre_save = qxl_pre_save,
1472 .pre_load = qxl_pre_load,
1473 .post_load = qxl_post_load,
1474 .fields = (VMStateField []) {
1475 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1476 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1477 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1478 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1479 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1480 VMSTATE_UINT32(mode, PCIQXLDevice),
1481 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
b67737a6
GH		 1482 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1483 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1484 qxl_memslot, struct guest_slots),
1485 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1486 qxl_surface, QXLSurfaceCreate),
1487 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1488 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1489 vmstate_info_uint64, uint64_t),
1490 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
a19cbfb3
GH		 1491 VMSTATE_END_OF_LIST()
1492 },
a19cbfb3
GH		 1493};
1494
1495static PCIDeviceInfo qxl_info_primary = {
1496 .qdev.name = "qxl-vga",
1497 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1498 .qdev.size = sizeof(PCIQXLDevice),
1499 .qdev.reset = qxl_reset_handler,
1500 .qdev.vmsd = &qxl_vmstate,
2f6bfe3b 1501 .no_hotplug = 1,
a19cbfb3
GH		 1502 .init = qxl_init_primary,
1503 .config_write = qxl_write_config,
1504 .romfile = "vgabios-qxl.bin",
96c05abc 1505 .vendor_id = REDHAT_PCI_VENDOR_ID,
638f4e47 1506 .device_id = QXL_DEVICE_ID_STABLE,
96c05abc 1507 .class_id = PCI_CLASS_DISPLAY_VGA,
a19cbfb3
GH		 1508 .qdev.props = (Property[]) {
1509 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1510 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1511 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1512 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1513 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1514 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1515 DEFINE_PROP_END_OF_LIST(),
1516 }
1517};
1518
1519static PCIDeviceInfo qxl_info_secondary = {
1520 .qdev.name = "qxl",
1521 .qdev.desc = "Spice QXL GPU (secondary)",
1522 .qdev.size = sizeof(PCIQXLDevice),
1523 .qdev.reset = qxl_reset_handler,
1524 .qdev.vmsd = &qxl_vmstate,
1525 .init = qxl_init_secondary,
96c05abc 1526 .vendor_id = REDHAT_PCI_VENDOR_ID,
638f4e47 1527 .device_id = QXL_DEVICE_ID_STABLE,
96c05abc 1528 .class_id = PCI_CLASS_DISPLAY_OTHER,
a19cbfb3
GH		 1529 .qdev.props = (Property[]) {
1530 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1531 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1532 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1533 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1534 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1535 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1536 DEFINE_PROP_END_OF_LIST(),
1537 }
1538};
1539
1540static void qxl_register(void)
1541{
1542 pci_qdev_register(&qxl_info_primary);
1543 pci_qdev_register(&qxl_info_secondary);
1544}
1545
1546device_init(qxl_register);
Qemu copy for testing