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Commit | Line | Data |
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a19cbfb3 GH |
1 | #include "qemu-common.h" |
2 | ||
3 | #include "console.h" | |
4 | #include "hw.h" | |
5 | #include "pci.h" | |
6 | #include "vga_int.h" | |
691f5c7b | 7 | #include "qemu-thread.h" |
a19cbfb3 GH |
8 | |
9 | #include "ui/qemu-spice.h" | |
10 | #include "ui/spice-display.h" | |
11 | ||
12 | enum qxl_mode { | |
13 | QXL_MODE_UNDEFINED, | |
14 | QXL_MODE_VGA, | |
15 | QXL_MODE_COMPAT, /* spice 0.4.x */ | |
16 | QXL_MODE_NATIVE, | |
17 | }; | |
18 | ||
6f2b175a GH |
19 | #ifndef QXL_VRAM64_RANGE_INDEX |
20 | #define QXL_VRAM64_RANGE_INDEX 4 | |
21 | #endif | |
22 | ||
5ff4e36c AL |
23 | #define QXL_UNDEFINED_IO UINT32_MAX |
24 | ||
81fb6f15 AL |
25 | #define QXL_NUM_DIRTY_RECTS 64 |
26 | ||
a19cbfb3 GH |
27 | typedef struct PCIQXLDevice { |
28 | PCIDevice pci; | |
29 | SimpleSpiceDisplay ssd; | |
30 | int id; | |
31 | uint32_t debug; | |
32 | uint32_t guestdebug; | |
33 | uint32_t cmdlog; | |
087e6a42 AL |
34 | |
35 | uint32_t guest_bug; | |
36 | ||
a19cbfb3 GH |
37 | enum qxl_mode mode; |
38 | uint32_t cmdflags; | |
39 | int generation; | |
40 | uint32_t revision; | |
41 | ||
42 | int32_t num_memslots; | |
43 | int32_t num_surfaces; | |
44 | ||
5ff4e36c AL |
45 | uint32_t current_async; |
46 | QemuMutex async_lock; | |
47 | ||
a19cbfb3 GH |
48 | struct guest_slots { |
49 | QXLMemSlot slot; | |
50 | void *ptr; | |
51 | uint64_t size; | |
52 | uint64_t delta; | |
53 | uint32_t active; | |
54 | } guest_slots[NUM_MEMSLOTS]; | |
55 | ||
56 | struct guest_primary { | |
57 | QXLSurfaceCreate surface; | |
58 | uint32_t commands; | |
59 | uint32_t resized; | |
0e2487bd GH |
60 | int32_t qxl_stride; |
61 | uint32_t abs_stride; | |
a19cbfb3 GH |
62 | uint32_t bits_pp; |
63 | uint32_t bytes_pp; | |
4c19ebb5 | 64 | uint8_t *data; |
a19cbfb3 GH |
65 | } guest_primary; |
66 | ||
67 | struct surfaces { | |
68 | QXLPHYSICAL cmds[NUM_SURFACES]; | |
69 | uint32_t count; | |
70 | uint32_t max; | |
71 | } guest_surfaces; | |
72 | QXLPHYSICAL guest_cursor; | |
73 | ||
14898cf6 GH |
74 | QemuMutex track_lock; |
75 | ||
a19cbfb3 | 76 | /* thread signaling */ |
691f5c7b | 77 | QemuThread main; |
a19cbfb3 GH |
78 | int pipe[2]; |
79 | ||
80 | /* ram pci bar */ | |
81 | QXLRam *ram; | |
82 | VGACommonState vga; | |
83 | uint32_t num_free_res; | |
84 | QXLReleaseInfo *last_release; | |
85 | uint32_t last_release_offset; | |
86 | uint32_t oom_running; | |
13d1fd44 | 87 | uint32_t vgamem_size; |
a19cbfb3 GH |
88 | |
89 | /* rom pci bar */ | |
90 | QXLRom shadow_rom; | |
91 | QXLRom *rom; | |
92 | QXLModes *modes; | |
93 | uint32_t rom_size; | |
b1950430 | 94 | MemoryRegion rom_bar; |
a19cbfb3 GH |
95 | |
96 | /* vram pci bar */ | |
97 | uint32_t vram_size; | |
b1950430 | 98 | MemoryRegion vram_bar; |
6f2b175a GH |
99 | uint32_t vram32_size; |
100 | MemoryRegion vram32_bar; | |
a19cbfb3 GH |
101 | |
102 | /* io bar */ | |
b1950430 | 103 | MemoryRegion io_bar; |
017438ee GH |
104 | |
105 | /* user-friendly properties (in megabytes) */ | |
106 | uint32_t ram_size_mb; | |
107 | uint32_t vram_size_mb; | |
6f2b175a | 108 | uint32_t vram32_size_mb; |
13d1fd44 | 109 | uint32_t vgamem_size_mb; |
81fb6f15 AL |
110 | |
111 | /* qxl_render_update state */ | |
112 | int render_update_cookie_num; | |
113 | int num_dirty_rects; | |
114 | QXLRect dirty[QXL_NUM_DIRTY_RECTS]; | |
115 | QEMUBH *update_area_bh; | |
a19cbfb3 GH |
116 | } PCIQXLDevice; |
117 | ||
118 | #define PANIC_ON(x) if ((x)) { \ | |
119 | printf("%s: PANIC %s failed\n", __FUNCTION__, #x); \ | |
2bce0400 | 120 | abort(); \ |
a19cbfb3 GH |
121 | } |
122 | ||
123 | #define dprint(_qxl, _level, _fmt, ...) \ | |
124 | do { \ | |
125 | if (_qxl->debug >= _level) { \ | |
126 | fprintf(stderr, "qxl-%d: ", _qxl->id); \ | |
127 | fprintf(stderr, _fmt, ## __VA_ARGS__); \ | |
128 | } \ | |
129 | } while (0) | |
130 | ||
9197a7c8 | 131 | #define QXL_DEFAULT_REVISION QXL_REVISION_STABLE_V10 |
9197a7c8 | 132 | |
a19cbfb3 GH |
133 | /* qxl.c */ |
134 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id); | |
0a530548 AL |
135 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
136 | GCC_FMT_ATTR(2, 3); | |
a19cbfb3 | 137 | |
aee32bf3 GH |
138 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, |
139 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
140 | uint32_t num_dirty_rects, | |
5ff4e36c | 141 | uint32_t clear_dirty_region, |
2e1a98c9 | 142 | qxl_async_io async, QXLCookie *cookie); |
aee32bf3 GH |
143 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
144 | uint32_t count); | |
145 | void qxl_spice_oom(PCIQXLDevice *qxl); | |
146 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl); | |
aee32bf3 GH |
147 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl); |
148 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl); | |
149 | ||
a19cbfb3 | 150 | /* qxl-logger.c */ |
fae2afb1 AL |
151 | int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id); |
152 | int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext); | |
a19cbfb3 GH |
153 | |
154 | /* qxl-render.c */ | |
155 | void qxl_render_resize(PCIQXLDevice *qxl); | |
156 | void qxl_render_update(PCIQXLDevice *qxl); | |
fae2afb1 | 157 | int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext); |
81fb6f15 AL |
158 | void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie); |
159 | void qxl_render_update_area_bh(void *opaque); |