[qemu.git] / hw / r2d.c

/*
 * Renesas SH7751R R2D-PLUS emulation
 *
 * Copyright (c) 2007 Magnus Damm
 * Copyright (c) 2008 Paul Mundt
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "hw.h"
#include "sh.h"
#include "devices.h"
#include "sysemu.h"
#include "boards.h"
#include "pci.h"
#include "net.h"
#include "sh7750_regs.h"
#include "ide.h"
#include "loader.h"
#include "usb.h"
#include "flash.h"
#include "blockdev.h"

#define FLASH_BASE 0x00000000
#define FLASH_SIZE 0x02000000

#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000

#define SM501_VRAM_SIZE 0x800000

#define BOOT_PARAMS_OFFSET 0x0010000
/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
#define LINUX_LOAD_OFFSET  0x0800000
#define INITRD_LOAD_OFFSET 0x1800000

#define PA_IRLMSK	0x00
#define PA_POWOFF	0x30
#define PA_VERREG	0x32
#define PA_OUTPORT	0x36

typedef struct {
    uint16_t bcr;
    uint16_t irlmsk;
    uint16_t irlmon;
    uint16_t cfctl;
    uint16_t cfpow;
    uint16_t dispctl;
    uint16_t sdmpow;
    uint16_t rtcce;
    uint16_t pcicd;
    uint16_t voyagerrts;
    uint16_t cfrst;
    uint16_t admrts;
    uint16_t extrst;
    uint16_t cfcdintclr;
    uint16_t keyctlclr;
    uint16_t pad0;
    uint16_t pad1;
    uint16_t verreg;
    uint16_t inport;
    uint16_t outport;
    uint16_t bverreg;

/* output pin */
    qemu_irq irl;
} r2d_fpga_t;

enum r2d_fpga_irq {
    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
    NR_IRQS
};

static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
    [CF_IDE]	= {  1, 1<<9 },
    [CF_CD]	= {  2, 1<<8 },
    [PCI_INTA]	= {  9, 1<<14 },
    [PCI_INTB]	= { 10, 1<<13 },
    [PCI_INTC]	= {  3, 1<<12 },
    [PCI_INTD]	= {  0, 1<<11 },
    [SM501]	= {  4, 1<<10 },
    [KEY]	= {  5, 1<<6 },
    [RTC_A]	= {  6, 1<<5 },
    [RTC_T]	= {  7, 1<<4 },
    [SDCARD]	= {  8, 1<<7 },
    [EXT]	= { 11, 1<<0 },
    [TP]	= { 12, 1<<15 },
};

static void update_irl(r2d_fpga_t *fpga)
{
    int i, irl = 15;
    for (i = 0; i < NR_IRQS; i++)
        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
            if (irqtab[i].irl < irl)
                irl = irqtab[i].irl;
    qemu_set_irq(fpga->irl, irl ^ 15);
}

static void r2d_fpga_irq_set(void *opaque, int n, int level)
{
    r2d_fpga_t *fpga = opaque;
    if (level)
        fpga->irlmon |= irqtab[n].msk;
    else
        fpga->irlmon &= ~irqtab[n].msk;
    update_irl(fpga);
}

static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        return s->irlmsk;
    case PA_OUTPORT:
	return s->outport;
    case PA_POWOFF:
	return 0x00;
    case PA_VERREG:
	return 0x10;
    }

    return 0;
}

static void
r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        s->irlmsk = value;
        update_irl(s);
	break;
    case PA_OUTPORT:
	s->outport = value;
	break;
    case PA_POWOFF:
        if (value & 1) {
            qemu_system_shutdown_request();
        }
        break;
    case PA_VERREG:
	/* Discard writes */
	break;
    }
}

static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
    r2d_fpga_read,
    r2d_fpga_read,
    NULL,
};

static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
    r2d_fpga_write,
    r2d_fpga_write,
    NULL,
};

static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
{
    int iomemtype;
    r2d_fpga_t *s;

    s = qemu_mallocz(sizeof(r2d_fpga_t));

    s->irl = irl;

    iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
				       r2d_fpga_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory(base, 0x40, iomemtype);
    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}

typedef struct ResetData {
    CPUState *env;
    uint32_t vector;
} ResetData;

static void main_cpu_reset(void *opaque)
{
    ResetData *s = (ResetData *)opaque;
    CPUState *env = s->env;

    cpu_reset(env);
    env->pc = s->vector;
}

static struct __attribute__((__packed__))
{
    int mount_root_rdonly;
    int ramdisk_flags;
    int orig_root_dev;
    int loader_type;
    int initrd_start;
    int initrd_size;

    char pad[232];

    char kernel_cmdline[256];
} boot_params;

static void r2d_init(ram_addr_t ram_size,
              const char *boot_device,
	      const char *kernel_filename, const char *kernel_cmdline,
	      const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    ResetData *reset_info;
    struct SH7750State *s;
    ram_addr_t sdram_addr;
    qemu_irq *irq;
    DriveInfo *dinfo;
    int i;

    if (!cpu_model)
        cpu_model = "SH7751R";

    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    reset_info = qemu_mallocz(sizeof(ResetData));
    reset_info->env = env;
    reset_info->vector = env->pc;
    qemu_register_reset(main_cpu_reset, reset_info);

    /* Allocate memory space */
    sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
    cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
    /* Register peripherals */
    s = sh7750_init(env);
    irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
    sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB],
                          irq[PCI_INTC], irq[PCI_INTD], NULL);

    sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);

    /* onboard CF (True IDE mode, Master only). */
    dinfo = drive_get(IF_IDE, 0, 0);
    mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
                  dinfo, NULL);

    /* onboard flash memory */
    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
                          dinfo ? dinfo->bdrv : NULL, (16 * 1024),
                          FLASH_SIZE >> 16,
                          1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
                          0x555, 0x2aa, 0);

    /* NIC: rtl8139 on-board, and 2 slots. */
    for (i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);

    /* USB keyboard */
    usbdevice_create("keyboard");

    /* Todo: register on board registers */
    memset(&boot_params, 0, sizeof(boot_params));

    if (kernel_filename) {
        int kernel_size;

        kernel_size = load_image_targphys(kernel_filename,
                                          SDRAM_BASE + LINUX_LOAD_OFFSET,
                                          INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
        if (kernel_size < 0) {
          fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
        stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
        reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
    }

    if (initrd_filename) {
        int initrd_size;

        initrd_size = load_image_targphys(initrd_filename,
                                          SDRAM_BASE + INITRD_LOAD_OFFSET,
                                          SDRAM_SIZE - INITRD_LOAD_OFFSET);

        if (initrd_size < 0) {
          fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        boot_params.loader_type = 1;
        boot_params.initrd_start = INITRD_LOAD_OFFSET;
        boot_params.initrd_size = initrd_size;
    }

    if (kernel_cmdline) {
        strncpy(boot_params.kernel_cmdline, kernel_cmdline,
                sizeof(boot_params.kernel_cmdline));
    }

    rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
                       SDRAM_BASE + BOOT_PARAMS_OFFSET);
}

static QEMUMachine r2d_machine = {
    .name = "r2d",
    .desc = "r2d-plus board",
    .init = r2d_init,
};

static void r2d_machine_init(void)
{
    qemu_register_machine(&r2d_machine);
}

machine_init(r2d_machine_init);
Commit	Line	Data
0d78f544 TS	1	/*
	2	* Renesas SH7751R R2D-PLUS emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
b319feb7	5	* Copyright (c) 2008 Paul Mundt
0d78f544 TS	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
cf154394	26	#include "sysbus.h"
87ecb68b PB	27	#include "hw.h"
87ecb68b PB	28	#include "sh.h"
ffd39257	29	#include "devices.h"
87ecb68b PB	30	#include "sysemu.h"
87ecb68b PB	31	#include "boards.h"
c2f01775 AZ	32	#include "pci.h"
	33	#include "net.h"
	34	#include "sh7750_regs.h"
3d2bf4a1	35	#include "ide.h"
ca20cf32	36	#include "loader.h"
9caa3ec1	37	#include "usb.h"
56839a19	38	#include "flash.h"
2446333c	39	#include "blockdev.h"
56839a19 AJ	40
	41	#define FLASH_BASE 0x00000000
	42	#define FLASH_SIZE 0x02000000
0d78f544 TS	43
	44	#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
	45	#define SDRAM_SIZE 0x04000000
	46
ffd39257 BS	47	#define SM501_VRAM_SIZE 0x800000
ffd39257 BS	48
73f19035	49	#define BOOT_PARAMS_OFFSET 0x0010000
e8afa065	50	/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
73f19035 AJ	51	#define LINUX_LOAD_OFFSET 0x0800000
73f19035 AJ	52	#define INITRD_LOAD_OFFSET 0x1800000
e8afa065	53
d47ede60	54	#define PA_IRLMSK 0x00
b319feb7 AJ	55	#define PA_POWOFF 0x30
	56	#define PA_VERREG 0x32
	57	#define PA_OUTPORT 0x36
	58
	59	typedef struct {
b319feb7	60	uint16_t bcr;
d47ede60	61	uint16_t irlmsk;
b319feb7 AJ	62	uint16_t irlmon;
	63	uint16_t cfctl;
	64	uint16_t cfpow;
	65	uint16_t dispctl;
	66	uint16_t sdmpow;
	67	uint16_t rtcce;
	68	uint16_t pcicd;
	69	uint16_t voyagerrts;
	70	uint16_t cfrst;
	71	uint16_t admrts;
	72	uint16_t extrst;
	73	uint16_t cfcdintclr;
	74	uint16_t keyctlclr;
	75	uint16_t pad0;
	76	uint16_t pad1;
b319feb7 AJ	77	uint16_t verreg;
	78	uint16_t inport;
	79	uint16_t outport;
	80	uint16_t bverreg;
d47ede60 AZ	81
	82	/* output pin */
	83	qemu_irq irl;
c227f099	84	} r2d_fpga_t;
b319feb7	85
d47ede60 AZ	86	enum r2d_fpga_irq {
	87	PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
	88	SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
	89	NR_IRQS
	90	};
	91
	92	static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
	93	[CF_IDE] = { 1, 1<<9 },
	94	[CF_CD] = { 2, 1<<8 },
	95	[PCI_INTA] = { 9, 1<<14 },
	96	[PCI_INTB] = { 10, 1<<13 },
	97	[PCI_INTC] = { 3, 1<<12 },
	98	[PCI_INTD] = { 0, 1<<11 },
	99	[SM501] = { 4, 1<<10 },
	100	[KEY] = { 5, 1<<6 },
	101	[RTC_A] = { 6, 1<<5 },
	102	[RTC_T] = { 7, 1<<4 },
	103	[SDCARD] = { 8, 1<<7 },
	104	[EXT] = { 11, 1<<0 },
	105	[TP] = { 12, 1<<15 },
	106	};
	107
c227f099	108	static void update_irl(r2d_fpga_t *fpga)
d47ede60 AZ	109	{
	110	int i, irl = 15;
	111	for (i = 0; i < NR_IRQS; i++)
	112	if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
	113	if (irqtab[i].irl < irl)
	114	irl = irqtab[i].irl;
	115	qemu_set_irq(fpga->irl, irl ^ 15);
	116	}
	117
	118	static void r2d_fpga_irq_set(void *opaque, int n, int level)
	119	{
c227f099	120	r2d_fpga_t *fpga = opaque;
d47ede60 AZ	121	if (level)
	122	fpga->irlmon \|= irqtab[n].msk;
	123	else
	124	fpga->irlmon &= ~irqtab[n].msk;
	125	update_irl(fpga);
	126	}
	127
c227f099	128	static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
b319feb7	129	{
c227f099	130	r2d_fpga_t *s = opaque;
b319feb7	131
b319feb7	132	switch (addr) {
d47ede60 AZ	133	case PA_IRLMSK:
d47ede60 AZ	134	return s->irlmsk;
b319feb7 AJ	135	case PA_OUTPORT:
	136	return s->outport;
	137	case PA_POWOFF:
37cc0b44	138	return 0x00;
b319feb7 AJ	139	case PA_VERREG:
	140	return 0x10;
	141	}
	142
	143	return 0;
	144	}
	145
	146	static void
c227f099	147	r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
b319feb7	148	{
c227f099	149	r2d_fpga_t *s = opaque;
b319feb7	150
b319feb7	151	switch (addr) {
d47ede60 AZ	152	case PA_IRLMSK:
	153	s->irlmsk = value;
	154	update_irl(s);
	155	break;
b319feb7 AJ	156	case PA_OUTPORT:
	157	s->outport = value;
	158	break;
	159	case PA_POWOFF:
37cc0b44 AJ	160	if (value & 1) {
	161	qemu_system_shutdown_request();
	162	}
	163	break;
b319feb7 AJ	164	case PA_VERREG:
	165	/* Discard writes */
	166	break;
	167	}
	168	}
	169
d60efc6b	170	static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
b319feb7 AJ	171	r2d_fpga_read,
b319feb7 AJ	172	r2d_fpga_read,
b2463a64	173	NULL,
b319feb7 AJ	174	};
b319feb7 AJ	175
d60efc6b	176	static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
b319feb7 AJ	177	r2d_fpga_write,
b319feb7 AJ	178	r2d_fpga_write,
b2463a64	179	NULL,
b319feb7 AJ	180	};
b319feb7 AJ	181
c227f099	182	static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
b319feb7 AJ	183	{
b319feb7 AJ	184	int iomemtype;
c227f099	185	r2d_fpga_t *s;
b319feb7	186
c227f099	187	s = qemu_mallocz(sizeof(r2d_fpga_t));
d47ede60 AZ	188
d47ede60 AZ	189	s->irl = irl;
b319feb7	190
1eed09cb	191	iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
2507c12a AG	192	r2d_fpga_writefn, s,
2507c12a AG	193	DEVICE_NATIVE_ENDIAN);
b319feb7	194	cpu_register_physical_memory(base, 0x40, iomemtype);
d47ede60	195	return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
b319feb7 AJ	196	}
b319feb7 AJ	197
4f6493ff AJ	198	typedef struct ResetData {
	199	CPUState *env;
	200	uint32_t vector;
	201	} ResetData;
	202
	203	static void main_cpu_reset(void *opaque)
	204	{
	205	ResetData s = (ResetData )opaque;
	206	CPUState *env = s->env;
	207
	208	cpu_reset(env);
	209	env->pc = s->vector;
	210	}
	211
73f19035 AJ	212	static struct __attribute__((__packed__))
	213	{
	214	int mount_root_rdonly;
	215	int ramdisk_flags;
	216	int orig_root_dev;
	217	int loader_type;
	218	int initrd_start;
	219	int initrd_size;
	220
	221	char pad[232];
	222
	223	char kernel_cmdline[256];
	224	} boot_params;
	225
c227f099	226	static void r2d_init(ram_addr_t ram_size,
3023f332	227	const char *boot_device,
0d78f544 TS	228	const char kernel_filename, const char kernel_cmdline,
	229	const char initrd_filename, const char cpu_model)
	230	{
0d78f544	231	CPUState *env;
4f6493ff	232	ResetData *reset_info;
0d78f544	233	struct SH7750State *s;
c227f099	234	ram_addr_t sdram_addr;
d47ede60	235	qemu_irq *irq;
751c6a17	236	DriveInfo *dinfo;
c2f01775	237	int i;
0d78f544	238
aaed909a	239	if (!cpu_model)
0fd3ca30	240	cpu_model = "SH7751R";
aaed909a FB	241
	242	env = cpu_init(cpu_model);
	243	if (!env) {
	244	fprintf(stderr, "Unable to find CPU definition\n");
	245	exit(1);
	246	}
4f6493ff AJ	247	reset_info = qemu_mallocz(sizeof(ResetData));
	248	reset_info->env = env;
	249	reset_info->vector = env->pc;
	250	qemu_register_reset(main_cpu_reset, reset_info);
0d78f544 TS	251
0d78f544 TS	252	/* Allocate memory space */
1724f049	253	sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
ffd39257	254	cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
0d78f544 TS	255	/* Register peripherals */
0d78f544 TS	256	s = sh7750_init(env);
d47ede60	257	irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
cf154394 AJ	258	sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB],
cf154394 AJ	259	irq[PCI_INTC], irq[PCI_INTD], NULL);
d47ede60	260
ac611340	261	sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
a4a771c0 AZ	262
a4a771c0 AZ	263	/* onboard CF (True IDE mode, Master only). */
612b2bd0 AJ	264	dinfo = drive_get(IF_IDE, 0, 0);
	265	mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
	266	dinfo, NULL);
a4a771c0	267
56839a19	268	/* onboard flash memory */
45e7e4bc	269	dinfo = drive_get(IF_PFLASH, 0, 0);
1724f049	270	pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
612b2bd0 AJ	271	dinfo ? dinfo->bdrv : NULL, (16 * 1024),
	272	FLASH_SIZE >> 16,
	273	1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
	274	0x555, 0x2aa, 0);
56839a19	275
c2f01775	276	/* NIC: rtl8139 on-board, and 2 slots. */
ab2da564	277	for (i = 0; i < nb_nics; i++)
07caea31	278	pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
c2f01775	279
9caa3ec1 AJ	280	/* USB keyboard */
	281	usbdevice_create("keyboard");
	282
0d78f544	283	/* Todo: register on board registers */
73f19035 AJ	284	memset(&boot_params, 0, sizeof(boot_params));
73f19035 AJ	285
e8afa065	286	if (kernel_filename) {
73f19035 AJ	287	int kernel_size;
	288
	289	kernel_size = load_image_targphys(kernel_filename,
	290	SDRAM_BASE + LINUX_LOAD_OFFSET,
	291	INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
	292	if (kernel_size < 0) {
	293	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
	294	exit(1);
	295	}
	296
	297	/* initialization which should be done by firmware */
	298	stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
	299	stw_phys(SH7750_BCR2, 3<<(32)); / cs3 32bit */
4f6493ff	300	reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) \| 0xa0000000; /* Start from P2 area */
0d78f544	301	}
73f19035 AJ	302
	303	if (initrd_filename) {
	304	int initrd_size;
	305
	306	initrd_size = load_image_targphys(initrd_filename,
	307	SDRAM_BASE + INITRD_LOAD_OFFSET,
	308	SDRAM_SIZE - INITRD_LOAD_OFFSET);
	309
	310	if (initrd_size < 0) {
	311	fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
	312	exit(1);
	313	}
	314
	315	/* initialization which should be done by firmware */
	316	boot_params.loader_type = 1;
	317	boot_params.initrd_start = INITRD_LOAD_OFFSET;
	318	boot_params.initrd_size = initrd_size;
	319	}
	320
	321	if (kernel_cmdline) {
	322	strncpy(boot_params.kernel_cmdline, kernel_cmdline,
	323	sizeof(boot_params.kernel_cmdline));
	324	}
	325
	326	rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
	327	SDRAM_BASE + BOOT_PARAMS_OFFSET);
0d78f544 TS	328	}
0d78f544 TS	329
f80f9ec9	330	static QEMUMachine r2d_machine = {
4b32e168 AL	331	.name = "r2d",
	332	.desc = "r2d-plus board",
	333	.init = r2d_init,
0d78f544	334	};
f80f9ec9 AL	335
	336	static void r2d_machine_init(void)
	337	{
	338	qemu_register_machine(&r2d_machine);
	339	}
	340
	341	machine_init(r2d_machine_init);