]> git.proxmox.com Git - qemu.git/blame - hw/r2d.c
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[qemu.git] / hw / r2d.c
CommitLineData
0d78f544
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1/*
2 * Renesas SH7751R R2D-PLUS emulation
3 *
4 * Copyright (c) 2007 Magnus Damm
b319feb7 5 * Copyright (c) 2008 Paul Mundt
0d78f544
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6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
87ecb68b
PB
26#include "hw.h"
27#include "sh.h"
ffd39257 28#include "devices.h"
87ecb68b
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29#include "sysemu.h"
30#include "boards.h"
c2f01775 31#include "pci.h"
18e08a55 32#include "sh_pci.h"
c2f01775
AZ
33#include "net.h"
34#include "sh7750_regs.h"
3d2bf4a1 35#include "ide.h"
ca20cf32 36#include "loader.h"
9caa3ec1 37#include "usb.h"
56839a19 38#include "flash.h"
2446333c 39#include "blockdev.h"
56839a19
AJ
40
41#define FLASH_BASE 0x00000000
42#define FLASH_SIZE 0x02000000
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43
44#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
45#define SDRAM_SIZE 0x04000000
46
ffd39257
BS
47#define SM501_VRAM_SIZE 0x800000
48
73f19035 49#define BOOT_PARAMS_OFFSET 0x0010000
e8afa065 50/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
73f19035
AJ
51#define LINUX_LOAD_OFFSET 0x0800000
52#define INITRD_LOAD_OFFSET 0x1800000
e8afa065 53
d47ede60 54#define PA_IRLMSK 0x00
b319feb7
AJ
55#define PA_POWOFF 0x30
56#define PA_VERREG 0x32
57#define PA_OUTPORT 0x36
58
59typedef struct {
b319feb7 60 uint16_t bcr;
d47ede60 61 uint16_t irlmsk;
b319feb7
AJ
62 uint16_t irlmon;
63 uint16_t cfctl;
64 uint16_t cfpow;
65 uint16_t dispctl;
66 uint16_t sdmpow;
67 uint16_t rtcce;
68 uint16_t pcicd;
69 uint16_t voyagerrts;
70 uint16_t cfrst;
71 uint16_t admrts;
72 uint16_t extrst;
73 uint16_t cfcdintclr;
74 uint16_t keyctlclr;
75 uint16_t pad0;
76 uint16_t pad1;
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77 uint16_t verreg;
78 uint16_t inport;
79 uint16_t outport;
80 uint16_t bverreg;
d47ede60
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81
82/* output pin */
83 qemu_irq irl;
c227f099 84} r2d_fpga_t;
b319feb7 85
d47ede60
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86enum r2d_fpga_irq {
87 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
88 SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
89 NR_IRQS
90};
91
92static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
93 [CF_IDE] = { 1, 1<<9 },
94 [CF_CD] = { 2, 1<<8 },
95 [PCI_INTA] = { 9, 1<<14 },
96 [PCI_INTB] = { 10, 1<<13 },
97 [PCI_INTC] = { 3, 1<<12 },
98 [PCI_INTD] = { 0, 1<<11 },
99 [SM501] = { 4, 1<<10 },
100 [KEY] = { 5, 1<<6 },
101 [RTC_A] = { 6, 1<<5 },
102 [RTC_T] = { 7, 1<<4 },
103 [SDCARD] = { 8, 1<<7 },
104 [EXT] = { 11, 1<<0 },
105 [TP] = { 12, 1<<15 },
106};
107
c227f099 108static void update_irl(r2d_fpga_t *fpga)
d47ede60
AZ
109{
110 int i, irl = 15;
111 for (i = 0; i < NR_IRQS; i++)
112 if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
113 if (irqtab[i].irl < irl)
114 irl = irqtab[i].irl;
115 qemu_set_irq(fpga->irl, irl ^ 15);
116}
117
118static void r2d_fpga_irq_set(void *opaque, int n, int level)
119{
c227f099 120 r2d_fpga_t *fpga = opaque;
d47ede60
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121 if (level)
122 fpga->irlmon |= irqtab[n].msk;
123 else
124 fpga->irlmon &= ~irqtab[n].msk;
125 update_irl(fpga);
126}
127
c227f099 128static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
b319feb7 129{
c227f099 130 r2d_fpga_t *s = opaque;
b319feb7 131
b319feb7 132 switch (addr) {
d47ede60
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133 case PA_IRLMSK:
134 return s->irlmsk;
b319feb7
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135 case PA_OUTPORT:
136 return s->outport;
137 case PA_POWOFF:
37cc0b44 138 return 0x00;
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139 case PA_VERREG:
140 return 0x10;
141 }
142
143 return 0;
144}
145
146static void
c227f099 147r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
b319feb7 148{
c227f099 149 r2d_fpga_t *s = opaque;
b319feb7 150
b319feb7 151 switch (addr) {
d47ede60
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152 case PA_IRLMSK:
153 s->irlmsk = value;
154 update_irl(s);
155 break;
b319feb7
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156 case PA_OUTPORT:
157 s->outport = value;
158 break;
159 case PA_POWOFF:
37cc0b44
AJ
160 if (value & 1) {
161 qemu_system_shutdown_request();
162 }
163 break;
b319feb7
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164 case PA_VERREG:
165 /* Discard writes */
166 break;
167 }
168}
169
d60efc6b 170static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
b319feb7
AJ
171 r2d_fpga_read,
172 r2d_fpga_read,
b2463a64 173 NULL,
b319feb7
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174};
175
d60efc6b 176static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
b319feb7
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177 r2d_fpga_write,
178 r2d_fpga_write,
b2463a64 179 NULL,
b319feb7
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180};
181
c227f099 182static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
b319feb7
AJ
183{
184 int iomemtype;
c227f099 185 r2d_fpga_t *s;
b319feb7 186
c227f099 187 s = qemu_mallocz(sizeof(r2d_fpga_t));
d47ede60
AZ
188
189 s->irl = irl;
b319feb7 190
1eed09cb 191 iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
b319feb7
AJ
192 r2d_fpga_writefn, s);
193 cpu_register_physical_memory(base, 0x40, iomemtype);
d47ede60 194 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
b319feb7
AJ
195}
196
5d4e84c8 197static void r2d_pci_set_irq(void *opaque, int n, int l)
c2f01775 198{
5d4e84c8
JQ
199 qemu_irq *p = opaque;
200
c2f01775
AZ
201 qemu_set_irq(p[n], l);
202}
203
204static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
205{
206 const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
207 return intx[d->devfn >> 3];
208}
209
73f19035
AJ
210static struct __attribute__((__packed__))
211{
212 int mount_root_rdonly;
213 int ramdisk_flags;
214 int orig_root_dev;
215 int loader_type;
216 int initrd_start;
217 int initrd_size;
218
219 char pad[232];
220
221 char kernel_cmdline[256];
222} boot_params;
223
c227f099 224static void r2d_init(ram_addr_t ram_size,
3023f332 225 const char *boot_device,
0d78f544
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226 const char *kernel_filename, const char *kernel_cmdline,
227 const char *initrd_filename, const char *cpu_model)
228{
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229 CPUState *env;
230 struct SH7750State *s;
c227f099 231 ram_addr_t sdram_addr;
d47ede60 232 qemu_irq *irq;
751c6a17 233 DriveInfo *dinfo;
c2f01775 234 int i;
0d78f544 235
aaed909a 236 if (!cpu_model)
0fd3ca30 237 cpu_model = "SH7751R";
aaed909a
FB
238
239 env = cpu_init(cpu_model);
240 if (!env) {
241 fprintf(stderr, "Unable to find CPU definition\n");
242 exit(1);
243 }
0d78f544
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244
245 /* Allocate memory space */
1724f049 246 sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
ffd39257 247 cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
0d78f544
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248 /* Register peripherals */
249 s = sh7750_init(env);
d47ede60 250 irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
a303f9e3 251 sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
d47ede60 252
ac611340 253 sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
a4a771c0
AZ
254
255 /* onboard CF (True IDE mode, Master only). */
612b2bd0
AJ
256 dinfo = drive_get(IF_IDE, 0, 0);
257 mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
258 dinfo, NULL);
a4a771c0 259
56839a19 260 /* onboard flash memory */
45e7e4bc 261 dinfo = drive_get(IF_PFLASH, 0, 0);
1724f049 262 pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
612b2bd0
AJ
263 dinfo ? dinfo->bdrv : NULL, (16 * 1024),
264 FLASH_SIZE >> 16,
265 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
266 0x555, 0x2aa, 0);
56839a19 267
c2f01775 268 /* NIC: rtl8139 on-board, and 2 slots. */
ab2da564 269 for (i = 0; i < nb_nics; i++)
07caea31 270 pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
c2f01775 271
9caa3ec1
AJ
272 /* USB keyboard */
273 usbdevice_create("keyboard");
274
0d78f544 275 /* Todo: register on board registers */
73f19035
AJ
276 memset(&boot_params, 0, sizeof(boot_params));
277
e8afa065 278 if (kernel_filename) {
73f19035
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279 int kernel_size;
280
281 kernel_size = load_image_targphys(kernel_filename,
282 SDRAM_BASE + LINUX_LOAD_OFFSET,
283 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
284 if (kernel_size < 0) {
285 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
286 exit(1);
287 }
288
289 /* initialization which should be done by firmware */
290 stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
291 stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
292 env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
0d78f544 293 }
73f19035
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294
295 if (initrd_filename) {
296 int initrd_size;
297
298 initrd_size = load_image_targphys(initrd_filename,
299 SDRAM_BASE + INITRD_LOAD_OFFSET,
300 SDRAM_SIZE - INITRD_LOAD_OFFSET);
301
302 if (initrd_size < 0) {
303 fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
304 exit(1);
305 }
306
307 /* initialization which should be done by firmware */
308 boot_params.loader_type = 1;
309 boot_params.initrd_start = INITRD_LOAD_OFFSET;
310 boot_params.initrd_size = initrd_size;
311 }
312
313 if (kernel_cmdline) {
314 strncpy(boot_params.kernel_cmdline, kernel_cmdline,
315 sizeof(boot_params.kernel_cmdline));
316 }
317
318 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
319 SDRAM_BASE + BOOT_PARAMS_OFFSET);
0d78f544
TS
320}
321
f80f9ec9 322static QEMUMachine r2d_machine = {
4b32e168
AL
323 .name = "r2d",
324 .desc = "r2d-plus board",
325 .init = r2d_init,
0d78f544 326};
f80f9ec9
AL
327
328static void r2d_machine_init(void)
329{
330 qemu_register_machine(&r2d_machine);
331}
332
333machine_init(r2d_machine_init);