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ef6d4ccd
YS
1/*
2 * QEMU paravirtual RDMA - Generic RDMA backend
3 *
4 * Copyright (C) 2018 Oracle
5 * Copyright (C) 2018 Red Hat Inc
6 *
7 * Authors:
8 * Yuval Shaia <yuval.shaia@oracle.com>
9 * Marcel Apfelbaum <marcel@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 *
14 */
15
0efc9511 16#include "qemu/osdep.h"
2b05705d 17#include "sysemu/sysemu.h"
0efc9511 18#include "qapi/error.h"
605ec166
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19#include "qapi/qmp/qlist.h"
20#include "qapi/qmp/qnum.h"
2b05705d 21#include "qapi/qapi-events-rdma.h"
ef6d4ccd
YS
22
23#include <infiniband/verbs.h>
605ec166
YS
24#include <infiniband/umad_types.h>
25#include <infiniband/umad.h>
26#include <rdma/rdma_user_cm.h>
ef6d4ccd 27
2b05705d 28#include "contrib/rdmacm-mux/rdmacm-mux.h"
ef6d4ccd
YS
29#include "trace.h"
30#include "rdma_utils.h"
31#include "rdma_rm.h"
32#include "rdma_backend.h"
33
ef6d4ccd 34#define THR_NAME_LEN 16
75152227 35#define THR_POLL_TO 5000
ef6d4ccd 36
605ec166
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37#define MAD_HDR_SIZE sizeof(struct ibv_grh)
38
ef6d4ccd 39typedef struct BackendCtx {
ef6d4ccd 40 void *up_ctx;
605ec166 41 struct ibv_sge sge; /* Used to save MAD recv buffer */
ef6d4ccd
YS
42} BackendCtx;
43
605ec166
YS
44struct backend_umad {
45 struct ib_user_mad hdr;
46 char mad[RDMA_MAX_PRIVATE_DATA];
47};
48
eaac0100 49static void (*comp_handler)(void *ctx, struct ibv_wc *wc);
ef6d4ccd 50
eaac0100 51static void dummy_comp_handler(void *ctx, struct ibv_wc *wc)
ef6d4ccd 52{
4d71b38a 53 rdma_error_report("No completion handler is registered");
ef6d4ccd
YS
54}
55
eaac0100
YS
56static inline void complete_work(enum ibv_wc_status status, uint32_t vendor_err,
57 void *ctx)
58{
59 struct ibv_wc wc = {0};
60
61 wc.status = status;
62 wc.vendor_err = vendor_err;
63
64 comp_handler(ctx, &wc);
65}
66
4d71b38a 67static void rdma_poll_cq(RdmaDeviceResources *rdma_dev_res, struct ibv_cq *ibcq)
ef6d4ccd
YS
68{
69 int i, ne;
70 BackendCtx *bctx;
71 struct ibv_wc wc[2];
72
ef6d4ccd
YS
73 do {
74 ne = ibv_poll_cq(ibcq, ARRAY_SIZE(wc), wc);
75
4d71b38a 76 trace_rdma_poll_cq(ne, ibcq);
ef6d4ccd
YS
77
78 for (i = 0; i < ne; i++) {
ef6d4ccd
YS
79 bctx = rdma_rm_get_cqe_ctx(rdma_dev_res, wc[i].wr_id);
80 if (unlikely(!bctx)) {
4d71b38a
YS
81 rdma_error_report("No matching ctx for req %"PRId64,
82 wc[i].wr_id);
ef6d4ccd
YS
83 continue;
84 }
ef6d4ccd 85
eaac0100 86 comp_handler(bctx->up_ctx, &wc[i]);
ef6d4ccd
YS
87
88 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, wc[i].wr_id);
89 g_free(bctx);
90 }
91 } while (ne > 0);
92
93 if (ne < 0) {
4d71b38a 94 rdma_error_report("ibv_poll_cq fail, rc=%d, errno=%d", ne, errno);
ef6d4ccd
YS
95 }
96}
97
98static void *comp_handler_thread(void *arg)
99{
100 RdmaBackendDev *backend_dev = (RdmaBackendDev *)arg;
101 int rc;
102 struct ibv_cq *ev_cq;
103 void *ev_ctx;
75152227
YS
104 int flags;
105 GPollFD pfds[1];
106
107 /* Change to non-blocking mode */
108 flags = fcntl(backend_dev->channel->fd, F_GETFL);
109 rc = fcntl(backend_dev->channel->fd, F_SETFL, flags | O_NONBLOCK);
110 if (rc < 0) {
4d71b38a 111 rdma_error_report("Failed to change backend channel FD to non-blocking");
75152227
YS
112 return NULL;
113 }
ef6d4ccd 114
75152227
YS
115 pfds[0].fd = backend_dev->channel->fd;
116 pfds[0].events = G_IO_IN | G_IO_HUP | G_IO_ERR;
117
118 backend_dev->comp_thread.is_running = true;
119
ef6d4ccd 120 while (backend_dev->comp_thread.run) {
75152227
YS
121 do {
122 rc = qemu_poll_ns(pfds, 1, THR_POLL_TO * (int64_t)SCALE_MS);
123 } while (!rc && backend_dev->comp_thread.run);
124
125 if (backend_dev->comp_thread.run) {
75152227 126 rc = ibv_get_cq_event(backend_dev->channel, &ev_cq, &ev_ctx);
75152227 127 if (unlikely(rc)) {
4d71b38a
YS
128 rdma_error_report("ibv_get_cq_event fail, rc=%d, errno=%d", rc,
129 errno);
75152227
YS
130 continue;
131 }
ef6d4ccd 132
75152227
YS
133 rc = ibv_req_notify_cq(ev_cq, 0);
134 if (unlikely(rc)) {
4d71b38a
YS
135 rdma_error_report("ibv_req_notify_cq fail, rc=%d, errno=%d", rc,
136 errno);
75152227 137 }
ef6d4ccd 138
4d71b38a 139 rdma_poll_cq(backend_dev->rdma_dev_res, ev_cq);
ef6d4ccd 140
75152227
YS
141 ibv_ack_cq_events(ev_cq, 1);
142 }
ef6d4ccd
YS
143 }
144
ef6d4ccd
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145 /* TODO: Post cqe for all remaining buffs that were posted */
146
75152227
YS
147 backend_dev->comp_thread.is_running = false;
148
149 qemu_thread_exit(0);
150
ef6d4ccd
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151 return NULL;
152}
153
2b05705d
YS
154static inline void disable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
155{
156 atomic_set(&backend_dev->rdmacm_mux.can_receive, 0);
157}
158
159static inline void enable_rdmacm_mux_async(RdmaBackendDev *backend_dev)
160{
161 atomic_set(&backend_dev->rdmacm_mux.can_receive, sizeof(RdmaCmMuxMsg));
162}
163
164static inline int rdmacm_mux_can_process_async(RdmaBackendDev *backend_dev)
165{
166 return atomic_read(&backend_dev->rdmacm_mux.can_receive);
167}
168
4d71b38a 169static int rdmacm_mux_check_op_status(CharBackend *mad_chr_be)
2b05705d 170{
555b3d67 171 RdmaCmMuxMsg msg = {};
2b05705d
YS
172 int ret;
173
2b05705d
YS
174 ret = qemu_chr_fe_read_all(mad_chr_be, (uint8_t *)&msg, sizeof(msg));
175 if (ret != sizeof(msg)) {
4d71b38a
YS
176 rdma_error_report("Got invalid message from mux: size %d, expecting %d",
177 ret, (int)sizeof(msg));
2b05705d
YS
178 return -EIO;
179 }
180
4d71b38a
YS
181 trace_rdmacm_mux_check_op_status(msg.hdr.msg_type, msg.hdr.op_code,
182 msg.hdr.err_code);
2b05705d
YS
183
184 if (msg.hdr.msg_type != RDMACM_MUX_MSG_TYPE_RESP) {
4d71b38a 185 rdma_error_report("Got invalid message type %d", msg.hdr.msg_type);
2b05705d
YS
186 return -EIO;
187 }
188
189 if (msg.hdr.err_code != RDMACM_MUX_ERR_CODE_OK) {
4d71b38a
YS
190 rdma_error_report("Operation failed in mux, error code %d",
191 msg.hdr.err_code);
2b05705d
YS
192 return -EIO;
193 }
194
195 return 0;
196}
197
4d71b38a 198static int rdmacm_mux_send(RdmaBackendDev *backend_dev, RdmaCmMuxMsg *msg)
2b05705d
YS
199{
200 int rc = 0;
201
2b05705d 202 msg->hdr.msg_type = RDMACM_MUX_MSG_TYPE_REQ;
4d71b38a 203 trace_rdmacm_mux("send", msg->hdr.msg_type, msg->hdr.op_code);
2b05705d
YS
204 disable_rdmacm_mux_async(backend_dev);
205 rc = qemu_chr_fe_write(backend_dev->rdmacm_mux.chr_be,
206 (const uint8_t *)msg, sizeof(*msg));
207 if (rc != sizeof(*msg)) {
208 enable_rdmacm_mux_async(backend_dev);
4d71b38a 209 rdma_error_report("Failed to send request to rdmacm_mux (rc=%d)", rc);
2b05705d
YS
210 return -EIO;
211 }
212
4d71b38a 213 rc = rdmacm_mux_check_op_status(backend_dev->rdmacm_mux.chr_be);
2b05705d 214 if (rc) {
4d71b38a
YS
215 rdma_error_report("Failed to execute rdmacm_mux request %d (rc=%d)",
216 msg->hdr.op_code, rc);
2b05705d
YS
217 }
218
219 enable_rdmacm_mux_async(backend_dev);
220
221 return 0;
222}
223
292dce62 224static void stop_backend_thread(RdmaBackendThread *thread)
75152227 225{
292dce62
YS
226 thread->run = false;
227 while (thread->is_running) {
75152227
YS
228 sleep(THR_POLL_TO / SCALE_US / 2);
229 }
230}
231
232static void start_comp_thread(RdmaBackendDev *backend_dev)
233{
234 char thread_name[THR_NAME_LEN] = {0};
235
292dce62 236 stop_backend_thread(&backend_dev->comp_thread);
75152227
YS
237
238 snprintf(thread_name, sizeof(thread_name), "rdma_comp_%s",
239 ibv_get_device_name(backend_dev->ib_dev));
240 backend_dev->comp_thread.run = true;
241 qemu_thread_create(&backend_dev->comp_thread.thread, thread_name,
242 comp_handler_thread, backend_dev, QEMU_THREAD_DETACHED);
243}
244
eaac0100
YS
245void rdma_backend_register_comp_handler(void (*handler)(void *ctx,
246 struct ibv_wc *wc))
ef6d4ccd
YS
247{
248 comp_handler = handler;
249}
250
251void rdma_backend_unregister_comp_handler(void)
252{
253 rdma_backend_register_comp_handler(dummy_comp_handler);
254}
255
256int rdma_backend_query_port(RdmaBackendDev *backend_dev,
257 struct ibv_port_attr *port_attr)
258{
259 int rc;
260
261 rc = ibv_query_port(backend_dev->context, backend_dev->port_num, port_attr);
262 if (rc) {
4d71b38a 263 rdma_error_report("ibv_query_port fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
264 return -EIO;
265 }
266
267 return 0;
268}
269
270void rdma_backend_poll_cq(RdmaDeviceResources *rdma_dev_res, RdmaBackendCQ *cq)
271{
4d71b38a 272 rdma_poll_cq(rdma_dev_res, cq->ibcq);
ef6d4ccd
YS
273}
274
275static GHashTable *ah_hash;
276
277static struct ibv_ah *create_ah(RdmaBackendDev *backend_dev, struct ibv_pd *pd,
278 uint8_t sgid_idx, union ibv_gid *dgid)
279{
280 GBytes *ah_key = g_bytes_new(dgid, sizeof(*dgid));
281 struct ibv_ah *ah = g_hash_table_lookup(ah_hash, ah_key);
282
283 if (ah) {
4d71b38a
YS
284 trace_rdma_create_ah_cache_hit(be64_to_cpu(dgid->global.subnet_prefix),
285 be64_to_cpu(dgid->global.interface_id));
ef6d4ccd
YS
286 g_bytes_unref(ah_key);
287 } else {
288 struct ibv_ah_attr ah_attr = {
289 .is_global = 1,
290 .port_num = backend_dev->port_num,
291 .grh.hop_limit = 1,
292 };
293
294 ah_attr.grh.dgid = *dgid;
295 ah_attr.grh.sgid_index = sgid_idx;
296
297 ah = ibv_create_ah(pd, &ah_attr);
298 if (ah) {
299 g_hash_table_insert(ah_hash, ah_key, ah);
300 } else {
301 g_bytes_unref(ah_key);
4d71b38a
YS
302 rdma_error_report("Failed to create AH for gid <0x%" PRIx64", 0x%"PRIx64">",
303 be64_to_cpu(dgid->global.subnet_prefix),
304 be64_to_cpu(dgid->global.interface_id));
ef6d4ccd
YS
305 }
306
4d71b38a
YS
307 trace_rdma_create_ah_cache_miss(be64_to_cpu(dgid->global.subnet_prefix),
308 be64_to_cpu(dgid->global.interface_id));
ef6d4ccd
YS
309 }
310
311 return ah;
312}
313
314static void destroy_ah_hash_key(gpointer data)
315{
316 g_bytes_unref(data);
317}
318
319static void destroy_ah_hast_data(gpointer data)
320{
321 struct ibv_ah *ah = data;
322
323 ibv_destroy_ah(ah);
324}
325
326static void ah_cache_init(void)
327{
328 ah_hash = g_hash_table_new_full(g_bytes_hash, g_bytes_equal,
329 destroy_ah_hash_key, destroy_ah_hast_data);
330}
331
332static int build_host_sge_array(RdmaDeviceResources *rdma_dev_res,
333 struct ibv_sge *dsge, struct ibv_sge *ssge,
334 uint8_t num_sge)
335{
336 RdmaRmMR *mr;
337 int ssge_idx;
338
ef6d4ccd
YS
339 for (ssge_idx = 0; ssge_idx < num_sge; ssge_idx++) {
340 mr = rdma_rm_get_mr(rdma_dev_res, ssge[ssge_idx].lkey);
341 if (unlikely(!mr)) {
4d71b38a 342 rdma_error_report("Invalid lkey 0x%x", ssge[ssge_idx].lkey);
ef6d4ccd
YS
343 return VENDOR_ERR_INVLKEY | ssge[ssge_idx].lkey;
344 }
345
7f99daad 346 dsge->addr = (uintptr_t)mr->virt + ssge[ssge_idx].addr - mr->start;
ef6d4ccd
YS
347 dsge->length = ssge[ssge_idx].length;
348 dsge->lkey = rdma_backend_mr_lkey(&mr->backend_mr);
349
ef6d4ccd
YS
350 dsge++;
351 }
352
353 return 0;
354}
355
4d71b38a
YS
356static void trace_mad_message(const char *title, char *buf, int len)
357{
358 int i;
359 char *b = g_malloc0(len * 3 + 1);
360 char b1[4];
361
362 for (i = 0; i < len; i++) {
363 sprintf(b1, "%.2X ", buf[i] & 0x000000FF);
364 strcat(b, b1);
365 }
366
367 trace_rdma_mad_message(title, len, b);
368
369 g_free(b);
370}
371
2b05705d
YS
372static int mad_send(RdmaBackendDev *backend_dev, uint8_t sgid_idx,
373 union ibv_gid *sgid, struct ibv_sge *sge, uint32_t num_sge)
605ec166 374{
555b3d67 375 RdmaCmMuxMsg msg = {};
2b05705d 376 char *hdr, *data;
605ec166
YS
377 int ret;
378
605ec166
YS
379 if (num_sge != 2) {
380 return -EINVAL;
381 }
382
2b05705d
YS
383 msg.hdr.op_code = RDMACM_MUX_OP_CODE_MAD;
384 memcpy(msg.hdr.sgid.raw, sgid->raw, sizeof(msg.hdr.sgid));
605ec166 385
2b05705d 386 msg.umad_len = sge[0].length + sge[1].length;
2b05705d
YS
387
388 if (msg.umad_len > sizeof(msg.umad.mad)) {
605ec166
YS
389 return -ENOMEM;
390 }
391
2b05705d
YS
392 msg.umad.hdr.addr.qpn = htobe32(1);
393 msg.umad.hdr.addr.grh_present = 1;
2b05705d
YS
394 msg.umad.hdr.addr.gid_index = sgid_idx;
395 memcpy(msg.umad.hdr.addr.gid, sgid->raw, sizeof(msg.umad.hdr.addr.gid));
396 msg.umad.hdr.addr.hop_limit = 0xFF;
605ec166
YS
397
398 hdr = rdma_pci_dma_map(backend_dev->dev, sge[0].addr, sge[0].length);
399 if (!hdr) {
605ec166
YS
400 return -ENOMEM;
401 }
2b05705d
YS
402 data = rdma_pci_dma_map(backend_dev->dev, sge[1].addr, sge[1].length);
403 if (!data) {
605ec166
YS
404 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
405 return -ENOMEM;
406 }
407
2b05705d
YS
408 memcpy(&msg.umad.mad[0], hdr, sge[0].length);
409 memcpy(&msg.umad.mad[sge[0].length], data, sge[1].length);
605ec166 410
2b05705d 411 rdma_pci_dma_unmap(backend_dev->dev, data, sge[1].length);
605ec166
YS
412 rdma_pci_dma_unmap(backend_dev->dev, hdr, sge[0].length);
413
4d71b38a
YS
414 trace_mad_message("send", msg.umad.mad, msg.umad_len);
415
416 ret = rdmacm_mux_send(backend_dev, &msg);
2b05705d 417 if (ret) {
4d71b38a 418 rdma_error_report("Failed to send MAD to rdma_umadmux (%d)", ret);
2b05705d
YS
419 return -EIO;
420 }
605ec166 421
2b05705d 422 return 0;
605ec166
YS
423}
424
ef6d4ccd
YS
425void rdma_backend_post_send(RdmaBackendDev *backend_dev,
426 RdmaBackendQP *qp, uint8_t qp_type,
427 struct ibv_sge *sge, uint32_t num_sge,
2b05705d
YS
428 uint8_t sgid_idx, union ibv_gid *sgid,
429 union ibv_gid *dgid, uint32_t dqpn, uint32_t dqkey,
430 void *ctx)
ef6d4ccd
YS
431{
432 BackendCtx *bctx;
433 struct ibv_sge new_sge[MAX_SGE];
434 uint32_t bctx_id;
435 int rc;
436 struct ibv_send_wr wr = {0}, *bad_wr;
437
4d71b38a 438 if (!qp->ibqp) { /* This field is not initialized for QP0 and QP1 */
ef6d4ccd 439 if (qp_type == IBV_QPT_SMI) {
4d71b38a 440 rdma_error_report("Got QP0 request");
eaac0100 441 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
ef6d4ccd 442 } else if (qp_type == IBV_QPT_GSI) {
2b05705d 443 rc = mad_send(backend_dev, sgid_idx, sgid, sge, num_sge);
605ec166 444 if (rc) {
eaac0100 445 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_MAD_SEND, ctx);
605ec166 446 } else {
eaac0100 447 complete_work(IBV_WC_SUCCESS, 0, ctx);
605ec166 448 }
ef6d4ccd 449 }
ef6d4ccd
YS
450 return;
451 }
452
ef6d4ccd
YS
453 bctx = g_malloc0(sizeof(*bctx));
454 bctx->up_ctx = ctx;
ef6d4ccd
YS
455
456 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
457 if (unlikely(rc)) {
eaac0100 458 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
ef6d4ccd
YS
459 goto out_free_bctx;
460 }
461
462 rc = build_host_sge_array(backend_dev->rdma_dev_res, new_sge, sge, num_sge);
463 if (rc) {
eaac0100 464 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
ef6d4ccd
YS
465 goto out_dealloc_cqe_ctx;
466 }
467
468 if (qp_type == IBV_QPT_UD) {
2b05705d 469 wr.wr.ud.ah = create_ah(backend_dev, qp->ibpd, sgid_idx, dgid);
305bdd7a 470 if (!wr.wr.ud.ah) {
eaac0100 471 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
305bdd7a
YS
472 goto out_dealloc_cqe_ctx;
473 }
ef6d4ccd
YS
474 wr.wr.ud.remote_qpn = dqpn;
475 wr.wr.ud.remote_qkey = dqkey;
476 }
477
478 wr.num_sge = num_sge;
479 wr.opcode = IBV_WR_SEND;
480 wr.send_flags = IBV_SEND_SIGNALED;
481 wr.sg_list = new_sge;
482 wr.wr_id = bctx_id;
483
484 rc = ibv_post_send(qp->ibqp, &wr, &bad_wr);
ef6d4ccd 485 if (rc) {
4d71b38a
YS
486 rdma_error_report("ibv_post_send fail, qpn=0x%x, rc=%d, errno=%d",
487 qp->ibqp->qp_num, rc, errno);
eaac0100 488 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
ef6d4ccd
YS
489 goto out_dealloc_cqe_ctx;
490 }
491
492 return;
493
494out_dealloc_cqe_ctx:
495 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, bctx_id);
496
497out_free_bctx:
498 g_free(bctx);
499}
500
605ec166
YS
501static unsigned int save_mad_recv_buffer(RdmaBackendDev *backend_dev,
502 struct ibv_sge *sge, uint32_t num_sge,
503 void *ctx)
504{
505 BackendCtx *bctx;
506 int rc;
507 uint32_t bctx_id;
508
509 if (num_sge != 1) {
4d71b38a 510 rdma_error_report("Invalid num_sge (%d), expecting 1", num_sge);
605ec166
YS
511 return VENDOR_ERR_INV_NUM_SGE;
512 }
513
514 if (sge[0].length < RDMA_MAX_PRIVATE_DATA + sizeof(struct ibv_grh)) {
4d71b38a 515 rdma_error_report("Too small buffer for MAD");
605ec166
YS
516 return VENDOR_ERR_INV_MAD_BUFF;
517 }
518
605ec166
YS
519 bctx = g_malloc0(sizeof(*bctx));
520
521 rc = rdma_rm_alloc_cqe_ctx(backend_dev->rdma_dev_res, &bctx_id, bctx);
522 if (unlikely(rc)) {
523 g_free(bctx);
605ec166
YS
524 return VENDOR_ERR_NOMEM;
525 }
526
605ec166
YS
527 bctx->up_ctx = ctx;
528 bctx->sge = *sge;
529
b20fc795 530 rdma_protected_qlist_append_int64(&backend_dev->recv_mads_list, bctx_id);
605ec166
YS
531
532 return 0;
533}
534
ef6d4ccd
YS
535void rdma_backend_post_recv(RdmaBackendDev *backend_dev,
536 RdmaDeviceResources *rdma_dev_res,
537 RdmaBackendQP *qp, uint8_t qp_type,
538 struct ibv_sge *sge, uint32_t num_sge, void *ctx)
539{
540 BackendCtx *bctx;
541 struct ibv_sge new_sge[MAX_SGE];
542 uint32_t bctx_id;
543 int rc;
544 struct ibv_recv_wr wr = {0}, *bad_wr;
545
546 if (!qp->ibqp) { /* This field does not get initialized for QP0 and QP1 */
547 if (qp_type == IBV_QPT_SMI) {
4d71b38a 548 rdma_error_report("Got QP0 request");
eaac0100 549 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_QP0, ctx);
ef6d4ccd
YS
550 }
551 if (qp_type == IBV_QPT_GSI) {
605ec166
YS
552 rc = save_mad_recv_buffer(backend_dev, sge, num_sge, ctx);
553 if (rc) {
eaac0100 554 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
605ec166 555 }
ef6d4ccd
YS
556 }
557 return;
558 }
559
ef6d4ccd
YS
560 bctx = g_malloc0(sizeof(*bctx));
561 bctx->up_ctx = ctx;
ef6d4ccd
YS
562
563 rc = rdma_rm_alloc_cqe_ctx(rdma_dev_res, &bctx_id, bctx);
564 if (unlikely(rc)) {
eaac0100 565 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_NOMEM, ctx);
ef6d4ccd
YS
566 goto out_free_bctx;
567 }
568
569 rc = build_host_sge_array(rdma_dev_res, new_sge, sge, num_sge);
570 if (rc) {
eaac0100 571 complete_work(IBV_WC_GENERAL_ERR, rc, ctx);
ef6d4ccd
YS
572 goto out_dealloc_cqe_ctx;
573 }
574
575 wr.num_sge = num_sge;
576 wr.sg_list = new_sge;
577 wr.wr_id = bctx_id;
578 rc = ibv_post_recv(qp->ibqp, &wr, &bad_wr);
ef6d4ccd 579 if (rc) {
4d71b38a
YS
580 rdma_error_report("ibv_post_recv fail, qpn=0x%x, rc=%d, errno=%d",
581 qp->ibqp->qp_num, rc, errno);
eaac0100 582 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_FAIL_BACKEND, ctx);
ef6d4ccd
YS
583 goto out_dealloc_cqe_ctx;
584 }
585
586 return;
587
588out_dealloc_cqe_ctx:
589 rdma_rm_dealloc_cqe_ctx(rdma_dev_res, bctx_id);
590
591out_free_bctx:
592 g_free(bctx);
593}
594
595int rdma_backend_create_pd(RdmaBackendDev *backend_dev, RdmaBackendPD *pd)
596{
597 pd->ibpd = ibv_alloc_pd(backend_dev->context);
598
4d71b38a
YS
599 if (!pd->ibpd) {
600 rdma_error_report("ibv_alloc_pd fail, errno=%d", errno);
601 return -EIO;
602 }
603
604 return 0;
ef6d4ccd
YS
605}
606
607void rdma_backend_destroy_pd(RdmaBackendPD *pd)
608{
609 if (pd->ibpd) {
610 ibv_dealloc_pd(pd->ibpd);
611 }
612}
613
9bbb8d35 614int rdma_backend_create_mr(RdmaBackendMR *mr, RdmaBackendPD *pd, void *addr,
ef6d4ccd
YS
615 size_t length, int access)
616{
9bbb8d35 617 mr->ibmr = ibv_reg_mr(pd->ibpd, addr, length, access);
4d71b38a
YS
618 if (!mr->ibmr) {
619 rdma_error_report("ibv_reg_mr fail, errno=%d", errno);
620 return -EIO;
ef6d4ccd
YS
621 }
622
4d71b38a
YS
623 mr->ibpd = pd->ibpd;
624
625 return 0;
ef6d4ccd
YS
626}
627
628void rdma_backend_destroy_mr(RdmaBackendMR *mr)
629{
630 if (mr->ibmr) {
631 ibv_dereg_mr(mr->ibmr);
632 }
633}
634
635int rdma_backend_create_cq(RdmaBackendDev *backend_dev, RdmaBackendCQ *cq,
636 int cqe)
637{
638 int rc;
639
ef6d4ccd
YS
640 cq->ibcq = ibv_create_cq(backend_dev->context, cqe + 1, NULL,
641 backend_dev->channel, 0);
4d71b38a
YS
642 if (!cq->ibcq) {
643 rdma_error_report("ibv_create_cq fail, errno=%d", errno);
644 return -EIO;
645 }
ef6d4ccd 646
4d71b38a
YS
647 rc = ibv_req_notify_cq(cq->ibcq, 0);
648 if (rc) {
649 rdma_warn_report("ibv_req_notify_cq fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
650 }
651
4d71b38a
YS
652 cq->backend_dev = backend_dev;
653
654 return 0;
ef6d4ccd
YS
655}
656
657void rdma_backend_destroy_cq(RdmaBackendCQ *cq)
658{
659 if (cq->ibcq) {
660 ibv_destroy_cq(cq->ibcq);
661 }
662}
663
664int rdma_backend_create_qp(RdmaBackendQP *qp, uint8_t qp_type,
665 RdmaBackendPD *pd, RdmaBackendCQ *scq,
666 RdmaBackendCQ *rcq, uint32_t max_send_wr,
667 uint32_t max_recv_wr, uint32_t max_send_sge,
668 uint32_t max_recv_sge)
669{
670 struct ibv_qp_init_attr attr = {0};
671
672 qp->ibqp = 0;
ef6d4ccd
YS
673
674 switch (qp_type) {
675 case IBV_QPT_GSI:
ef6d4ccd
YS
676 return 0;
677
678 case IBV_QPT_RC:
679 /* fall through */
680 case IBV_QPT_UD:
681 /* do nothing */
682 break;
683
684 default:
4d71b38a 685 rdma_error_report("Unsupported QP type %d", qp_type);
ef6d4ccd
YS
686 return -EIO;
687 }
688
689 attr.qp_type = qp_type;
690 attr.send_cq = scq->ibcq;
691 attr.recv_cq = rcq->ibcq;
692 attr.cap.max_send_wr = max_send_wr;
693 attr.cap.max_recv_wr = max_recv_wr;
694 attr.cap.max_send_sge = max_send_sge;
695 attr.cap.max_recv_sge = max_recv_sge;
696
ef6d4ccd 697 qp->ibqp = ibv_create_qp(pd->ibpd, &attr);
4d71b38a
YS
698 if (!qp->ibqp) {
699 rdma_error_report("ibv_create_qp fail, errno=%d", errno);
ef6d4ccd
YS
700 return -EIO;
701 }
702
703 qp->ibpd = pd->ibpd;
704
705 /* TODO: Query QP to get max_inline_data and save it to be used in send */
706
ef6d4ccd
YS
707 return 0;
708}
709
710int rdma_backend_qp_state_init(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
711 uint8_t qp_type, uint32_t qkey)
712{
713 struct ibv_qp_attr attr = {0};
714 int rc, attr_mask;
715
ef6d4ccd
YS
716 attr_mask = IBV_QP_STATE | IBV_QP_PKEY_INDEX | IBV_QP_PORT;
717 attr.qp_state = IBV_QPS_INIT;
718 attr.pkey_index = 0;
719 attr.port_num = backend_dev->port_num;
720
721 switch (qp_type) {
722 case IBV_QPT_RC:
723 attr_mask |= IBV_QP_ACCESS_FLAGS;
4d71b38a 724 trace_rdma_backend_rc_qp_state_init(qp->ibqp->qp_num);
ef6d4ccd
YS
725 break;
726
727 case IBV_QPT_UD:
728 attr.qkey = qkey;
729 attr_mask |= IBV_QP_QKEY;
4d71b38a 730 trace_rdma_backend_ud_qp_state_init(qp->ibqp->qp_num, qkey);
ef6d4ccd
YS
731 break;
732
733 default:
4d71b38a 734 rdma_error_report("Unsupported QP type %d", qp_type);
ef6d4ccd
YS
735 return -EIO;
736 }
737
738 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
739 if (rc) {
4d71b38a 740 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
741 return -EIO;
742 }
743
744 return 0;
745}
746
747int rdma_backend_qp_state_rtr(RdmaBackendDev *backend_dev, RdmaBackendQP *qp,
2b05705d
YS
748 uint8_t qp_type, uint8_t sgid_idx,
749 union ibv_gid *dgid, uint32_t dqpn,
750 uint32_t rq_psn, uint32_t qkey, bool use_qkey)
ef6d4ccd
YS
751{
752 struct ibv_qp_attr attr = {0};
753 union ibv_gid ibv_gid = {
754 .global.interface_id = dgid->global.interface_id,
755 .global.subnet_prefix = dgid->global.subnet_prefix
756 };
757 int rc, attr_mask;
758
759 attr.qp_state = IBV_QPS_RTR;
760 attr_mask = IBV_QP_STATE;
761
2b05705d
YS
762 qp->sgid_idx = sgid_idx;
763
ef6d4ccd
YS
764 switch (qp_type) {
765 case IBV_QPT_RC:
ef6d4ccd
YS
766 attr.path_mtu = IBV_MTU_1024;
767 attr.dest_qp_num = dqpn;
768 attr.max_dest_rd_atomic = 1;
769 attr.min_rnr_timer = 12;
770 attr.ah_attr.port_num = backend_dev->port_num;
771 attr.ah_attr.is_global = 1;
772 attr.ah_attr.grh.hop_limit = 1;
773 attr.ah_attr.grh.dgid = ibv_gid;
2b05705d 774 attr.ah_attr.grh.sgid_index = qp->sgid_idx;
ef6d4ccd
YS
775 attr.rq_psn = rq_psn;
776
777 attr_mask |= IBV_QP_AV | IBV_QP_PATH_MTU | IBV_QP_DEST_QPN |
778 IBV_QP_RQ_PSN | IBV_QP_MAX_DEST_RD_ATOMIC |
779 IBV_QP_MIN_RNR_TIMER;
4d71b38a
YS
780
781 trace_rdma_backend_rc_qp_state_rtr(qp->ibqp->qp_num,
782 be64_to_cpu(ibv_gid.global.
783 subnet_prefix),
784 be64_to_cpu(ibv_gid.global.
785 interface_id),
786 qp->sgid_idx, dqpn, rq_psn);
ef6d4ccd
YS
787 break;
788
789 case IBV_QPT_UD:
790 if (use_qkey) {
ef6d4ccd
YS
791 attr.qkey = qkey;
792 attr_mask |= IBV_QP_QKEY;
793 }
4d71b38a
YS
794 trace_rdma_backend_ud_qp_state_rtr(qp->ibqp->qp_num, use_qkey ? qkey :
795 0);
ef6d4ccd
YS
796 break;
797 }
798
799 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
800 if (rc) {
4d71b38a 801 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
802 return -EIO;
803 }
804
805 return 0;
806}
807
808int rdma_backend_qp_state_rts(RdmaBackendQP *qp, uint8_t qp_type,
809 uint32_t sq_psn, uint32_t qkey, bool use_qkey)
810{
811 struct ibv_qp_attr attr = {0};
812 int rc, attr_mask;
813
ef6d4ccd
YS
814 attr.qp_state = IBV_QPS_RTS;
815 attr.sq_psn = sq_psn;
816 attr_mask = IBV_QP_STATE | IBV_QP_SQ_PSN;
817
818 switch (qp_type) {
819 case IBV_QPT_RC:
820 attr.timeout = 14;
821 attr.retry_cnt = 7;
822 attr.rnr_retry = 7;
823 attr.max_rd_atomic = 1;
824
825 attr_mask |= IBV_QP_TIMEOUT | IBV_QP_RETRY_CNT | IBV_QP_RNR_RETRY |
826 IBV_QP_MAX_QP_RD_ATOMIC;
4d71b38a 827 trace_rdma_backend_rc_qp_state_rts(qp->ibqp->qp_num, sq_psn);
ef6d4ccd
YS
828 break;
829
830 case IBV_QPT_UD:
831 if (use_qkey) {
ef6d4ccd
YS
832 attr.qkey = qkey;
833 attr_mask |= IBV_QP_QKEY;
834 }
4d71b38a
YS
835 trace_rdma_backend_ud_qp_state_rts(qp->ibqp->qp_num, sq_psn,
836 use_qkey ? qkey : 0);
ef6d4ccd
YS
837 break;
838 }
839
840 rc = ibv_modify_qp(qp->ibqp, &attr, attr_mask);
841 if (rc) {
4d71b38a 842 rdma_error_report("ibv_modify_qp fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
843 return -EIO;
844 }
845
846 return 0;
847}
848
c99f2174
YS
849int rdma_backend_query_qp(RdmaBackendQP *qp, struct ibv_qp_attr *attr,
850 int attr_mask, struct ibv_qp_init_attr *init_attr)
851{
852 if (!qp->ibqp) {
c99f2174
YS
853 attr->qp_state = IBV_QPS_RTS;
854 return 0;
855 }
856
857 return ibv_query_qp(qp->ibqp, attr, attr_mask, init_attr);
858}
859
ef6d4ccd
YS
860void rdma_backend_destroy_qp(RdmaBackendQP *qp)
861{
862 if (qp->ibqp) {
863 ibv_destroy_qp(qp->ibqp);
864 }
865}
866
867#define CHK_ATTR(req, dev, member, fmt) ({ \
4d71b38a 868 trace_rdma_check_dev_attr(#member, dev.member, req->member); \
ef6d4ccd 869 if (req->member > dev.member) { \
4d71b38a
YS
870 rdma_warn_report("%s = "fmt" is higher than host device capability "fmt, \
871 #member, req->member, dev.member); \
ef6d4ccd
YS
872 req->member = dev.member; \
873 } \
4d71b38a 874})
ef6d4ccd
YS
875
876static int init_device_caps(RdmaBackendDev *backend_dev,
877 struct ibv_device_attr *dev_attr)
878{
732d948c 879 struct ibv_device_attr bk_dev_attr;
4d71b38a 880 int rc;
732d948c 881
4d71b38a
YS
882 rc = ibv_query_device(backend_dev->context, &bk_dev_attr);
883 if (rc) {
884 rdma_error_report("ibv_query_device fail, rc=%d, errno=%d", rc, errno);
ef6d4ccd
YS
885 return -EIO;
886 }
887
ffef4775
YS
888 dev_attr->max_sge = MAX_SGE;
889
732d948c
YS
890 CHK_ATTR(dev_attr, bk_dev_attr, max_mr_size, "%" PRId64);
891 CHK_ATTR(dev_attr, bk_dev_attr, max_qp, "%d");
892 CHK_ATTR(dev_attr, bk_dev_attr, max_sge, "%d");
732d948c 893 CHK_ATTR(dev_attr, bk_dev_attr, max_cq, "%d");
732d948c
YS
894 CHK_ATTR(dev_attr, bk_dev_attr, max_mr, "%d");
895 CHK_ATTR(dev_attr, bk_dev_attr, max_pd, "%d");
896 CHK_ATTR(dev_attr, bk_dev_attr, max_qp_rd_atom, "%d");
897 CHK_ATTR(dev_attr, bk_dev_attr, max_qp_init_rd_atom, "%d");
898 CHK_ATTR(dev_attr, bk_dev_attr, max_ah, "%d");
ef6d4ccd
YS
899
900 return 0;
901}
902
605ec166
YS
903static inline void build_mad_hdr(struct ibv_grh *grh, union ibv_gid *sgid,
904 union ibv_gid *my_gid, int paylen)
905{
906 grh->paylen = htons(paylen);
907 grh->sgid = *sgid;
908 grh->dgid = *my_gid;
605ec166
YS
909}
910
2b05705d
YS
911static void process_incoming_mad_req(RdmaBackendDev *backend_dev,
912 RdmaCmMuxMsg *msg)
605ec166 913{
605ec166
YS
914 unsigned long cqe_ctx_id;
915 BackendCtx *bctx;
916 char *mad;
605ec166 917
4d71b38a 918 trace_mad_message("recv", msg->umad.mad, msg->umad_len);
605ec166 919
b20fc795
YS
920 cqe_ctx_id = rdma_protected_qlist_pop_int64(&backend_dev->recv_mads_list);
921 if (cqe_ctx_id == -ENOENT) {
4d71b38a 922 rdma_warn_report("No more free MADs buffers, waiting for a while");
605ec166
YS
923 sleep(THR_POLL_TO);
924 return;
925 }
926
605ec166
YS
927 bctx = rdma_rm_get_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
928 if (unlikely(!bctx)) {
4d71b38a 929 rdma_error_report("No matching ctx for req %ld", cqe_ctx_id);
605ec166
YS
930 return;
931 }
932
605ec166
YS
933 mad = rdma_pci_dma_map(backend_dev->dev, bctx->sge.addr,
934 bctx->sge.length);
2b05705d 935 if (!mad || bctx->sge.length < msg->umad_len + MAD_HDR_SIZE) {
eaac0100
YS
936 complete_work(IBV_WC_GENERAL_ERR, VENDOR_ERR_INV_MAD_BUFF,
937 bctx->up_ctx);
605ec166 938 } else {
eaac0100 939 struct ibv_wc wc = {0};
605ec166
YS
940 memset(mad, 0, bctx->sge.length);
941 build_mad_hdr((struct ibv_grh *)mad,
2b05705d
YS
942 (union ibv_gid *)&msg->umad.hdr.addr.gid, &msg->hdr.sgid,
943 msg->umad_len);
944 memcpy(&mad[MAD_HDR_SIZE], msg->umad.mad, msg->umad_len);
605ec166
YS
945 rdma_pci_dma_unmap(backend_dev->dev, mad, bctx->sge.length);
946
eaac0100
YS
947 wc.byte_len = msg->umad_len;
948 wc.status = IBV_WC_SUCCESS;
949 wc.wc_flags = IBV_WC_GRH;
950 comp_handler(bctx->up_ctx, &wc);
605ec166
YS
951 }
952
953 g_free(bctx);
954 rdma_rm_dealloc_cqe_ctx(backend_dev->rdma_dev_res, cqe_ctx_id);
955}
956
2b05705d 957static inline int rdmacm_mux_can_receive(void *opaque)
605ec166 958{
2b05705d 959 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
605ec166 960
2b05705d
YS
961 return rdmacm_mux_can_process_async(backend_dev);
962}
963
964static void rdmacm_mux_read(void *opaque, const uint8_t *buf, int size)
965{
966 RdmaBackendDev *backend_dev = (RdmaBackendDev *)opaque;
967 RdmaCmMuxMsg *msg = (RdmaCmMuxMsg *)buf;
968
4d71b38a 969 trace_rdmacm_mux("read", msg->hdr.msg_type, msg->hdr.op_code);
2b05705d
YS
970
971 if (msg->hdr.msg_type != RDMACM_MUX_MSG_TYPE_REQ &&
972 msg->hdr.op_code != RDMACM_MUX_OP_CODE_MAD) {
4d71b38a 973 rdma_error_report("Error: Not a MAD request, skipping");
2b05705d 974 return;
605ec166 975 }
2b05705d
YS
976 process_incoming_mad_req(backend_dev, msg);
977}
978
979static int mad_init(RdmaBackendDev *backend_dev, CharBackend *mad_chr_be)
980{
981 int ret;
605ec166 982
2b05705d 983 backend_dev->rdmacm_mux.chr_be = mad_chr_be;
605ec166 984
2b05705d
YS
985 ret = qemu_chr_fe_backend_connected(backend_dev->rdmacm_mux.chr_be);
986 if (!ret) {
4d71b38a 987 rdma_error_report("Missing chardev for MAD multiplexer");
2b05705d 988 return -EIO;
605ec166
YS
989 }
990
b20fc795 991 rdma_protected_qlist_init(&backend_dev->recv_mads_list);
605ec166 992
2b05705d
YS
993 enable_rdmacm_mux_async(backend_dev);
994
995 qemu_chr_fe_set_handlers(backend_dev->rdmacm_mux.chr_be,
996 rdmacm_mux_can_receive, rdmacm_mux_read, NULL,
997 NULL, backend_dev, NULL, true);
998
605ec166
YS
999 return 0;
1000}
1001
1002static void mad_fini(RdmaBackendDev *backend_dev)
1003{
2b05705d
YS
1004 disable_rdmacm_mux_async(backend_dev);
1005 qemu_chr_fe_disconnect(backend_dev->rdmacm_mux.chr_be);
b20fc795 1006 rdma_protected_qlist_destroy(&backend_dev->recv_mads_list);
605ec166
YS
1007}
1008
2b05705d
YS
1009int rdma_backend_get_gid_index(RdmaBackendDev *backend_dev,
1010 union ibv_gid *gid)
1011{
1012 union ibv_gid sgid;
1013 int ret;
1014 int i = 0;
1015
2b05705d
YS
1016 do {
1017 ret = ibv_query_gid(backend_dev->context, backend_dev->port_num, i,
1018 &sgid);
1019 i++;
1020 } while (!ret && (memcmp(&sgid, gid, sizeof(*gid))));
1021
4d71b38a
YS
1022 trace_rdma_backend_get_gid_index(be64_to_cpu(gid->global.subnet_prefix),
1023 be64_to_cpu(gid->global.interface_id),
1024 i - 1);
2b05705d
YS
1025
1026 return ret ? ret : i - 1;
1027}
1028
1029int rdma_backend_add_gid(RdmaBackendDev *backend_dev, const char *ifname,
1030 union ibv_gid *gid)
1031{
555b3d67 1032 RdmaCmMuxMsg msg = {};
2b05705d
YS
1033 int ret;
1034
4d71b38a
YS
1035 trace_rdma_backend_gid_change("add", be64_to_cpu(gid->global.subnet_prefix),
1036 be64_to_cpu(gid->global.interface_id));
2b05705d
YS
1037
1038 msg.hdr.op_code = RDMACM_MUX_OP_CODE_REG;
1039 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1040
4d71b38a 1041 ret = rdmacm_mux_send(backend_dev, &msg);
2b05705d 1042 if (ret) {
4d71b38a 1043 rdma_error_report("Failed to register GID to rdma_umadmux (%d)", ret);
2b05705d
YS
1044 return -EIO;
1045 }
1046
1047 qapi_event_send_rdma_gid_status_changed(ifname, true,
1048 gid->global.subnet_prefix,
1049 gid->global.interface_id);
1050
1051 return ret;
1052}
1053
1054int rdma_backend_del_gid(RdmaBackendDev *backend_dev, const char *ifname,
1055 union ibv_gid *gid)
1056{
555b3d67 1057 RdmaCmMuxMsg msg = {};
2b05705d
YS
1058 int ret;
1059
4d71b38a
YS
1060 trace_rdma_backend_gid_change("del", be64_to_cpu(gid->global.subnet_prefix),
1061 be64_to_cpu(gid->global.interface_id));
2b05705d
YS
1062
1063 msg.hdr.op_code = RDMACM_MUX_OP_CODE_UNREG;
1064 memcpy(msg.hdr.sgid.raw, gid->raw, sizeof(msg.hdr.sgid));
1065
4d71b38a 1066 ret = rdmacm_mux_send(backend_dev, &msg);
2b05705d 1067 if (ret) {
4d71b38a
YS
1068 rdma_error_report("Failed to unregister GID from rdma_umadmux (%d)",
1069 ret);
2b05705d
YS
1070 return -EIO;
1071 }
1072
1073 qapi_event_send_rdma_gid_status_changed(ifname, false,
1074 gid->global.subnet_prefix,
1075 gid->global.interface_id);
1076
1077 return 0;
1078}
1079
430e440c 1080int rdma_backend_init(RdmaBackendDev *backend_dev, PCIDevice *pdev,
ef6d4ccd
YS
1081 RdmaDeviceResources *rdma_dev_res,
1082 const char *backend_device_name, uint8_t port_num,
4d71b38a 1083 struct ibv_device_attr *dev_attr, CharBackend *mad_chr_be)
ef6d4ccd
YS
1084{
1085 int i;
1086 int ret = 0;
1087 int num_ibv_devices;
ef6d4ccd 1088 struct ibv_device **dev_list;
ef6d4ccd 1089
430e440c
YS
1090 memset(backend_dev, 0, sizeof(*backend_dev));
1091
1092 backend_dev->dev = pdev;
ef6d4ccd
YS
1093 backend_dev->port_num = port_num;
1094 backend_dev->rdma_dev_res = rdma_dev_res;
1095
1096 rdma_backend_register_comp_handler(dummy_comp_handler);
1097
1098 dev_list = ibv_get_device_list(&num_ibv_devices);
1099 if (!dev_list) {
4d71b38a 1100 rdma_error_report("Failed to get IB devices list");
ef6d4ccd
YS
1101 return -EIO;
1102 }
1103
1104 if (num_ibv_devices == 0) {
4d71b38a 1105 rdma_error_report("No IB devices were found");
ef6d4ccd
YS
1106 ret = -ENXIO;
1107 goto out_free_dev_list;
1108 }
1109
1110 if (backend_device_name) {
1111 for (i = 0; dev_list[i]; ++i) {
1112 if (!strcmp(ibv_get_device_name(dev_list[i]),
1113 backend_device_name)) {
1114 break;
1115 }
1116 }
1117
1118 backend_dev->ib_dev = dev_list[i];
1119 if (!backend_dev->ib_dev) {
4d71b38a
YS
1120 rdma_error_report("Failed to find IB device %s",
1121 backend_device_name);
ef6d4ccd
YS
1122 ret = -EIO;
1123 goto out_free_dev_list;
1124 }
1125 } else {
1126 backend_dev->ib_dev = *dev_list;
1127 }
1128
4d71b38a 1129 rdma_info_report("uverb device %s", backend_dev->ib_dev->dev_name);
ef6d4ccd
YS
1130
1131 backend_dev->context = ibv_open_device(backend_dev->ib_dev);
1132 if (!backend_dev->context) {
4d71b38a
YS
1133 rdma_error_report("Failed to open IB device %s",
1134 ibv_get_device_name(backend_dev->ib_dev));
ef6d4ccd
YS
1135 ret = -EIO;
1136 goto out;
1137 }
1138
1139 backend_dev->channel = ibv_create_comp_channel(backend_dev->context);
1140 if (!backend_dev->channel) {
4d71b38a 1141 rdma_error_report("Failed to create IB communication channel");
ef6d4ccd
YS
1142 ret = -EIO;
1143 goto out_close_device;
1144 }
ef6d4ccd 1145
ef6d4ccd
YS
1146 ret = init_device_caps(backend_dev, dev_attr);
1147 if (ret) {
4d71b38a 1148 rdma_error_report("Failed to initialize device capabilities");
ef6d4ccd
YS
1149 ret = -EIO;
1150 goto out_destroy_comm_channel;
1151 }
1152
ef6d4ccd 1153
2b05705d 1154 ret = mad_init(backend_dev, mad_chr_be);
605ec166 1155 if (ret) {
4d71b38a 1156 rdma_error_report("Failed to initialize mad");
605ec166
YS
1157 ret = -EIO;
1158 goto out_destroy_comm_channel;
1159 }
1160
75152227
YS
1161 backend_dev->comp_thread.run = false;
1162 backend_dev->comp_thread.is_running = false;
ef6d4ccd
YS
1163
1164 ah_cache_init();
1165
1166 goto out_free_dev_list;
1167
1168out_destroy_comm_channel:
1169 ibv_destroy_comp_channel(backend_dev->channel);
1170
1171out_close_device:
1172 ibv_close_device(backend_dev->context);
1173
1174out_free_dev_list:
1175 ibv_free_device_list(dev_list);
1176
1177out:
1178 return ret;
1179}
1180
75152227
YS
1181
1182void rdma_backend_start(RdmaBackendDev *backend_dev)
1183{
75152227
YS
1184 start_comp_thread(backend_dev);
1185}
1186
1187void rdma_backend_stop(RdmaBackendDev *backend_dev)
1188{
292dce62 1189 stop_backend_thread(&backend_dev->comp_thread);
75152227
YS
1190}
1191
ef6d4ccd
YS
1192void rdma_backend_fini(RdmaBackendDev *backend_dev)
1193{
75152227 1194 rdma_backend_stop(backend_dev);
605ec166 1195 mad_fini(backend_dev);
ef6d4ccd
YS
1196 g_hash_table_destroy(ah_hash);
1197 ibv_destroy_comp_channel(backend_dev->channel);
1198 ibv_close_device(backend_dev->context);
1199}