[qemu.git] / hw / realview.c

/*
 * ARM RealView Baseboard System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "pci.h"
#include "usb-ohci.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
#include "bitbang_i2c.h"
#include "sysbus.h"
#include "blockdev.h"

#define SMP_BOOT_ADDR 0xe0000000

typedef struct {
    SysBusDevice busdev;
    bitbang_i2c_interface *bitbang;
    int out;
    int in;
} RealViewI2CState;

static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    if (offset == 0) {
        return (s->out & 1) | (s->in << 1);
    } else {
        hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
        return -1;
    }
}

static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
                               uint32_t value)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    switch (offset) {
    case 0:
        s->out |= value & 3;
        break;
    case 4:
        s->out &= ~value;
        break;
    default:
        hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
    }
    bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
    s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
}

static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
   realview_i2c_read,
   realview_i2c_read,
   realview_i2c_read
};

static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
   realview_i2c_write,
   realview_i2c_write,
   realview_i2c_write
};

static int realview_i2c_init(SysBusDevice *dev)
{
    RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
    i2c_bus *bus;
    int iomemtype;

    bus = i2c_init_bus(&dev->qdev, "i2c");
    s->bitbang = bitbang_i2c_init(bus);
    iomemtype = cpu_register_io_memory(realview_i2c_readfn,
                                       realview_i2c_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    return 0;
}

static SysBusDeviceInfo realview_i2c_info = {
    .init = realview_i2c_init,
    .qdev.name  = "realview_i2c",
    .qdev.size  = sizeof(RealViewI2CState),
};

static void realview_register_devices(void)
{
    sysbus_register_withprop(&realview_i2c_info);
}

/* Board init.  */

static struct arm_boot_info realview_binfo = {
    .smp_loader_start = SMP_BOOT_ADDR,
};

static void secondary_cpu_reset(void *opaque)
{
  CPUState *env = opaque;

  cpu_reset(env);
  /* Set entry point for secondary CPUs.  This assumes we're using
     the init code from arm_boot.c.  Real hardware resets all CPUs
     the same.  */
  env->regs[15] = SMP_BOOT_ADDR;
}

/* The following two lists must be consistent.  */
enum realview_board_type {
    BOARD_EB,
    BOARD_EB_MPCORE,
    BOARD_PB_A8,
    BOARD_PBX_A9,
};

static const int realview_board_id[] = {
    0x33b,
    0x33b,
    0x769,
    0x76d
};

static void realview_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     enum realview_board_type board_type)
{
    CPUState *env = NULL;
    ram_addr_t ram_offset;
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq *irqp;
    qemu_irq pic[64];
    PCIBus *pci_bus;
    NICInfo *nd;
    i2c_bus *i2c;
    int n;
    int done_nic = 0;
    qemu_irq cpu_irq[4];
    int is_mpcore = 0;
    int is_pb = 0;
    uint32_t proc_id = 0;
    uint32_t sys_id;
    ram_addr_t low_ram_size;

    switch (board_type) {
    case BOARD_EB:
        break;
    case BOARD_EB_MPCORE:
        is_mpcore = 1;
        break;
    case BOARD_PB_A8:
        is_pb = 1;
        break;
    case BOARD_PBX_A9:
        is_mpcore = 1;
        is_pb = 1;
        break;
    }
    for (n = 0; n < smp_cpus; n++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }
        irqp = arm_pic_init_cpu(env);
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
        if (n > 0) {
            qemu_register_reset(secondary_cpu_reset, env);
        }
    }
    if (arm_feature(env, ARM_FEATURE_V7)) {
        if (is_mpcore) {
            proc_id = 0x0c000000;
        } else {
            proc_id = 0x0e000000;
        }
    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
        proc_id = 0x06000000;
    } else if (arm_feature(env, ARM_FEATURE_V6)) {
        proc_id = 0x04000000;
    } else {
        proc_id = 0x02000000;
    }

    if (is_pb && ram_size > 0x20000000) {
        /* Core tile RAM.  */
        low_ram_size = ram_size - 0x20000000;
        ram_size = 0x20000000;
        ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size);
        cpu_register_physical_memory(0x20000000, low_ram_size,
                                     ram_offset | IO_MEM_RAM);
    }

    ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size);
    low_ram_size = ram_size;
    if (low_ram_size > 0x10000000)
      low_ram_size = 0x10000000;
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
    if (is_pb) {
        /* And again at a high address.  */
        cpu_register_physical_memory(0x70000000, ram_size,
                                     ram_offset | IO_MEM_RAM);
    } else {
        ram_size = low_ram_size;
    }

    sys_id = is_pb ? 0x01780500 : 0xc1400400;
    arm_sysctl_init(0x10000000, sys_id, proc_id);

    if (is_mpcore) {
        dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
        qdev_init_nofail(dev);
        busdev = sysbus_from_qdev(dev);
        if (is_pb) {
            realview_binfo.smp_priv_base = 0x1f000000;
        } else {
            realview_binfo.smp_priv_base = 0x10100000;
        }
        sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
        for (n = 0; n < smp_cpus; n++) {
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
        }
    } else {
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
        /* For now just create the nIRQ GIC, and ignore the others.  */
        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
    }
    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);

    sysbus_create_simple("pl011", 0x10009000, pic[12]);
    sysbus_create_simple("pl011", 0x1000a000, pic[13]);
    sysbus_create_simple("pl011", 0x1000b000, pic[14]);
    sysbus_create_simple("pl011", 0x1000c000, pic[15]);

    /* DMA controller is optional, apparently.  */
    sysbus_create_simple("pl081", 0x10030000, pic[24]);

    sysbus_create_simple("sp804", 0x10011000, pic[4]);
    sysbus_create_simple("sp804", 0x10012000, pic[5]);

    sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);

    sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);

    sysbus_create_simple("pl031", 0x10017000, pic[10]);

    if (!is_pb) {
        dev = sysbus_create_varargs("realview_pci", 0x60000000,
                                    pic[48], pic[49], pic[50], pic[51], NULL);
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
        if (usb_enabled) {
            usb_ohci_init_pci(pci_bus, -1);
        }
        n = drive_get_max_bus(IF_SCSI);
        while (n >= 0) {
            pci_create_simple(pci_bus, -1, "lsi53c895a");
            n--;
        }
    }
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if ((!nd->model && !done_nic)
            || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
            if (is_pb) {
                lan9118_init(nd, 0x4e000000, pic[28]);
            } else {
                smc91c111_init(nd, 0x4e000000, pic[28]);
            }
            done_nic = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }

    dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
    i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Memory map for RealView Emulation Baseboard:  */
    /* 0x10000000 System registers.  */
    /*  0x10001000 System controller.  */
    /* 0x10002000 Two-Wire Serial Bus.  */
    /* 0x10003000 Reserved.  */
    /*  0x10004000 AACI.  */
    /*  0x10005000 MCI.  */
    /* 0x10006000 KMI0.  */
    /* 0x10007000 KMI1.  */
    /*  0x10008000 Character LCD. (EB) */
    /* 0x10009000 UART0.  */
    /* 0x1000a000 UART1.  */
    /* 0x1000b000 UART2.  */
    /* 0x1000c000 UART3.  */
    /*  0x1000d000 SSPI.  */
    /*  0x1000e000 SCI.  */
    /* 0x1000f000 Reserved.  */
    /*  0x10010000 Watchdog.  */
    /* 0x10011000 Timer 0+1.  */
    /* 0x10012000 Timer 2+3.  */
    /*  0x10013000 GPIO 0.  */
    /*  0x10014000 GPIO 1.  */
    /*  0x10015000 GPIO 2.  */
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
    /* 0x10017000 RTC.  */
    /*  0x10018000 DMC.  */
    /*  0x10019000 PCI controller config.  */
    /*  0x10020000 CLCD.  */
    /* 0x10030000 DMA Controller.  */
    /* 0x10040000 GIC1. (EB) */
    /*  0x10050000 GIC2. (EB) */
    /*  0x10060000 GIC3. (EB) */
    /*  0x10070000 GIC4. (EB) */
    /*  0x10080000 SMC.  */
    /* 0x1e000000 GIC1. (PB) */
    /*  0x1e001000 GIC2. (PB) */
    /*  0x1e002000 GIC3. (PB) */
    /*  0x1e003000 GIC4. (PB) */
    /*  0x40000000 NOR flash.  */
    /*  0x44000000 DoC flash.  */
    /*  0x48000000 SRAM.  */
    /*  0x4c000000 Configuration flash.  */
    /* 0x4e000000 Ethernet.  */
    /*  0x4f000000 USB.  */
    /*  0x50000000 PISMO.  */
    /*  0x54000000 PISMO.  */
    /*  0x58000000 PISMO.  */
    /*  0x5c000000 PISMO.  */
    /* 0x60000000 PCI.  */
    /* 0x61000000 PCI Self Config.  */
    /* 0x62000000 PCI Config.  */
    /* 0x63000000 PCI IO.  */
    /* 0x64000000 PCI mem 0.  */
    /* 0x68000000 PCI mem 1.  */
    /* 0x6c000000 PCI mem 2.  */

    /* ??? Hack to map an additional page of ram for the secondary CPU
       startup code.  I guess this works on real hardware because the
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
       until after Linux boots the secondary CPUs.  */
    ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000);
    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
                                 ram_offset | IO_MEM_RAM);

    realview_binfo.ram_size = ram_size;
    realview_binfo.kernel_filename = kernel_filename;
    realview_binfo.kernel_cmdline = kernel_cmdline;
    realview_binfo.initrd_filename = initrd_filename;
    realview_binfo.nb_cpus = smp_cpus;
    realview_binfo.board_id = realview_board_id[board_type];
    realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
    arm_load_kernel(first_cpu, &realview_binfo);
}

static void realview_eb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm926";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB);
}

static void realview_eb_mpcore_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm11mpcore";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
}

static void realview_pb_a8_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a8";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PB_A8);
}

static void realview_pbx_a9_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PBX_A9);
}

static QEMUMachine realview_eb_machine = {
    .name = "realview-eb",
    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
    .init = realview_eb_init,
    .use_scsi = 1,
};

static QEMUMachine realview_eb_mpcore_machine = {
    .name = "realview-eb-mpcore",
    .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
    .init = realview_eb_mpcore_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static QEMUMachine realview_pb_a8_machine = {
    .name = "realview-pb-a8",
    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
    .init = realview_pb_a8_init,
};

static QEMUMachine realview_pbx_a9_machine = {
    .name = "realview-pbx-a9",
    .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
    .init = realview_pbx_a9_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static void realview_machine_init(void)
{
    qemu_register_machine(&realview_eb_machine);
    qemu_register_machine(&realview_eb_mpcore_machine);
    qemu_register_machine(&realview_pb_a8_machine);
    qemu_register_machine(&realview_pbx_a9_machine);
}

machine_init(realview_machine_init);
device_init(realview_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* ARM RealView Baseboard System emulation.
e69954b9 PB	3	*
a1bb27b1	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "pci.h"
18e08a55	15	#include "usb-ohci.h"
87ecb68b PB	16	#include "net.h"
	17	#include "sysemu.h"
	18	#include "boards.h"
eee48504 PB	19	#include "bitbang_i2c.h"
eee48504 PB	20	#include "sysbus.h"
2446333c	21	#include "blockdev.h"
e69954b9	22
0ef849d7	23	#define SMP_BOOT_ADDR 0xe0000000
eee48504 PB	24
	25	typedef struct {
	26	SysBusDevice busdev;
	27	bitbang_i2c_interface *bitbang;
	28	int out;
	29	int in;
	30	} RealViewI2CState;
	31
	32	static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
	33	{
	34	RealViewI2CState s = (RealViewI2CState )opaque;
	35
	36	if (offset == 0) {
	37	return (s->out & 1) \| (s->in << 1);
	38	} else {
	39	hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
	40	return -1;
	41	}
	42	}
	43
	44	static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
	45	uint32_t value)
	46	{
	47	RealViewI2CState s = (RealViewI2CState )opaque;
	48
	49	switch (offset) {
	50	case 0:
	51	s->out \|= value & 3;
	52	break;
	53	case 4:
	54	s->out &= ~value;
	55	break;
	56	default:
	57	hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
	58	}
	59	bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
	60	s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
	61	}
	62
	63	static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
	64	realview_i2c_read,
	65	realview_i2c_read,
	66	realview_i2c_read
	67	};
	68
	69	static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
	70	realview_i2c_write,
	71	realview_i2c_write,
	72	realview_i2c_write
	73	};
	74
	75	static int realview_i2c_init(SysBusDevice *dev)
	76	{
	77	RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
	78	i2c_bus *bus;
	79	int iomemtype;
	80
	81	bus = i2c_init_bus(&dev->qdev, "i2c");
	82	s->bitbang = bitbang_i2c_init(bus);
	83	iomemtype = cpu_register_io_memory(realview_i2c_readfn,
2507c12a AG	84	realview_i2c_writefn, s,
2507c12a AG	85	DEVICE_NATIVE_ENDIAN);
eee48504 PB	86	sysbus_init_mmio(dev, 0x1000, iomemtype);
	87	return 0;
	88	}
	89
	90	static SysBusDeviceInfo realview_i2c_info = {
	91	.init = realview_i2c_init,
	92	.qdev.name = "realview_i2c",
	93	.qdev.size = sizeof(RealViewI2CState),
	94	};
	95
	96	static void realview_register_devices(void)
	97	{
	98	sysbus_register_withprop(&realview_i2c_info);
	99	}
	100
e69954b9 PB	101	/* Board init. */
e69954b9 PB	102
f93eb9ff	103	static struct arm_boot_info realview_binfo = {
0ef849d7	104	.smp_loader_start = SMP_BOOT_ADDR,
f93eb9ff AZ	105	};
f93eb9ff AZ	106
be0f204a PB	107	static void secondary_cpu_reset(void *opaque)
	108	{
	109	CPUState *env = opaque;
	110
	111	cpu_reset(env);
	112	/* Set entry point for secondary CPUs. This assumes we're using
	113	the init code from arm_boot.c. Real hardware resets all CPUs
	114	the same. */
0ef849d7	115	env->regs[15] = SMP_BOOT_ADDR;
be0f204a PB	116	}
be0f204a PB	117
f7c70325	118	/* The following two lists must be consistent. */
c988bfad PB	119	enum realview_board_type {
c988bfad PB	120	BOARD_EB,
0ef849d7	121	BOARD_EB_MPCORE,
f7c70325 PB	122	BOARD_PB_A8,
	123	BOARD_PBX_A9,
	124	};
	125
d05ac8fa	126	static const int realview_board_id[] = {
f7c70325 PB	127	0x33b,
	128	0x33b,
	129	0x769,
	130	0x76d
c988bfad PB	131	};
c988bfad PB	132
c227f099	133	static void realview_init(ram_addr_t ram_size,
3023f332	134	const char *boot_device,
e69954b9	135	const char kernel_filename, const char kernel_cmdline,
c988bfad PB	136	const char initrd_filename, const char cpu_model,
c988bfad PB	137	enum realview_board_type board_type)
e69954b9	138	{
c988bfad	139	CPUState *env = NULL;
c227f099	140	ram_addr_t ram_offset;
0027b06d	141	DeviceState *dev;
c988bfad	142	SysBusDevice *busdev;
fe7e8758 PB	143	qemu_irq *irqp;
fe7e8758 PB	144	qemu_irq pic[64];
e69954b9 PB	145	PCIBus *pci_bus;
e69954b9 PB	146	NICInfo *nd;
eee48504	147	i2c_bus *i2c;
e69954b9	148	int n;
0ef849d7	149	int done_nic = 0;
9ee6e8bb	150	qemu_irq cpu_irq[4];
f7c70325 PB	151	int is_mpcore = 0;
f7c70325 PB	152	int is_pb = 0;
26e92f65	153	uint32_t proc_id = 0;
0ef849d7 PB	154	uint32_t sys_id;
0ef849d7 PB	155	ram_addr_t low_ram_size;
e69954b9	156
f7c70325 PB	157	switch (board_type) {
	158	case BOARD_EB:
	159	break;
	160	case BOARD_EB_MPCORE:
	161	is_mpcore = 1;
	162	break;
	163	case BOARD_PB_A8:
	164	is_pb = 1;
	165	break;
	166	case BOARD_PBX_A9:
	167	is_mpcore = 1;
	168	is_pb = 1;
	169	break;
	170	}
c988bfad	171	for (n = 0; n < smp_cpus; n++) {
9ee6e8bb PB	172	env = cpu_init(cpu_model);
	173	if (!env) {
	174	fprintf(stderr, "Unable to find CPU definition\n");
	175	exit(1);
	176	}
fe7e8758 PB	177	irqp = arm_pic_init_cpu(env);
fe7e8758 PB	178	cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
9ee6e8bb	179	if (n > 0) {
be0f204a	180	qemu_register_reset(secondary_cpu_reset, env);
9ee6e8bb	181	}
aaed909a	182	}
26e92f65	183	if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325 PB	184	if (is_mpcore) {
	185	proc_id = 0x0c000000;
	186	} else {
	187	proc_id = 0x0e000000;
	188	}
26e92f65 PB	189	} else if (arm_feature(env, ARM_FEATURE_V6K)) {
	190	proc_id = 0x06000000;
	191	} else if (arm_feature(env, ARM_FEATURE_V6)) {
	192	proc_id = 0x04000000;
	193	} else {
	194	proc_id = 0x02000000;
	195	}
aaed909a	196
21a88941 PB	197	if (is_pb && ram_size > 0x20000000) {
	198	/* Core tile RAM. */
	199	low_ram_size = ram_size - 0x20000000;
	200	ram_size = 0x20000000;
1724f049	201	ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size);
21a88941 PB	202	cpu_register_physical_memory(0x20000000, low_ram_size,
	203	ram_offset \| IO_MEM_RAM);
	204	}
	205
1724f049	206	ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size);
0ef849d7 PB	207	low_ram_size = ram_size;
	208	if (low_ram_size > 0x10000000)
	209	low_ram_size = 0x10000000;
e69954b9	210	/* SDRAM at address zero. */
0ef849d7 PB	211	cpu_register_physical_memory(0, low_ram_size, ram_offset \| IO_MEM_RAM);
	212	if (is_pb) {
	213	/* And again at a high address. */
	214	cpu_register_physical_memory(0x70000000, ram_size,
	215	ram_offset \| IO_MEM_RAM);
	216	} else {
	217	ram_size = low_ram_size;
	218	}
e69954b9	219
0ef849d7 PB	220	sys_id = is_pb ? 0x01780500 : 0xc1400400;
0ef849d7 PB	221	arm_sysctl_init(0x10000000, sys_id, proc_id);
9ee6e8bb	222
c988bfad	223	if (is_mpcore) {
f7c70325	224	dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
c988bfad PB	225	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	226	qdev_init_nofail(dev);
	227	busdev = sysbus_from_qdev(dev);
f7c70325 PB	228	if (is_pb) {
	229	realview_binfo.smp_priv_base = 0x1f000000;
	230	} else {
	231	realview_binfo.smp_priv_base = 0x10100000;
	232	}
	233	sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
c988bfad PB	234	for (n = 0; n < smp_cpus; n++) {
	235	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	236	}
9ee6e8bb	237	} else {
0ef849d7 PB	238	uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
	239	/* For now just create the nIRQ GIC, and ignore the others. */
	240	dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
fe7e8758 PB	241	}
fe7e8758 PB	242	for (n = 0; n < 64; n++) {
067a3ddc	243	pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb PB	244	}
9ee6e8bb PB	245
86394e96 PB	246	sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
86394e96 PB	247	sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9	248
a7d518a6 PB	249	sysbus_create_simple("pl011", 0x10009000, pic[12]);
	250	sysbus_create_simple("pl011", 0x1000a000, pic[13]);
	251	sysbus_create_simple("pl011", 0x1000b000, pic[14]);
	252	sysbus_create_simple("pl011", 0x1000c000, pic[15]);
e69954b9 PB	253
e69954b9 PB	254	/* DMA controller is optional, apparently. */
b4496b13	255	sysbus_create_simple("pl081", 0x10030000, pic[24]);
e69954b9	256
6a824ec3 PB	257	sysbus_create_simple("sp804", 0x10011000, pic[4]);
6a824ec3 PB	258	sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9	259
2e9bdce5	260	sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
e69954b9	261
aa9311d8	262	sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
a1bb27b1	263
a63bdb31	264	sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2	265
0ef849d7 PB	266	if (!is_pb) {
	267	dev = sysbus_create_varargs("realview_pci", 0x60000000,
	268	pic[48], pic[49], pic[50], pic[51], NULL);
	269	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
	270	if (usb_enabled) {
a67ba3b6	271	usb_ohci_init_pci(pci_bus, -1);
0ef849d7 PB	272	}
	273	n = drive_get_max_bus(IF_SCSI);
	274	while (n >= 0) {
	275	pci_create_simple(pci_bus, -1, "lsi53c895a");
	276	n--;
	277	}
e69954b9 PB	278	}
	279	for(n = 0; n < nb_nics; n++) {
	280	nd = &nd_table[n];
0ae18cee	281
0ef849d7 PB	282	if ((!nd->model && !done_nic)
	283	\|\| strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
	284	if (is_pb) {
	285	lan9118_init(nd, 0x4e000000, pic[28]);
	286	} else {
	287	smc91c111_init(nd, 0x4e000000, pic[28]);
	288	}
	289	done_nic = 1;
e69954b9	290	} else {
07caea31	291	pci_nic_init_nofail(nd, "rtl8139", NULL);
e69954b9 PB	292	}
	293	}
	294
eee48504 PB	295	dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
	296	i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
	297	i2c_create_slave(i2c, "ds1338", 0x68);
	298
e69954b9 PB	299	/* Memory map for RealView Emulation Baseboard: */
	300	/* 0x10000000 System registers. */
	301	/* 0x10001000 System controller. */
eee48504	302	/* 0x10002000 Two-Wire Serial Bus. */
e69954b9 PB	303	/* 0x10003000 Reserved. */
	304	/* 0x10004000 AACI. */
	305	/* 0x10005000 MCI. */
	306	/* 0x10006000 KMI0. */
	307	/* 0x10007000 KMI1. */
0ef849d7	308	/* 0x10008000 Character LCD. (EB) */
e69954b9 PB	309	/* 0x10009000 UART0. */
	310	/* 0x1000a000 UART1. */
	311	/* 0x1000b000 UART2. */
	312	/* 0x1000c000 UART3. */
	313	/* 0x1000d000 SSPI. */
	314	/* 0x1000e000 SCI. */
	315	/* 0x1000f000 Reserved. */
	316	/* 0x10010000 Watchdog. */
	317	/* 0x10011000 Timer 0+1. */
	318	/* 0x10012000 Timer 2+3. */
	319	/* 0x10013000 GPIO 0. */
	320	/* 0x10014000 GPIO 1. */
	321	/* 0x10015000 GPIO 2. */
0ef849d7	322	/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2	323	/* 0x10017000 RTC. */
e69954b9 PB	324	/* 0x10018000 DMC. */
	325	/* 0x10019000 PCI controller config. */
	326	/* 0x10020000 CLCD. */
	327	/* 0x10030000 DMA Controller. */
0ef849d7 PB	328	/* 0x10040000 GIC1. (EB) */
	329	/* 0x10050000 GIC2. (EB) */
	330	/* 0x10060000 GIC3. (EB) */
	331	/* 0x10070000 GIC4. (EB) */
e69954b9	332	/* 0x10080000 SMC. */
0ef849d7 PB	333	/* 0x1e000000 GIC1. (PB) */
	334	/* 0x1e001000 GIC2. (PB) */
	335	/* 0x1e002000 GIC3. (PB) */
	336	/* 0x1e003000 GIC4. (PB) */
e69954b9 PB	337	/* 0x40000000 NOR flash. */
	338	/* 0x44000000 DoC flash. */
	339	/* 0x48000000 SRAM. */
	340	/* 0x4c000000 Configuration flash. */
	341	/* 0x4e000000 Ethernet. */
	342	/* 0x4f000000 USB. */
	343	/* 0x50000000 PISMO. */
	344	/* 0x54000000 PISMO. */
	345	/* 0x58000000 PISMO. */
	346	/* 0x5c000000 PISMO. */
	347	/* 0x60000000 PCI. */
	348	/* 0x61000000 PCI Self Config. */
	349	/* 0x62000000 PCI Config. */
	350	/* 0x63000000 PCI IO. */
	351	/* 0x64000000 PCI mem 0. */
	352	/* 0x68000000 PCI mem 1. */
	353	/* 0x6c000000 PCI mem 2. */
	354
7ffab4d7 PB	355	/* ??? Hack to map an additional page of ram for the secondary CPU
	356	startup code. I guess this works on real hardware because the
	357	BootROM happens to be in ROM/flash or in memory that isn't clobbered
	358	until after Linux boots the secondary CPUs. */
1724f049	359	ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000);
0ef849d7 PB	360	cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
0ef849d7 PB	361	ram_offset \| IO_MEM_RAM);
7ffab4d7	362
f93eb9ff AZ	363	realview_binfo.ram_size = ram_size;
	364	realview_binfo.kernel_filename = kernel_filename;
	365	realview_binfo.kernel_cmdline = kernel_cmdline;
	366	realview_binfo.initrd_filename = initrd_filename;
c988bfad	367	realview_binfo.nb_cpus = smp_cpus;
f7c70325	368	realview_binfo.board_id = realview_board_id[board_type];
21a88941	369	realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
f93eb9ff	370	arm_load_kernel(first_cpu, &realview_binfo);
e69954b9 PB	371	}
e69954b9 PB	372
c988bfad PB	373	static void realview_eb_init(ram_addr_t ram_size,
	374	const char *boot_device,
	375	const char kernel_filename, const char kernel_cmdline,
	376	const char initrd_filename, const char cpu_model)
	377	{
	378	if (!cpu_model) {
	379	cpu_model = "arm926";
	380	}
	381	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	382	initrd_filename, cpu_model, BOARD_EB);
	383	}
	384
	385	static void realview_eb_mpcore_init(ram_addr_t ram_size,
	386	const char *boot_device,
	387	const char kernel_filename, const char kernel_cmdline,
	388	const char initrd_filename, const char cpu_model)
	389	{
	390	if (!cpu_model) {
	391	cpu_model = "arm11mpcore";
	392	}
	393	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	394	initrd_filename, cpu_model, BOARD_EB_MPCORE);
	395	}
	396
0ef849d7 PB	397	static void realview_pb_a8_init(ram_addr_t ram_size,
	398	const char *boot_device,
	399	const char kernel_filename, const char kernel_cmdline,
	400	const char initrd_filename, const char cpu_model)
	401	{
	402	if (!cpu_model) {
	403	cpu_model = "cortex-a8";
	404	}
	405	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	406	initrd_filename, cpu_model, BOARD_PB_A8);
	407	}
	408
f7c70325 PB	409	static void realview_pbx_a9_init(ram_addr_t ram_size,
	410	const char *boot_device,
	411	const char kernel_filename, const char kernel_cmdline,
	412	const char initrd_filename, const char cpu_model)
	413	{
	414	if (!cpu_model) {
	415	cpu_model = "cortex-a9";
	416	}
	417	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	418	initrd_filename, cpu_model, BOARD_PBX_A9);
	419	}
	420
c988bfad PB	421	static QEMUMachine realview_eb_machine = {
c988bfad PB	422	.name = "realview-eb",
c9b1ae2c	423	.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
c988bfad PB	424	.init = realview_eb_init,
	425	.use_scsi = 1,
	426	};
	427
	428	static QEMUMachine realview_eb_mpcore_machine = {
	429	.name = "realview-eb-mpcore",
	430	.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
	431	.init = realview_eb_mpcore_init,
c9b1ae2c	432	.use_scsi = 1,
c988bfad	433	.max_cpus = 4,
e69954b9	434	};
f80f9ec9	435
0ef849d7 PB	436	static QEMUMachine realview_pb_a8_machine = {
	437	.name = "realview-pb-a8",
	438	.desc = "ARM RealView Platform Baseboard for Cortex-A8",
	439	.init = realview_pb_a8_init,
f7c70325 PB	440	};
	441
	442	static QEMUMachine realview_pbx_a9_machine = {
	443	.name = "realview-pbx-a9",
	444	.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
	445	.init = realview_pbx_a9_init,
0ef849d7	446	.use_scsi = 1,
f7c70325	447	.max_cpus = 4,
0ef849d7 PB	448	};
0ef849d7 PB	449
f80f9ec9 AL	450	static void realview_machine_init(void)
f80f9ec9 AL	451	{
c988bfad PB	452	qemu_register_machine(&realview_eb_machine);
c988bfad PB	453	qemu_register_machine(&realview_eb_mpcore_machine);
0ef849d7	454	qemu_register_machine(&realview_pb_a8_machine);
f7c70325	455	qemu_register_machine(&realview_pbx_a9_machine);
f80f9ec9 AL	456	}
	457
	458	machine_init(realview_machine_init);
eee48504	459	device_init(realview_register_devices)