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5fafdf24 | 1 | /* |
e69954b9 PB |
2 | * ARM RealView Baseboard System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the GPL. | |
8 | */ | |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b PB |
11 | #include "arm-misc.h" |
12 | #include "primecell.h" | |
13 | #include "devices.h" | |
14 | #include "pci.h" | |
15 | #include "net.h" | |
16 | #include "sysemu.h" | |
17 | #include "boards.h" | |
e69954b9 PB |
18 | |
19 | /* Board init. */ | |
20 | ||
f93eb9ff AZ |
21 | static struct arm_boot_info realview_binfo = { |
22 | .loader_start = 0x0, | |
52b43737 | 23 | .smp_loader_start = 0x80000000, |
f93eb9ff AZ |
24 | .board_id = 0x33b, |
25 | }; | |
26 | ||
fbe1b595 | 27 | static void realview_init(ram_addr_t ram_size, |
3023f332 | 28 | const char *boot_device, |
e69954b9 | 29 | const char *kernel_filename, const char *kernel_cmdline, |
94fc95cd | 30 | const char *initrd_filename, const char *cpu_model) |
e69954b9 PB |
31 | { |
32 | CPUState *env; | |
7ffab4d7 | 33 | ram_addr_t ram_offset; |
0027b06d | 34 | DeviceState *dev; |
fe7e8758 PB |
35 | qemu_irq *irqp; |
36 | qemu_irq pic[64]; | |
e69954b9 PB |
37 | PCIBus *pci_bus; |
38 | NICInfo *nd; | |
39 | int n; | |
40 | int done_smc = 0; | |
9ee6e8bb PB |
41 | qemu_irq cpu_irq[4]; |
42 | int ncpu; | |
e69954b9 | 43 | |
3371d272 PB |
44 | if (!cpu_model) |
45 | cpu_model = "arm926"; | |
9ee6e8bb PB |
46 | /* FIXME: obey smp_cpus. */ |
47 | if (strcmp(cpu_model, "arm11mpcore") == 0) { | |
48 | ncpu = 4; | |
49 | } else { | |
50 | ncpu = 1; | |
51 | } | |
52 | ||
53 | for (n = 0; n < ncpu; n++) { | |
54 | env = cpu_init(cpu_model); | |
55 | if (!env) { | |
56 | fprintf(stderr, "Unable to find CPU definition\n"); | |
57 | exit(1); | |
58 | } | |
fe7e8758 PB |
59 | irqp = arm_pic_init_cpu(env); |
60 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; | |
9ee6e8bb PB |
61 | if (n > 0) { |
62 | /* Set entry point for secondary CPUs. This assumes we're using | |
63 | the init code from arm_boot.c. Real hardware resets all CPUs | |
64 | the same. */ | |
65 | env->regs[15] = 0x80000000; | |
66 | } | |
aaed909a FB |
67 | } |
68 | ||
7ffab4d7 | 69 | ram_offset = qemu_ram_alloc(ram_size); |
1235fc06 | 70 | /* ??? RAM should repeat to fill physical memory space. */ |
e69954b9 | 71 | /* SDRAM at address zero. */ |
7ffab4d7 | 72 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
e69954b9 PB |
73 | |
74 | arm_sysctl_init(0x10000000, 0xc1400400); | |
9ee6e8bb PB |
75 | |
76 | if (ncpu == 1) { | |
77 | /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 | |
78 | is nIRQ (there are inconsistencies). However Linux 2.6.17 expects | |
79 | GIC1 to be nIRQ and ignores all the others, so do that for now. */ | |
fe7e8758 | 80 | dev = sysbus_create_simple("realview_gic", 0x10040000, cpu_irq[0]); |
9ee6e8bb | 81 | } else { |
fe7e8758 PB |
82 | dev = sysbus_create_varargs("realview_mpcore", -1, |
83 | cpu_irq[0], cpu_irq[1], cpu_irq[2], | |
84 | cpu_irq[3], NULL); | |
85 | } | |
86 | for (n = 0; n < 64; n++) { | |
067a3ddc | 87 | pic[n] = qdev_get_gpio_in(dev, n); |
9ee6e8bb PB |
88 | } |
89 | ||
86394e96 PB |
90 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); |
91 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); | |
e69954b9 | 92 | |
a7d518a6 PB |
93 | sysbus_create_simple("pl011", 0x10009000, pic[12]); |
94 | sysbus_create_simple("pl011", 0x1000a000, pic[13]); | |
95 | sysbus_create_simple("pl011", 0x1000b000, pic[14]); | |
96 | sysbus_create_simple("pl011", 0x1000c000, pic[15]); | |
e69954b9 PB |
97 | |
98 | /* DMA controller is optional, apparently. */ | |
b4496b13 | 99 | sysbus_create_simple("pl081", 0x10030000, pic[24]); |
e69954b9 | 100 | |
6a824ec3 PB |
101 | sysbus_create_simple("sp804", 0x10011000, pic[4]); |
102 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | |
e69954b9 | 103 | |
2e9bdce5 | 104 | sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]); |
e69954b9 | 105 | |
aa9311d8 | 106 | sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); |
a1bb27b1 | 107 | |
a63bdb31 | 108 | sysbus_create_simple("pl031", 0x10017000, pic[10]); |
7e1543c2 | 109 | |
0027b06d PB |
110 | dev = sysbus_create_varargs("realview_pci", 0x60000000, |
111 | pic[48], pic[49], pic[50], pic[51], NULL); | |
02e2da45 | 112 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
e69954b9 | 113 | if (usb_enabled) { |
e24ad6f1 | 114 | usb_ohci_init_pci(pci_bus, 3, -1); |
e69954b9 | 115 | } |
9be5dafe PB |
116 | n = drive_get_max_bus(IF_SCSI); |
117 | while (n >= 0) { | |
118 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
119 | n--; | |
e69954b9 PB |
120 | } |
121 | for(n = 0; n < nb_nics; n++) { | |
122 | nd = &nd_table[n]; | |
0ae18cee AL |
123 | |
124 | if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) { | |
d537cf6c | 125 | smc91c111_init(nd, 0x4e000000, pic[28]); |
0ae18cee | 126 | done_smc = 1; |
e69954b9 | 127 | } else { |
5607c388 | 128 | pci_nic_init(nd, "rtl8139", NULL); |
e69954b9 PB |
129 | } |
130 | } | |
131 | ||
132 | /* Memory map for RealView Emulation Baseboard: */ | |
133 | /* 0x10000000 System registers. */ | |
134 | /* 0x10001000 System controller. */ | |
135 | /* 0x10002000 Two-Wire Serial Bus. */ | |
136 | /* 0x10003000 Reserved. */ | |
137 | /* 0x10004000 AACI. */ | |
138 | /* 0x10005000 MCI. */ | |
139 | /* 0x10006000 KMI0. */ | |
140 | /* 0x10007000 KMI1. */ | |
141 | /* 0x10008000 Character LCD. */ | |
142 | /* 0x10009000 UART0. */ | |
143 | /* 0x1000a000 UART1. */ | |
144 | /* 0x1000b000 UART2. */ | |
145 | /* 0x1000c000 UART3. */ | |
146 | /* 0x1000d000 SSPI. */ | |
147 | /* 0x1000e000 SCI. */ | |
148 | /* 0x1000f000 Reserved. */ | |
149 | /* 0x10010000 Watchdog. */ | |
150 | /* 0x10011000 Timer 0+1. */ | |
151 | /* 0x10012000 Timer 2+3. */ | |
152 | /* 0x10013000 GPIO 0. */ | |
153 | /* 0x10014000 GPIO 1. */ | |
154 | /* 0x10015000 GPIO 2. */ | |
155 | /* 0x10016000 Reserved. */ | |
7e1543c2 | 156 | /* 0x10017000 RTC. */ |
e69954b9 PB |
157 | /* 0x10018000 DMC. */ |
158 | /* 0x10019000 PCI controller config. */ | |
159 | /* 0x10020000 CLCD. */ | |
160 | /* 0x10030000 DMA Controller. */ | |
9ee6e8bb PB |
161 | /* 0x10040000 GIC1. */ |
162 | /* 0x10050000 GIC2. */ | |
163 | /* 0x10060000 GIC3. */ | |
164 | /* 0x10070000 GIC4. */ | |
e69954b9 PB |
165 | /* 0x10080000 SMC. */ |
166 | /* 0x40000000 NOR flash. */ | |
167 | /* 0x44000000 DoC flash. */ | |
168 | /* 0x48000000 SRAM. */ | |
169 | /* 0x4c000000 Configuration flash. */ | |
170 | /* 0x4e000000 Ethernet. */ | |
171 | /* 0x4f000000 USB. */ | |
172 | /* 0x50000000 PISMO. */ | |
173 | /* 0x54000000 PISMO. */ | |
174 | /* 0x58000000 PISMO. */ | |
175 | /* 0x5c000000 PISMO. */ | |
176 | /* 0x60000000 PCI. */ | |
177 | /* 0x61000000 PCI Self Config. */ | |
178 | /* 0x62000000 PCI Config. */ | |
179 | /* 0x63000000 PCI IO. */ | |
180 | /* 0x64000000 PCI mem 0. */ | |
181 | /* 0x68000000 PCI mem 1. */ | |
182 | /* 0x6c000000 PCI mem 2. */ | |
183 | ||
7ffab4d7 PB |
184 | /* ??? Hack to map an additional page of ram for the secondary CPU |
185 | startup code. I guess this works on real hardware because the | |
186 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
187 | until after Linux boots the secondary CPUs. */ | |
188 | ram_offset = qemu_ram_alloc(0x1000); | |
189 | cpu_register_physical_memory(0x80000000, 0x1000, ram_offset | IO_MEM_RAM); | |
190 | ||
f93eb9ff AZ |
191 | realview_binfo.ram_size = ram_size; |
192 | realview_binfo.kernel_filename = kernel_filename; | |
193 | realview_binfo.kernel_cmdline = kernel_cmdline; | |
194 | realview_binfo.initrd_filename = initrd_filename; | |
195 | realview_binfo.nb_cpus = ncpu; | |
196 | arm_load_kernel(first_cpu, &realview_binfo); | |
e69954b9 PB |
197 | } |
198 | ||
199 | QEMUMachine realview_machine = { | |
c9b1ae2c BS |
200 | .name = "realview", |
201 | .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", | |
202 | .init = realview_init, | |
c9b1ae2c | 203 | .use_scsi = 1, |
e69954b9 | 204 | }; |
f80f9ec9 AL |
205 | |
206 | static void realview_machine_init(void) | |
207 | { | |
208 | qemu_register_machine(&realview_machine); | |
209 | } | |
210 | ||
211 | machine_init(realview_machine_init); |