[qemu.git] / hw / realview.c

/*
 * ARM RealView Baseboard System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "pci.h"
#include "usb-ohci.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
#include "bitbang_i2c.h"
#include "blockdev.h"
#include "exec-memory.h"

#define SMP_BOOT_ADDR 0xe0000000

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    bitbang_i2c_interface *bitbang;
    int out;
    int in;
} RealViewI2CState;

static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset,
                                  unsigned size)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    if (offset == 0) {
        return (s->out & 1) | (s->in << 1);
    } else {
        hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
        return -1;
    }
}

static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
                               uint64_t value, unsigned size)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    switch (offset) {
    case 0:
        s->out |= value & 3;
        break;
    case 4:
        s->out &= ~value;
        break;
    default:
        hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
    }
    bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
    s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
}

static const MemoryRegionOps realview_i2c_ops = {
    .read = realview_i2c_read,
    .write = realview_i2c_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int realview_i2c_init(SysBusDevice *dev)
{
    RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
    i2c_bus *bus;

    bus = i2c_init_bus(&dev->qdev, "i2c");
    s->bitbang = bitbang_i2c_init(bus);
    memory_region_init_io(&s->iomem, &realview_i2c_ops, s,
                          "realview-i2c", 0x1000);
    sysbus_init_mmio_region(dev, &s->iomem);
    return 0;
}

static SysBusDeviceInfo realview_i2c_info = {
    .init = realview_i2c_init,
    .qdev.name  = "realview_i2c",
    .qdev.size  = sizeof(RealViewI2CState),
};

static void realview_register_devices(void)
{
    sysbus_register_withprop(&realview_i2c_info);
}

/* Board init.  */

static struct arm_boot_info realview_binfo = {
    .smp_loader_start = SMP_BOOT_ADDR,
};

/* The following two lists must be consistent.  */
enum realview_board_type {
    BOARD_EB,
    BOARD_EB_MPCORE,
    BOARD_PB_A8,
    BOARD_PBX_A9,
};

static const int realview_board_id[] = {
    0x33b,
    0x33b,
    0x769,
    0x76d
};

static void realview_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     enum realview_board_type board_type)
{
    CPUState *env = NULL;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
    MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
    MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
    MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
    DeviceState *dev, *sysctl, *gpio2, *pl041;
    SysBusDevice *busdev;
    qemu_irq *irqp;
    qemu_irq pic[64];
    qemu_irq mmc_irq[2];
    PCIBus *pci_bus;
    NICInfo *nd;
    i2c_bus *i2c;
    int n;
    int done_nic = 0;
    qemu_irq cpu_irq[4];
    int is_mpcore = 0;
    int is_pb = 0;
    uint32_t proc_id = 0;
    uint32_t sys_id;
    ram_addr_t low_ram_size;

    switch (board_type) {
    case BOARD_EB:
        break;
    case BOARD_EB_MPCORE:
        is_mpcore = 1;
        break;
    case BOARD_PB_A8:
        is_pb = 1;
        break;
    case BOARD_PBX_A9:
        is_mpcore = 1;
        is_pb = 1;
        break;
    }
    for (n = 0; n < smp_cpus; n++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }
        irqp = arm_pic_init_cpu(env);
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
    }
    if (arm_feature(env, ARM_FEATURE_V7)) {
        if (is_mpcore) {
            proc_id = 0x0c000000;
        } else {
            proc_id = 0x0e000000;
        }
    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
        proc_id = 0x06000000;
    } else if (arm_feature(env, ARM_FEATURE_V6)) {
        proc_id = 0x04000000;
    } else {
        proc_id = 0x02000000;
    }

    if (is_pb && ram_size > 0x20000000) {
        /* Core tile RAM.  */
        low_ram_size = ram_size - 0x20000000;
        ram_size = 0x20000000;
        memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
        memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
    }

    memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
    low_ram_size = ram_size;
    if (low_ram_size > 0x10000000)
      low_ram_size = 0x10000000;
    /* SDRAM at address zero.  */
    memory_region_init_alias(ram_alias, "realview.alias",
                             ram_hi, 0, low_ram_size);
    memory_region_add_subregion(sysmem, 0, ram_alias);
    if (is_pb) {
        /* And again at a high address.  */
        memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
    } else {
        ram_size = low_ram_size;
    }

    sys_id = is_pb ? 0x01780500 : 0xc1400400;
    sysctl = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
    qdev_init_nofail(sysctl);
    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
    sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);

    if (is_mpcore) {
        dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
        qdev_init_nofail(dev);
        busdev = sysbus_from_qdev(dev);
        if (is_pb) {
            realview_binfo.smp_priv_base = 0x1f000000;
        } else {
            realview_binfo.smp_priv_base = 0x10100000;
        }
        sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
        for (n = 0; n < smp_cpus; n++) {
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
        }
    } else {
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
        /* For now just create the nIRQ GIC, and ignore the others.  */
        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
    }
    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    pl041 = qdev_create(NULL, "pl041");
    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
    qdev_init_nofail(pl041);
    sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
    sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]);

    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);

    sysbus_create_simple("pl011", 0x10009000, pic[12]);
    sysbus_create_simple("pl011", 0x1000a000, pic[13]);
    sysbus_create_simple("pl011", 0x1000b000, pic[14]);
    sysbus_create_simple("pl011", 0x1000c000, pic[15]);

    /* DMA controller is optional, apparently.  */
    sysbus_create_simple("pl081", 0x10030000, pic[24]);

    sysbus_create_simple("sp804", 0x10011000, pic[4]);
    sysbus_create_simple("sp804", 0x10012000, pic[5]);

    sysbus_create_simple("pl061", 0x10013000, pic[6]);
    sysbus_create_simple("pl061", 0x10014000, pic[7]);
    gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);

    sysbus_create_simple("pl111", 0x10020000, pic[23]);

    dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
    /* Wire up MMC card detect and read-only signals. These have
     * to go to both the PL061 GPIO and the sysctl register.
     * Note that the PL181 orders these lines (readonly,inserted)
     * and the PL061 has them the other way about. Also the card
     * detect line is inverted.
     */
    mmc_irq[0] = qemu_irq_split(
        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
        qdev_get_gpio_in(gpio2, 1));
    mmc_irq[1] = qemu_irq_split(
        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
    qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
    qdev_connect_gpio_out(dev, 1, mmc_irq[1]);

    sysbus_create_simple("pl031", 0x10017000, pic[10]);

    if (!is_pb) {
        dev = qdev_create(NULL, "realview_pci");
        busdev = sysbus_from_qdev(dev);
        qdev_init_nofail(dev);
        sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */
        sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */
        sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */
        sysbus_connect_irq(busdev, 0, pic[48]);
        sysbus_connect_irq(busdev, 1, pic[49]);
        sysbus_connect_irq(busdev, 2, pic[50]);
        sysbus_connect_irq(busdev, 3, pic[51]);
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
        if (usb_enabled) {
            usb_ohci_init_pci(pci_bus, -1);
        }
        n = drive_get_max_bus(IF_SCSI);
        while (n >= 0) {
            pci_create_simple(pci_bus, -1, "lsi53c895a");
            n--;
        }
    }
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if (!done_nic && (!nd->model ||
                    strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
            if (is_pb) {
                lan9118_init(nd, 0x4e000000, pic[28]);
            } else {
                smc91c111_init(nd, 0x4e000000, pic[28]);
            }
            done_nic = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }

    dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
    i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Memory map for RealView Emulation Baseboard:  */
    /* 0x10000000 System registers.  */
    /*  0x10001000 System controller.  */
    /* 0x10002000 Two-Wire Serial Bus.  */
    /* 0x10003000 Reserved.  */
    /*  0x10004000 AACI.  */
    /*  0x10005000 MCI.  */
    /* 0x10006000 KMI0.  */
    /* 0x10007000 KMI1.  */
    /*  0x10008000 Character LCD. (EB) */
    /* 0x10009000 UART0.  */
    /* 0x1000a000 UART1.  */
    /* 0x1000b000 UART2.  */
    /* 0x1000c000 UART3.  */
    /*  0x1000d000 SSPI.  */
    /*  0x1000e000 SCI.  */
    /* 0x1000f000 Reserved.  */
    /*  0x10010000 Watchdog.  */
    /* 0x10011000 Timer 0+1.  */
    /* 0x10012000 Timer 2+3.  */
    /*  0x10013000 GPIO 0.  */
    /*  0x10014000 GPIO 1.  */
    /*  0x10015000 GPIO 2.  */
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
    /* 0x10017000 RTC.  */
    /*  0x10018000 DMC.  */
    /*  0x10019000 PCI controller config.  */
    /*  0x10020000 CLCD.  */
    /* 0x10030000 DMA Controller.  */
    /* 0x10040000 GIC1. (EB) */
    /*  0x10050000 GIC2. (EB) */
    /*  0x10060000 GIC3. (EB) */
    /*  0x10070000 GIC4. (EB) */
    /*  0x10080000 SMC.  */
    /* 0x1e000000 GIC1. (PB) */
    /*  0x1e001000 GIC2. (PB) */
    /*  0x1e002000 GIC3. (PB) */
    /*  0x1e003000 GIC4. (PB) */
    /*  0x40000000 NOR flash.  */
    /*  0x44000000 DoC flash.  */
    /*  0x48000000 SRAM.  */
    /*  0x4c000000 Configuration flash.  */
    /* 0x4e000000 Ethernet.  */
    /*  0x4f000000 USB.  */
    /*  0x50000000 PISMO.  */
    /*  0x54000000 PISMO.  */
    /*  0x58000000 PISMO.  */
    /*  0x5c000000 PISMO.  */
    /* 0x60000000 PCI.  */
    /* 0x61000000 PCI Self Config.  */
    /* 0x62000000 PCI Config.  */
    /* 0x63000000 PCI IO.  */
    /* 0x64000000 PCI mem 0.  */
    /* 0x68000000 PCI mem 1.  */
    /* 0x6c000000 PCI mem 2.  */

    /* ??? Hack to map an additional page of ram for the secondary CPU
       startup code.  I guess this works on real hardware because the
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
       until after Linux boots the secondary CPUs.  */
    memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
    memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);

    realview_binfo.ram_size = ram_size;
    realview_binfo.kernel_filename = kernel_filename;
    realview_binfo.kernel_cmdline = kernel_cmdline;
    realview_binfo.initrd_filename = initrd_filename;
    realview_binfo.nb_cpus = smp_cpus;
    realview_binfo.board_id = realview_board_id[board_type];
    realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
    arm_load_kernel(first_cpu, &realview_binfo);
}

static void realview_eb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm926";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB);
}

static void realview_eb_mpcore_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm11mpcore";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
}

static void realview_pb_a8_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a8";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PB_A8);
}

static void realview_pbx_a9_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PBX_A9);
}

static QEMUMachine realview_eb_machine = {
    .name = "realview-eb",
    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
    .init = realview_eb_init,
    .use_scsi = 1,
};

static QEMUMachine realview_eb_mpcore_machine = {
    .name = "realview-eb-mpcore",
    .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
    .init = realview_eb_mpcore_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static QEMUMachine realview_pb_a8_machine = {
    .name = "realview-pb-a8",
    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
    .init = realview_pb_a8_init,
};

static QEMUMachine realview_pbx_a9_machine = {
    .name = "realview-pbx-a9",
    .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
    .init = realview_pbx_a9_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static void realview_machine_init(void)
{
    qemu_register_machine(&realview_eb_machine);
    qemu_register_machine(&realview_eb_mpcore_machine);
    qemu_register_machine(&realview_pb_a8_machine);
    qemu_register_machine(&realview_pbx_a9_machine);
}

machine_init(realview_machine_init);
device_init(realview_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* ARM RealView Baseboard System emulation.
e69954b9 PB	3	*
a1bb27b1	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
e69954b9 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
e69954b9 PB	8	*/
e69954b9 PB	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "pci.h"
18e08a55	15	#include "usb-ohci.h"
87ecb68b PB	16	#include "net.h"
	17	#include "sysemu.h"
	18	#include "boards.h"
eee48504	19	#include "bitbang_i2c.h"
2446333c	20	#include "blockdev.h"
35e87820	21	#include "exec-memory.h"
e69954b9	22
0ef849d7	23	#define SMP_BOOT_ADDR 0xe0000000
eee48504 PB	24
	25	typedef struct {
	26	SysBusDevice busdev;
35e87820	27	MemoryRegion iomem;
eee48504 PB	28	bitbang_i2c_interface *bitbang;
	29	int out;
	30	int in;
	31	} RealViewI2CState;
	32
35e87820 AK	33	static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset,
35e87820 AK	34	unsigned size)
eee48504 PB	35	{
	36	RealViewI2CState s = (RealViewI2CState )opaque;
	37
	38	if (offset == 0) {
	39	return (s->out & 1) \| (s->in << 1);
	40	} else {
	41	hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
	42	return -1;
	43	}
	44	}
	45
	46	static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
35e87820	47	uint64_t value, unsigned size)
eee48504 PB	48	{
	49	RealViewI2CState s = (RealViewI2CState )opaque;
	50
	51	switch (offset) {
	52	case 0:
	53	s->out \|= value & 3;
	54	break;
	55	case 4:
	56	s->out &= ~value;
	57	break;
	58	default:
	59	hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
	60	}
	61	bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
	62	s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
	63	}
	64
35e87820 AK	65	static const MemoryRegionOps realview_i2c_ops = {
	66	.read = realview_i2c_read,
	67	.write = realview_i2c_write,
	68	.endianness = DEVICE_NATIVE_ENDIAN,
eee48504 PB	69	};
	70
	71	static int realview_i2c_init(SysBusDevice *dev)
	72	{
	73	RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
	74	i2c_bus *bus;
eee48504 PB	75
	76	bus = i2c_init_bus(&dev->qdev, "i2c");
	77	s->bitbang = bitbang_i2c_init(bus);
35e87820 AK	78	memory_region_init_io(&s->iomem, &realview_i2c_ops, s,
	79	"realview-i2c", 0x1000);
	80	sysbus_init_mmio_region(dev, &s->iomem);
eee48504 PB	81	return 0;
	82	}
	83
	84	static SysBusDeviceInfo realview_i2c_info = {
	85	.init = realview_i2c_init,
	86	.qdev.name = "realview_i2c",
	87	.qdev.size = sizeof(RealViewI2CState),
	88	};
	89
	90	static void realview_register_devices(void)
	91	{
	92	sysbus_register_withprop(&realview_i2c_info);
	93	}
	94
e69954b9 PB	95	/* Board init. */
e69954b9 PB	96
f93eb9ff	97	static struct arm_boot_info realview_binfo = {
0ef849d7	98	.smp_loader_start = SMP_BOOT_ADDR,
f93eb9ff AZ	99	};
f93eb9ff AZ	100
f7c70325	101	/* The following two lists must be consistent. */
c988bfad PB	102	enum realview_board_type {
c988bfad PB	103	BOARD_EB,
0ef849d7	104	BOARD_EB_MPCORE,
f7c70325 PB	105	BOARD_PB_A8,
	106	BOARD_PBX_A9,
	107	};
	108
d05ac8fa	109	static const int realview_board_id[] = {
f7c70325 PB	110	0x33b,
	111	0x33b,
	112	0x769,
	113	0x76d
c988bfad PB	114	};
c988bfad PB	115
c227f099	116	static void realview_init(ram_addr_t ram_size,
3023f332	117	const char *boot_device,
e69954b9	118	const char kernel_filename, const char kernel_cmdline,
c988bfad PB	119	const char initrd_filename, const char cpu_model,
c988bfad PB	120	enum realview_board_type board_type)
e69954b9	121	{
c988bfad	122	CPUState *env = NULL;
35e87820 AK	123	MemoryRegion *sysmem = get_system_memory();
	124	MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
	125	MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
	126	MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
	127	MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
03a0e944	128	DeviceState dev, sysctl, gpio2, pl041;
c988bfad	129	SysBusDevice *busdev;
fe7e8758 PB	130	qemu_irq *irqp;
fe7e8758 PB	131	qemu_irq pic[64];
26883c69	132	qemu_irq mmc_irq[2];
e69954b9 PB	133	PCIBus *pci_bus;
e69954b9 PB	134	NICInfo *nd;
eee48504	135	i2c_bus *i2c;
e69954b9	136	int n;
0ef849d7	137	int done_nic = 0;
9ee6e8bb	138	qemu_irq cpu_irq[4];
f7c70325 PB	139	int is_mpcore = 0;
f7c70325 PB	140	int is_pb = 0;
26e92f65	141	uint32_t proc_id = 0;
0ef849d7 PB	142	uint32_t sys_id;
0ef849d7 PB	143	ram_addr_t low_ram_size;
e69954b9	144
f7c70325 PB	145	switch (board_type) {
	146	case BOARD_EB:
	147	break;
	148	case BOARD_EB_MPCORE:
	149	is_mpcore = 1;
	150	break;
	151	case BOARD_PB_A8:
	152	is_pb = 1;
	153	break;
	154	case BOARD_PBX_A9:
	155	is_mpcore = 1;
	156	is_pb = 1;
	157	break;
	158	}
c988bfad	159	for (n = 0; n < smp_cpus; n++) {
9ee6e8bb PB	160	env = cpu_init(cpu_model);
	161	if (!env) {
	162	fprintf(stderr, "Unable to find CPU definition\n");
	163	exit(1);
	164	}
fe7e8758 PB	165	irqp = arm_pic_init_cpu(env);
fe7e8758 PB	166	cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
aaed909a	167	}
26e92f65	168	if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325 PB	169	if (is_mpcore) {
	170	proc_id = 0x0c000000;
	171	} else {
	172	proc_id = 0x0e000000;
	173	}
26e92f65 PB	174	} else if (arm_feature(env, ARM_FEATURE_V6K)) {
	175	proc_id = 0x06000000;
	176	} else if (arm_feature(env, ARM_FEATURE_V6)) {
	177	proc_id = 0x04000000;
	178	} else {
	179	proc_id = 0x02000000;
	180	}
aaed909a	181
21a88941 PB	182	if (is_pb && ram_size > 0x20000000) {
	183	/* Core tile RAM. */
	184	low_ram_size = ram_size - 0x20000000;
	185	ram_size = 0x20000000;
35e87820 AK	186	memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size);
35e87820 AK	187	memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
21a88941 PB	188	}
21a88941 PB	189
35e87820	190	memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size);
0ef849d7 PB	191	low_ram_size = ram_size;
	192	if (low_ram_size > 0x10000000)
	193	low_ram_size = 0x10000000;
e69954b9	194	/* SDRAM at address zero. */
35e87820 AK	195	memory_region_init_alias(ram_alias, "realview.alias",
	196	ram_hi, 0, low_ram_size);
	197	memory_region_add_subregion(sysmem, 0, ram_alias);
0ef849d7 PB	198	if (is_pb) {
0ef849d7 PB	199	/* And again at a high address. */
35e87820	200	memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
0ef849d7 PB	201	} else {
	202	ram_size = low_ram_size;
	203	}
e69954b9	204
0ef849d7	205	sys_id = is_pb ? 0x01780500 : 0xc1400400;
26883c69 PM	206	sysctl = qdev_create(NULL, "realview_sysctl");
	207	qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
	208	qdev_init_nofail(sysctl);
	209	qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
	210	sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
9ee6e8bb	211
c988bfad	212	if (is_mpcore) {
f7c70325	213	dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
c988bfad PB	214	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	215	qdev_init_nofail(dev);
	216	busdev = sysbus_from_qdev(dev);
f7c70325 PB	217	if (is_pb) {
	218	realview_binfo.smp_priv_base = 0x1f000000;
	219	} else {
	220	realview_binfo.smp_priv_base = 0x10100000;
	221	}
	222	sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
c988bfad PB	223	for (n = 0; n < smp_cpus; n++) {
	224	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	225	}
9ee6e8bb	226	} else {
0ef849d7 PB	227	uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
	228	/* For now just create the nIRQ GIC, and ignore the others. */
	229	dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
fe7e8758 PB	230	}
fe7e8758 PB	231	for (n = 0; n < 64; n++) {
067a3ddc	232	pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb PB	233	}
9ee6e8bb PB	234
03a0e944 PM	235	pl041 = qdev_create(NULL, "pl041");
	236	qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
	237	qdev_init_nofail(pl041);
	238	sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
	239	sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]);
	240
86394e96 PB	241	sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
86394e96 PB	242	sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9	243
a7d518a6 PB	244	sysbus_create_simple("pl011", 0x10009000, pic[12]);
	245	sysbus_create_simple("pl011", 0x1000a000, pic[13]);
	246	sysbus_create_simple("pl011", 0x1000b000, pic[14]);
	247	sysbus_create_simple("pl011", 0x1000c000, pic[15]);
e69954b9 PB	248
e69954b9 PB	249	/* DMA controller is optional, apparently. */
b4496b13	250	sysbus_create_simple("pl081", 0x10030000, pic[24]);
e69954b9	251
6a824ec3 PB	252	sysbus_create_simple("sp804", 0x10011000, pic[4]);
6a824ec3 PB	253	sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9	254
26883c69 PM	255	sysbus_create_simple("pl061", 0x10013000, pic[6]);
	256	sysbus_create_simple("pl061", 0x10014000, pic[7]);
	257	gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
	258
acb9b722	259	sysbus_create_simple("pl111", 0x10020000, pic[23]);
e69954b9	260
26883c69 PM	261	dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
	262	/* Wire up MMC card detect and read-only signals. These have
	263	* to go to both the PL061 GPIO and the sysctl register.
	264	* Note that the PL181 orders these lines (readonly,inserted)
	265	* and the PL061 has them the other way about. Also the card
	266	* detect line is inverted.
	267	*/
	268	mmc_irq[0] = qemu_irq_split(
	269	qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
	270	qdev_get_gpio_in(gpio2, 1));
	271	mmc_irq[1] = qemu_irq_split(
	272	qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
	273	qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
	274	qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
	275	qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
a1bb27b1	276
a63bdb31	277	sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2	278
0ef849d7	279	if (!is_pb) {
7d6e771f PM	280	dev = qdev_create(NULL, "realview_pci");
	281	busdev = sysbus_from_qdev(dev);
	282	qdev_init_nofail(dev);
	283	sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */
	284	sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */
	285	sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */
	286	sysbus_connect_irq(busdev, 0, pic[48]);
	287	sysbus_connect_irq(busdev, 1, pic[49]);
	288	sysbus_connect_irq(busdev, 2, pic[50]);
	289	sysbus_connect_irq(busdev, 3, pic[51]);
0ef849d7 PB	290	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0ef849d7 PB	291	if (usb_enabled) {
a67ba3b6	292	usb_ohci_init_pci(pci_bus, -1);
0ef849d7 PB	293	}
	294	n = drive_get_max_bus(IF_SCSI);
	295	while (n >= 0) {
	296	pci_create_simple(pci_bus, -1, "lsi53c895a");
	297	n--;
	298	}
e69954b9 PB	299	}
	300	for(n = 0; n < nb_nics; n++) {
	301	nd = &nd_table[n];
0ae18cee	302
e6b3c8ca PM	303	if (!done_nic && (!nd->model \|\|
e6b3c8ca PM	304	strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
0ef849d7 PB	305	if (is_pb) {
	306	lan9118_init(nd, 0x4e000000, pic[28]);
	307	} else {
	308	smc91c111_init(nd, 0x4e000000, pic[28]);
	309	}
	310	done_nic = 1;
e69954b9	311	} else {
07caea31	312	pci_nic_init_nofail(nd, "rtl8139", NULL);
e69954b9 PB	313	}
	314	}
	315
eee48504 PB	316	dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
	317	i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
	318	i2c_create_slave(i2c, "ds1338", 0x68);
	319
e69954b9 PB	320	/* Memory map for RealView Emulation Baseboard: */
	321	/* 0x10000000 System registers. */
	322	/* 0x10001000 System controller. */
eee48504	323	/* 0x10002000 Two-Wire Serial Bus. */
e69954b9 PB	324	/* 0x10003000 Reserved. */
	325	/* 0x10004000 AACI. */
	326	/* 0x10005000 MCI. */
	327	/* 0x10006000 KMI0. */
	328	/* 0x10007000 KMI1. */
0ef849d7	329	/* 0x10008000 Character LCD. (EB) */
e69954b9 PB	330	/* 0x10009000 UART0. */
	331	/* 0x1000a000 UART1. */
	332	/* 0x1000b000 UART2. */
	333	/* 0x1000c000 UART3. */
	334	/* 0x1000d000 SSPI. */
	335	/* 0x1000e000 SCI. */
	336	/* 0x1000f000 Reserved. */
	337	/* 0x10010000 Watchdog. */
	338	/* 0x10011000 Timer 0+1. */
	339	/* 0x10012000 Timer 2+3. */
	340	/* 0x10013000 GPIO 0. */
	341	/* 0x10014000 GPIO 1. */
	342	/* 0x10015000 GPIO 2. */
0ef849d7	343	/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2	344	/* 0x10017000 RTC. */
e69954b9 PB	345	/* 0x10018000 DMC. */
	346	/* 0x10019000 PCI controller config. */
	347	/* 0x10020000 CLCD. */
	348	/* 0x10030000 DMA Controller. */
0ef849d7 PB	349	/* 0x10040000 GIC1. (EB) */
	350	/* 0x10050000 GIC2. (EB) */
	351	/* 0x10060000 GIC3. (EB) */
	352	/* 0x10070000 GIC4. (EB) */
e69954b9	353	/* 0x10080000 SMC. */
0ef849d7 PB	354	/* 0x1e000000 GIC1. (PB) */
	355	/* 0x1e001000 GIC2. (PB) */
	356	/* 0x1e002000 GIC3. (PB) */
	357	/* 0x1e003000 GIC4. (PB) */
e69954b9 PB	358	/* 0x40000000 NOR flash. */
	359	/* 0x44000000 DoC flash. */
	360	/* 0x48000000 SRAM. */
	361	/* 0x4c000000 Configuration flash. */
	362	/* 0x4e000000 Ethernet. */
	363	/* 0x4f000000 USB. */
	364	/* 0x50000000 PISMO. */
	365	/* 0x54000000 PISMO. */
	366	/* 0x58000000 PISMO. */
	367	/* 0x5c000000 PISMO. */
	368	/* 0x60000000 PCI. */
	369	/* 0x61000000 PCI Self Config. */
	370	/* 0x62000000 PCI Config. */
	371	/* 0x63000000 PCI IO. */
	372	/* 0x64000000 PCI mem 0. */
	373	/* 0x68000000 PCI mem 1. */
	374	/* 0x6c000000 PCI mem 2. */
	375
7ffab4d7 PB	376	/* ??? Hack to map an additional page of ram for the secondary CPU
	377	startup code. I guess this works on real hardware because the
	378	BootROM happens to be in ROM/flash or in memory that isn't clobbered
	379	until after Linux boots the secondary CPUs. */
35e87820 AK	380	memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000);
35e87820 AK	381	memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
7ffab4d7	382
f93eb9ff AZ	383	realview_binfo.ram_size = ram_size;
	384	realview_binfo.kernel_filename = kernel_filename;
	385	realview_binfo.kernel_cmdline = kernel_cmdline;
	386	realview_binfo.initrd_filename = initrd_filename;
c988bfad	387	realview_binfo.nb_cpus = smp_cpus;
f7c70325	388	realview_binfo.board_id = realview_board_id[board_type];
21a88941	389	realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
f93eb9ff	390	arm_load_kernel(first_cpu, &realview_binfo);
e69954b9 PB	391	}
e69954b9 PB	392
c988bfad PB	393	static void realview_eb_init(ram_addr_t ram_size,
	394	const char *boot_device,
	395	const char kernel_filename, const char kernel_cmdline,
	396	const char initrd_filename, const char cpu_model)
	397	{
	398	if (!cpu_model) {
	399	cpu_model = "arm926";
	400	}
	401	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	402	initrd_filename, cpu_model, BOARD_EB);
	403	}
	404
	405	static void realview_eb_mpcore_init(ram_addr_t ram_size,
	406	const char *boot_device,
	407	const char kernel_filename, const char kernel_cmdline,
	408	const char initrd_filename, const char cpu_model)
	409	{
	410	if (!cpu_model) {
	411	cpu_model = "arm11mpcore";
	412	}
	413	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	414	initrd_filename, cpu_model, BOARD_EB_MPCORE);
	415	}
	416
0ef849d7 PB	417	static void realview_pb_a8_init(ram_addr_t ram_size,
	418	const char *boot_device,
	419	const char kernel_filename, const char kernel_cmdline,
	420	const char initrd_filename, const char cpu_model)
	421	{
	422	if (!cpu_model) {
	423	cpu_model = "cortex-a8";
	424	}
	425	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	426	initrd_filename, cpu_model, BOARD_PB_A8);
	427	}
	428
f7c70325 PB	429	static void realview_pbx_a9_init(ram_addr_t ram_size,
	430	const char *boot_device,
	431	const char kernel_filename, const char kernel_cmdline,
	432	const char initrd_filename, const char cpu_model)
	433	{
	434	if (!cpu_model) {
	435	cpu_model = "cortex-a9";
	436	}
	437	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	438	initrd_filename, cpu_model, BOARD_PBX_A9);
	439	}
	440
c988bfad PB	441	static QEMUMachine realview_eb_machine = {
c988bfad PB	442	.name = "realview-eb",
c9b1ae2c	443	.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
c988bfad PB	444	.init = realview_eb_init,
	445	.use_scsi = 1,
	446	};
	447
	448	static QEMUMachine realview_eb_mpcore_machine = {
	449	.name = "realview-eb-mpcore",
	450	.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
	451	.init = realview_eb_mpcore_init,
c9b1ae2c	452	.use_scsi = 1,
c988bfad	453	.max_cpus = 4,
e69954b9	454	};
f80f9ec9	455
0ef849d7 PB	456	static QEMUMachine realview_pb_a8_machine = {
	457	.name = "realview-pb-a8",
	458	.desc = "ARM RealView Platform Baseboard for Cortex-A8",
	459	.init = realview_pb_a8_init,
f7c70325 PB	460	};
	461
	462	static QEMUMachine realview_pbx_a9_machine = {
	463	.name = "realview-pbx-a9",
	464	.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
	465	.init = realview_pbx_a9_init,
0ef849d7	466	.use_scsi = 1,
f7c70325	467	.max_cpus = 4,
0ef849d7 PB	468	};
0ef849d7 PB	469
f80f9ec9 AL	470	static void realview_machine_init(void)
f80f9ec9 AL	471	{
c988bfad PB	472	qemu_register_machine(&realview_eb_machine);
c988bfad PB	473	qemu_register_machine(&realview_eb_mpcore_machine);
0ef849d7	474	qemu_register_machine(&realview_pb_a8_machine);
f7c70325	475	qemu_register_machine(&realview_pbx_a9_machine);
f80f9ec9 AL	476	}
	477
	478	machine_init(realview_machine_init);
eee48504	479	device_init(realview_register_devices)