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5fafdf24 | 1 | /* |
e69954b9 PB |
2 | * ARM RealView Baseboard System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
7 | * This code is licenced under the GPL. | |
8 | */ | |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b PB |
11 | #include "arm-misc.h" |
12 | #include "primecell.h" | |
13 | #include "devices.h" | |
14 | #include "pci.h" | |
18e08a55 | 15 | #include "usb-ohci.h" |
87ecb68b PB |
16 | #include "net.h" |
17 | #include "sysemu.h" | |
18 | #include "boards.h" | |
eee48504 PB |
19 | #include "bitbang_i2c.h" |
20 | #include "sysbus.h" | |
2446333c | 21 | #include "blockdev.h" |
e69954b9 | 22 | |
0ef849d7 | 23 | #define SMP_BOOT_ADDR 0xe0000000 |
eee48504 PB |
24 | |
25 | typedef struct { | |
26 | SysBusDevice busdev; | |
27 | bitbang_i2c_interface *bitbang; | |
28 | int out; | |
29 | int in; | |
30 | } RealViewI2CState; | |
31 | ||
32 | static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset) | |
33 | { | |
34 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
35 | ||
36 | if (offset == 0) { | |
37 | return (s->out & 1) | (s->in << 1); | |
38 | } else { | |
39 | hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset); | |
40 | return -1; | |
41 | } | |
42 | } | |
43 | ||
44 | static void realview_i2c_write(void *opaque, target_phys_addr_t offset, | |
45 | uint32_t value) | |
46 | { | |
47 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
48 | ||
49 | switch (offset) { | |
50 | case 0: | |
51 | s->out |= value & 3; | |
52 | break; | |
53 | case 4: | |
54 | s->out &= ~value; | |
55 | break; | |
56 | default: | |
57 | hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset); | |
58 | } | |
59 | bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); | |
60 | s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); | |
61 | } | |
62 | ||
63 | static CPUReadMemoryFunc * const realview_i2c_readfn[] = { | |
64 | realview_i2c_read, | |
65 | realview_i2c_read, | |
66 | realview_i2c_read | |
67 | }; | |
68 | ||
69 | static CPUWriteMemoryFunc * const realview_i2c_writefn[] = { | |
70 | realview_i2c_write, | |
71 | realview_i2c_write, | |
72 | realview_i2c_write | |
73 | }; | |
74 | ||
75 | static int realview_i2c_init(SysBusDevice *dev) | |
76 | { | |
77 | RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev); | |
78 | i2c_bus *bus; | |
79 | int iomemtype; | |
80 | ||
81 | bus = i2c_init_bus(&dev->qdev, "i2c"); | |
82 | s->bitbang = bitbang_i2c_init(bus); | |
83 | iomemtype = cpu_register_io_memory(realview_i2c_readfn, | |
2507c12a AG |
84 | realview_i2c_writefn, s, |
85 | DEVICE_NATIVE_ENDIAN); | |
eee48504 PB |
86 | sysbus_init_mmio(dev, 0x1000, iomemtype); |
87 | return 0; | |
88 | } | |
89 | ||
90 | static SysBusDeviceInfo realview_i2c_info = { | |
91 | .init = realview_i2c_init, | |
92 | .qdev.name = "realview_i2c", | |
93 | .qdev.size = sizeof(RealViewI2CState), | |
94 | }; | |
95 | ||
96 | static void realview_register_devices(void) | |
97 | { | |
98 | sysbus_register_withprop(&realview_i2c_info); | |
99 | } | |
100 | ||
e69954b9 PB |
101 | /* Board init. */ |
102 | ||
f93eb9ff | 103 | static struct arm_boot_info realview_binfo = { |
0ef849d7 | 104 | .smp_loader_start = SMP_BOOT_ADDR, |
f93eb9ff AZ |
105 | }; |
106 | ||
f7c70325 | 107 | /* The following two lists must be consistent. */ |
c988bfad PB |
108 | enum realview_board_type { |
109 | BOARD_EB, | |
0ef849d7 | 110 | BOARD_EB_MPCORE, |
f7c70325 PB |
111 | BOARD_PB_A8, |
112 | BOARD_PBX_A9, | |
113 | }; | |
114 | ||
d05ac8fa | 115 | static const int realview_board_id[] = { |
f7c70325 PB |
116 | 0x33b, |
117 | 0x33b, | |
118 | 0x769, | |
119 | 0x76d | |
c988bfad PB |
120 | }; |
121 | ||
c227f099 | 122 | static void realview_init(ram_addr_t ram_size, |
3023f332 | 123 | const char *boot_device, |
e69954b9 | 124 | const char *kernel_filename, const char *kernel_cmdline, |
c988bfad PB |
125 | const char *initrd_filename, const char *cpu_model, |
126 | enum realview_board_type board_type) | |
e69954b9 | 127 | { |
c988bfad | 128 | CPUState *env = NULL; |
c227f099 | 129 | ram_addr_t ram_offset; |
26883c69 | 130 | DeviceState *dev, *sysctl, *gpio2; |
c988bfad | 131 | SysBusDevice *busdev; |
fe7e8758 PB |
132 | qemu_irq *irqp; |
133 | qemu_irq pic[64]; | |
26883c69 | 134 | qemu_irq mmc_irq[2]; |
e69954b9 PB |
135 | PCIBus *pci_bus; |
136 | NICInfo *nd; | |
eee48504 | 137 | i2c_bus *i2c; |
e69954b9 | 138 | int n; |
0ef849d7 | 139 | int done_nic = 0; |
9ee6e8bb | 140 | qemu_irq cpu_irq[4]; |
f7c70325 PB |
141 | int is_mpcore = 0; |
142 | int is_pb = 0; | |
26e92f65 | 143 | uint32_t proc_id = 0; |
0ef849d7 PB |
144 | uint32_t sys_id; |
145 | ram_addr_t low_ram_size; | |
e69954b9 | 146 | |
f7c70325 PB |
147 | switch (board_type) { |
148 | case BOARD_EB: | |
149 | break; | |
150 | case BOARD_EB_MPCORE: | |
151 | is_mpcore = 1; | |
152 | break; | |
153 | case BOARD_PB_A8: | |
154 | is_pb = 1; | |
155 | break; | |
156 | case BOARD_PBX_A9: | |
157 | is_mpcore = 1; | |
158 | is_pb = 1; | |
159 | break; | |
160 | } | |
c988bfad | 161 | for (n = 0; n < smp_cpus; n++) { |
9ee6e8bb PB |
162 | env = cpu_init(cpu_model); |
163 | if (!env) { | |
164 | fprintf(stderr, "Unable to find CPU definition\n"); | |
165 | exit(1); | |
166 | } | |
fe7e8758 PB |
167 | irqp = arm_pic_init_cpu(env); |
168 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; | |
aaed909a | 169 | } |
26e92f65 | 170 | if (arm_feature(env, ARM_FEATURE_V7)) { |
f7c70325 PB |
171 | if (is_mpcore) { |
172 | proc_id = 0x0c000000; | |
173 | } else { | |
174 | proc_id = 0x0e000000; | |
175 | } | |
26e92f65 PB |
176 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { |
177 | proc_id = 0x06000000; | |
178 | } else if (arm_feature(env, ARM_FEATURE_V6)) { | |
179 | proc_id = 0x04000000; | |
180 | } else { | |
181 | proc_id = 0x02000000; | |
182 | } | |
aaed909a | 183 | |
21a88941 PB |
184 | if (is_pb && ram_size > 0x20000000) { |
185 | /* Core tile RAM. */ | |
186 | low_ram_size = ram_size - 0x20000000; | |
187 | ram_size = 0x20000000; | |
1724f049 | 188 | ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size); |
21a88941 PB |
189 | cpu_register_physical_memory(0x20000000, low_ram_size, |
190 | ram_offset | IO_MEM_RAM); | |
191 | } | |
192 | ||
1724f049 | 193 | ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size); |
0ef849d7 PB |
194 | low_ram_size = ram_size; |
195 | if (low_ram_size > 0x10000000) | |
196 | low_ram_size = 0x10000000; | |
e69954b9 | 197 | /* SDRAM at address zero. */ |
0ef849d7 PB |
198 | cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM); |
199 | if (is_pb) { | |
200 | /* And again at a high address. */ | |
201 | cpu_register_physical_memory(0x70000000, ram_size, | |
202 | ram_offset | IO_MEM_RAM); | |
203 | } else { | |
204 | ram_size = low_ram_size; | |
205 | } | |
e69954b9 | 206 | |
0ef849d7 | 207 | sys_id = is_pb ? 0x01780500 : 0xc1400400; |
26883c69 PM |
208 | sysctl = qdev_create(NULL, "realview_sysctl"); |
209 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
210 | qdev_init_nofail(sysctl); | |
211 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); | |
212 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); | |
9ee6e8bb | 213 | |
c988bfad | 214 | if (is_mpcore) { |
f7c70325 | 215 | dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); |
c988bfad PB |
216 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
217 | qdev_init_nofail(dev); | |
218 | busdev = sysbus_from_qdev(dev); | |
f7c70325 PB |
219 | if (is_pb) { |
220 | realview_binfo.smp_priv_base = 0x1f000000; | |
221 | } else { | |
222 | realview_binfo.smp_priv_base = 0x10100000; | |
223 | } | |
224 | sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base); | |
c988bfad PB |
225 | for (n = 0; n < smp_cpus; n++) { |
226 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
227 | } | |
9ee6e8bb | 228 | } else { |
0ef849d7 PB |
229 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; |
230 | /* For now just create the nIRQ GIC, and ignore the others. */ | |
231 | dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); | |
fe7e8758 PB |
232 | } |
233 | for (n = 0; n < 64; n++) { | |
067a3ddc | 234 | pic[n] = qdev_get_gpio_in(dev, n); |
9ee6e8bb PB |
235 | } |
236 | ||
86394e96 PB |
237 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); |
238 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); | |
e69954b9 | 239 | |
a7d518a6 PB |
240 | sysbus_create_simple("pl011", 0x10009000, pic[12]); |
241 | sysbus_create_simple("pl011", 0x1000a000, pic[13]); | |
242 | sysbus_create_simple("pl011", 0x1000b000, pic[14]); | |
243 | sysbus_create_simple("pl011", 0x1000c000, pic[15]); | |
e69954b9 PB |
244 | |
245 | /* DMA controller is optional, apparently. */ | |
b4496b13 | 246 | sysbus_create_simple("pl081", 0x10030000, pic[24]); |
e69954b9 | 247 | |
6a824ec3 PB |
248 | sysbus_create_simple("sp804", 0x10011000, pic[4]); |
249 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | |
e69954b9 | 250 | |
26883c69 PM |
251 | sysbus_create_simple("pl061", 0x10013000, pic[6]); |
252 | sysbus_create_simple("pl061", 0x10014000, pic[7]); | |
253 | gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); | |
254 | ||
2e9bdce5 | 255 | sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]); |
e69954b9 | 256 | |
26883c69 PM |
257 | dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); |
258 | /* Wire up MMC card detect and read-only signals. These have | |
259 | * to go to both the PL061 GPIO and the sysctl register. | |
260 | * Note that the PL181 orders these lines (readonly,inserted) | |
261 | * and the PL061 has them the other way about. Also the card | |
262 | * detect line is inverted. | |
263 | */ | |
264 | mmc_irq[0] = qemu_irq_split( | |
265 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | |
266 | qdev_get_gpio_in(gpio2, 1)); | |
267 | mmc_irq[1] = qemu_irq_split( | |
268 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | |
269 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | |
270 | qdev_connect_gpio_out(dev, 0, mmc_irq[0]); | |
271 | qdev_connect_gpio_out(dev, 1, mmc_irq[1]); | |
a1bb27b1 | 272 | |
a63bdb31 | 273 | sysbus_create_simple("pl031", 0x10017000, pic[10]); |
7e1543c2 | 274 | |
0ef849d7 PB |
275 | if (!is_pb) { |
276 | dev = sysbus_create_varargs("realview_pci", 0x60000000, | |
277 | pic[48], pic[49], pic[50], pic[51], NULL); | |
278 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); | |
279 | if (usb_enabled) { | |
a67ba3b6 | 280 | usb_ohci_init_pci(pci_bus, -1); |
0ef849d7 PB |
281 | } |
282 | n = drive_get_max_bus(IF_SCSI); | |
283 | while (n >= 0) { | |
284 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
285 | n--; | |
286 | } | |
e69954b9 PB |
287 | } |
288 | for(n = 0; n < nb_nics; n++) { | |
289 | nd = &nd_table[n]; | |
0ae18cee | 290 | |
0ef849d7 PB |
291 | if ((!nd->model && !done_nic) |
292 | || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) { | |
293 | if (is_pb) { | |
294 | lan9118_init(nd, 0x4e000000, pic[28]); | |
295 | } else { | |
296 | smc91c111_init(nd, 0x4e000000, pic[28]); | |
297 | } | |
298 | done_nic = 1; | |
e69954b9 | 299 | } else { |
07caea31 | 300 | pci_nic_init_nofail(nd, "rtl8139", NULL); |
e69954b9 PB |
301 | } |
302 | } | |
303 | ||
eee48504 PB |
304 | dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL); |
305 | i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); | |
306 | i2c_create_slave(i2c, "ds1338", 0x68); | |
307 | ||
e69954b9 PB |
308 | /* Memory map for RealView Emulation Baseboard: */ |
309 | /* 0x10000000 System registers. */ | |
310 | /* 0x10001000 System controller. */ | |
eee48504 | 311 | /* 0x10002000 Two-Wire Serial Bus. */ |
e69954b9 PB |
312 | /* 0x10003000 Reserved. */ |
313 | /* 0x10004000 AACI. */ | |
314 | /* 0x10005000 MCI. */ | |
315 | /* 0x10006000 KMI0. */ | |
316 | /* 0x10007000 KMI1. */ | |
0ef849d7 | 317 | /* 0x10008000 Character LCD. (EB) */ |
e69954b9 PB |
318 | /* 0x10009000 UART0. */ |
319 | /* 0x1000a000 UART1. */ | |
320 | /* 0x1000b000 UART2. */ | |
321 | /* 0x1000c000 UART3. */ | |
322 | /* 0x1000d000 SSPI. */ | |
323 | /* 0x1000e000 SCI. */ | |
324 | /* 0x1000f000 Reserved. */ | |
325 | /* 0x10010000 Watchdog. */ | |
326 | /* 0x10011000 Timer 0+1. */ | |
327 | /* 0x10012000 Timer 2+3. */ | |
328 | /* 0x10013000 GPIO 0. */ | |
329 | /* 0x10014000 GPIO 1. */ | |
330 | /* 0x10015000 GPIO 2. */ | |
0ef849d7 | 331 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ |
7e1543c2 | 332 | /* 0x10017000 RTC. */ |
e69954b9 PB |
333 | /* 0x10018000 DMC. */ |
334 | /* 0x10019000 PCI controller config. */ | |
335 | /* 0x10020000 CLCD. */ | |
336 | /* 0x10030000 DMA Controller. */ | |
0ef849d7 PB |
337 | /* 0x10040000 GIC1. (EB) */ |
338 | /* 0x10050000 GIC2. (EB) */ | |
339 | /* 0x10060000 GIC3. (EB) */ | |
340 | /* 0x10070000 GIC4. (EB) */ | |
e69954b9 | 341 | /* 0x10080000 SMC. */ |
0ef849d7 PB |
342 | /* 0x1e000000 GIC1. (PB) */ |
343 | /* 0x1e001000 GIC2. (PB) */ | |
344 | /* 0x1e002000 GIC3. (PB) */ | |
345 | /* 0x1e003000 GIC4. (PB) */ | |
e69954b9 PB |
346 | /* 0x40000000 NOR flash. */ |
347 | /* 0x44000000 DoC flash. */ | |
348 | /* 0x48000000 SRAM. */ | |
349 | /* 0x4c000000 Configuration flash. */ | |
350 | /* 0x4e000000 Ethernet. */ | |
351 | /* 0x4f000000 USB. */ | |
352 | /* 0x50000000 PISMO. */ | |
353 | /* 0x54000000 PISMO. */ | |
354 | /* 0x58000000 PISMO. */ | |
355 | /* 0x5c000000 PISMO. */ | |
356 | /* 0x60000000 PCI. */ | |
357 | /* 0x61000000 PCI Self Config. */ | |
358 | /* 0x62000000 PCI Config. */ | |
359 | /* 0x63000000 PCI IO. */ | |
360 | /* 0x64000000 PCI mem 0. */ | |
361 | /* 0x68000000 PCI mem 1. */ | |
362 | /* 0x6c000000 PCI mem 2. */ | |
363 | ||
7ffab4d7 PB |
364 | /* ??? Hack to map an additional page of ram for the secondary CPU |
365 | startup code. I guess this works on real hardware because the | |
366 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
367 | until after Linux boots the secondary CPUs. */ | |
1724f049 | 368 | ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000); |
0ef849d7 PB |
369 | cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000, |
370 | ram_offset | IO_MEM_RAM); | |
7ffab4d7 | 371 | |
f93eb9ff AZ |
372 | realview_binfo.ram_size = ram_size; |
373 | realview_binfo.kernel_filename = kernel_filename; | |
374 | realview_binfo.kernel_cmdline = kernel_cmdline; | |
375 | realview_binfo.initrd_filename = initrd_filename; | |
c988bfad | 376 | realview_binfo.nb_cpus = smp_cpus; |
f7c70325 | 377 | realview_binfo.board_id = realview_board_id[board_type]; |
21a88941 | 378 | realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); |
f93eb9ff | 379 | arm_load_kernel(first_cpu, &realview_binfo); |
e69954b9 PB |
380 | } |
381 | ||
c988bfad PB |
382 | static void realview_eb_init(ram_addr_t ram_size, |
383 | const char *boot_device, | |
384 | const char *kernel_filename, const char *kernel_cmdline, | |
385 | const char *initrd_filename, const char *cpu_model) | |
386 | { | |
387 | if (!cpu_model) { | |
388 | cpu_model = "arm926"; | |
389 | } | |
390 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
391 | initrd_filename, cpu_model, BOARD_EB); | |
392 | } | |
393 | ||
394 | static void realview_eb_mpcore_init(ram_addr_t ram_size, | |
395 | const char *boot_device, | |
396 | const char *kernel_filename, const char *kernel_cmdline, | |
397 | const char *initrd_filename, const char *cpu_model) | |
398 | { | |
399 | if (!cpu_model) { | |
400 | cpu_model = "arm11mpcore"; | |
401 | } | |
402 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
403 | initrd_filename, cpu_model, BOARD_EB_MPCORE); | |
404 | } | |
405 | ||
0ef849d7 PB |
406 | static void realview_pb_a8_init(ram_addr_t ram_size, |
407 | const char *boot_device, | |
408 | const char *kernel_filename, const char *kernel_cmdline, | |
409 | const char *initrd_filename, const char *cpu_model) | |
410 | { | |
411 | if (!cpu_model) { | |
412 | cpu_model = "cortex-a8"; | |
413 | } | |
414 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
415 | initrd_filename, cpu_model, BOARD_PB_A8); | |
416 | } | |
417 | ||
f7c70325 PB |
418 | static void realview_pbx_a9_init(ram_addr_t ram_size, |
419 | const char *boot_device, | |
420 | const char *kernel_filename, const char *kernel_cmdline, | |
421 | const char *initrd_filename, const char *cpu_model) | |
422 | { | |
423 | if (!cpu_model) { | |
424 | cpu_model = "cortex-a9"; | |
425 | } | |
426 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
427 | initrd_filename, cpu_model, BOARD_PBX_A9); | |
428 | } | |
429 | ||
c988bfad PB |
430 | static QEMUMachine realview_eb_machine = { |
431 | .name = "realview-eb", | |
c9b1ae2c | 432 | .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", |
c988bfad PB |
433 | .init = realview_eb_init, |
434 | .use_scsi = 1, | |
435 | }; | |
436 | ||
437 | static QEMUMachine realview_eb_mpcore_machine = { | |
438 | .name = "realview-eb-mpcore", | |
439 | .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", | |
440 | .init = realview_eb_mpcore_init, | |
c9b1ae2c | 441 | .use_scsi = 1, |
c988bfad | 442 | .max_cpus = 4, |
e69954b9 | 443 | }; |
f80f9ec9 | 444 | |
0ef849d7 PB |
445 | static QEMUMachine realview_pb_a8_machine = { |
446 | .name = "realview-pb-a8", | |
447 | .desc = "ARM RealView Platform Baseboard for Cortex-A8", | |
448 | .init = realview_pb_a8_init, | |
f7c70325 PB |
449 | }; |
450 | ||
451 | static QEMUMachine realview_pbx_a9_machine = { | |
452 | .name = "realview-pbx-a9", | |
453 | .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", | |
454 | .init = realview_pbx_a9_init, | |
0ef849d7 | 455 | .use_scsi = 1, |
f7c70325 | 456 | .max_cpus = 4, |
0ef849d7 PB |
457 | }; |
458 | ||
f80f9ec9 AL |
459 | static void realview_machine_init(void) |
460 | { | |
c988bfad PB |
461 | qemu_register_machine(&realview_eb_machine); |
462 | qemu_register_machine(&realview_eb_mpcore_machine); | |
0ef849d7 | 463 | qemu_register_machine(&realview_pb_a8_machine); |
f7c70325 | 464 | qemu_register_machine(&realview_pbx_a9_machine); |
f80f9ec9 AL |
465 | } |
466 | ||
467 | machine_init(realview_machine_init); | |
eee48504 | 468 | device_init(realview_register_devices) |