[qemu.git] / hw / realview.c

/*
 * ARM RealView Baseboard System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "pci.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
#include "bitbang_i2c.h"
#include "sysbus.h"

#define SMP_BOOT_ADDR 0xe0000000

typedef struct {
    SysBusDevice busdev;
    bitbang_i2c_interface *bitbang;
    int out;
    int in;
} RealViewI2CState;

static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    if (offset == 0) {
        return (s->out & 1) | (s->in << 1);
    } else {
        hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
        return -1;
    }
}

static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
                               uint32_t value)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    switch (offset) {
    case 0:
        s->out |= value & 3;
        break;
    case 4:
        s->out &= ~value;
        break;
    default:
        hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
    }
    bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
    s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
}

static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
   realview_i2c_read,
   realview_i2c_read,
   realview_i2c_read
};

static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
   realview_i2c_write,
   realview_i2c_write,
   realview_i2c_write
};

static int realview_i2c_init(SysBusDevice *dev)
{
    RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
    i2c_bus *bus;
    int iomemtype;

    bus = i2c_init_bus(&dev->qdev, "i2c");
    s->bitbang = bitbang_i2c_init(bus);
    iomemtype = cpu_register_io_memory(realview_i2c_readfn,
                                       realview_i2c_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    return 0;
}

static SysBusDeviceInfo realview_i2c_info = {
    .init = realview_i2c_init,
    .qdev.name  = "realview_i2c",
    .qdev.size  = sizeof(RealViewI2CState),
};

static void realview_register_devices(void)
{
    sysbus_register_withprop(&realview_i2c_info);
}

/* Board init.  */

static struct arm_boot_info realview_binfo = {
    .smp_loader_start = SMP_BOOT_ADDR,
};

static void secondary_cpu_reset(void *opaque)
{
  CPUState *env = opaque;

  cpu_reset(env);
  /* Set entry point for secondary CPUs.  This assumes we're using
     the init code from arm_boot.c.  Real hardware resets all CPUs
     the same.  */
  env->regs[15] = SMP_BOOT_ADDR;
}

/* The following two lists must be consistent.  */
enum realview_board_type {
    BOARD_EB,
    BOARD_EB_MPCORE,
    BOARD_PB_A8,
    BOARD_PBX_A9,
};

int realview_board_id[] = {
    0x33b,
    0x33b,
    0x769,
    0x76d
};

static void realview_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     enum realview_board_type board_type)
{
    CPUState *env = NULL;
    ram_addr_t ram_offset;
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq *irqp;
    qemu_irq pic[64];
    PCIBus *pci_bus;
    NICInfo *nd;
    i2c_bus *i2c;
    int n;
    int done_nic = 0;
    qemu_irq cpu_irq[4];
    int is_mpcore = 0;
    int is_pb = 0;
    uint32_t proc_id = 0;
    uint32_t sys_id;
    ram_addr_t low_ram_size;

    switch (board_type) {
    case BOARD_EB:
        break;
    case BOARD_EB_MPCORE:
        is_mpcore = 1;
        break;
    case BOARD_PB_A8:
        is_pb = 1;
        break;
    case BOARD_PBX_A9:
        is_mpcore = 1;
        is_pb = 1;
        break;
    }
    for (n = 0; n < smp_cpus; n++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }
        irqp = arm_pic_init_cpu(env);
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
        if (n > 0) {
            qemu_register_reset(secondary_cpu_reset, env);
        }
    }
    if (arm_feature(env, ARM_FEATURE_V7)) {
        if (is_mpcore) {
            proc_id = 0x0c000000;
        } else {
            proc_id = 0x0e000000;
        }
    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
        proc_id = 0x06000000;
    } else if (arm_feature(env, ARM_FEATURE_V6)) {
        proc_id = 0x04000000;
    } else {
        proc_id = 0x02000000;
    }

    ram_offset = qemu_ram_alloc(ram_size);
    low_ram_size = ram_size;
    if (low_ram_size > 0x10000000)
      low_ram_size = 0x10000000;
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
    if (is_pb) {
        /* And again at a high address.  */
        cpu_register_physical_memory(0x70000000, ram_size,
                                     ram_offset | IO_MEM_RAM);
    } else {
        ram_size = low_ram_size;
    }

    sys_id = is_pb ? 0x01780500 : 0xc1400400;
    arm_sysctl_init(0x10000000, sys_id, proc_id);

    if (is_mpcore) {
        dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
        qdev_init_nofail(dev);
        busdev = sysbus_from_qdev(dev);
        if (is_pb) {
            realview_binfo.smp_priv_base = 0x1f000000;
        } else {
            realview_binfo.smp_priv_base = 0x10100000;
        }
        sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
        for (n = 0; n < smp_cpus; n++) {
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
        }
    } else {
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
        /* For now just create the nIRQ GIC, and ignore the others.  */
        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
    }
    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);

    sysbus_create_simple("pl011", 0x10009000, pic[12]);
    sysbus_create_simple("pl011", 0x1000a000, pic[13]);
    sysbus_create_simple("pl011", 0x1000b000, pic[14]);
    sysbus_create_simple("pl011", 0x1000c000, pic[15]);

    /* DMA controller is optional, apparently.  */
    sysbus_create_simple("pl081", 0x10030000, pic[24]);

    sysbus_create_simple("sp804", 0x10011000, pic[4]);
    sysbus_create_simple("sp804", 0x10012000, pic[5]);

    sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);

    sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);

    sysbus_create_simple("pl031", 0x10017000, pic[10]);

    if (!is_pb) {
        dev = sysbus_create_varargs("realview_pci", 0x60000000,
                                    pic[48], pic[49], pic[50], pic[51], NULL);
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
        if (usb_enabled) {
            usb_ohci_init_pci(pci_bus, -1);
        }
        n = drive_get_max_bus(IF_SCSI);
        while (n >= 0) {
            pci_create_simple(pci_bus, -1, "lsi53c895a");
            n--;
        }
    }
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if ((!nd->model && !done_nic)
            || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
            if (is_pb) {
                lan9118_init(nd, 0x4e000000, pic[28]);
            } else {
                smc91c111_init(nd, 0x4e000000, pic[28]);
            }
            done_nic = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }

    dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
    i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Memory map for RealView Emulation Baseboard:  */
    /* 0x10000000 System registers.  */
    /*  0x10001000 System controller.  */
    /* 0x10002000 Two-Wire Serial Bus.  */
    /* 0x10003000 Reserved.  */
    /*  0x10004000 AACI.  */
    /*  0x10005000 MCI.  */
    /* 0x10006000 KMI0.  */
    /* 0x10007000 KMI1.  */
    /*  0x10008000 Character LCD. (EB) */
    /* 0x10009000 UART0.  */
    /* 0x1000a000 UART1.  */
    /* 0x1000b000 UART2.  */
    /* 0x1000c000 UART3.  */
    /*  0x1000d000 SSPI.  */
    /*  0x1000e000 SCI.  */
    /* 0x1000f000 Reserved.  */
    /*  0x10010000 Watchdog.  */
    /* 0x10011000 Timer 0+1.  */
    /* 0x10012000 Timer 2+3.  */
    /*  0x10013000 GPIO 0.  */
    /*  0x10014000 GPIO 1.  */
    /*  0x10015000 GPIO 2.  */
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
    /* 0x10017000 RTC.  */
    /*  0x10018000 DMC.  */
    /*  0x10019000 PCI controller config.  */
    /*  0x10020000 CLCD.  */
    /* 0x10030000 DMA Controller.  */
    /* 0x10040000 GIC1. (EB) */
    /*  0x10050000 GIC2. (EB) */
    /*  0x10060000 GIC3. (EB) */
    /*  0x10070000 GIC4. (EB) */
    /*  0x10080000 SMC.  */
    /* 0x1e000000 GIC1. (PB) */
    /*  0x1e001000 GIC2. (PB) */
    /*  0x1e002000 GIC3. (PB) */
    /*  0x1e003000 GIC4. (PB) */
    /*  0x40000000 NOR flash.  */
    /*  0x44000000 DoC flash.  */
    /*  0x48000000 SRAM.  */
    /*  0x4c000000 Configuration flash.  */
    /* 0x4e000000 Ethernet.  */
    /*  0x4f000000 USB.  */
    /*  0x50000000 PISMO.  */
    /*  0x54000000 PISMO.  */
    /*  0x58000000 PISMO.  */
    /*  0x5c000000 PISMO.  */
    /* 0x60000000 PCI.  */
    /* 0x61000000 PCI Self Config.  */
    /* 0x62000000 PCI Config.  */
    /* 0x63000000 PCI IO.  */
    /* 0x64000000 PCI mem 0.  */
    /* 0x68000000 PCI mem 1.  */
    /* 0x6c000000 PCI mem 2.  */

    /* ??? Hack to map an additional page of ram for the secondary CPU
       startup code.  I guess this works on real hardware because the
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
       until after Linux boots the secondary CPUs.  */
    ram_offset = qemu_ram_alloc(0x1000);
    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
                                 ram_offset | IO_MEM_RAM);

    realview_binfo.ram_size = ram_size;
    realview_binfo.kernel_filename = kernel_filename;
    realview_binfo.kernel_cmdline = kernel_cmdline;
    realview_binfo.initrd_filename = initrd_filename;
    realview_binfo.nb_cpus = smp_cpus;
    realview_binfo.board_id = realview_board_id[board_type];
    realview_binfo.loader_start = is_pb ? 0x70000000 : 0;
    arm_load_kernel(first_cpu, &realview_binfo);
}

static void realview_eb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm926";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB);
}

static void realview_eb_mpcore_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm11mpcore";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
}

static void realview_pb_a8_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a8";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PB_A8);
}

static void realview_pbx_a9_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PBX_A9);
}

static QEMUMachine realview_eb_machine = {
    .name = "realview-eb",
    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
    .init = realview_eb_init,
    .use_scsi = 1,
};

static QEMUMachine realview_eb_mpcore_machine = {
    .name = "realview-eb-mpcore",
    .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
    .init = realview_eb_mpcore_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static QEMUMachine realview_pb_a8_machine = {
    .name = "realview-pb-a8",
    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
    .init = realview_pb_a8_init,
};

static QEMUMachine realview_pbx_a9_machine = {
    .name = "realview-pbx-a9",
    .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
    .init = realview_pbx_a9_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static void realview_machine_init(void)
{
    qemu_register_machine(&realview_eb_machine);
    qemu_register_machine(&realview_eb_mpcore_machine);
    qemu_register_machine(&realview_pb_a8_machine);
    qemu_register_machine(&realview_pbx_a9_machine);
}

machine_init(realview_machine_init);
device_init(realview_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* ARM RealView Baseboard System emulation.
e69954b9 PB	3	*
a1bb27b1	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "pci.h"
	15	#include "net.h"
	16	#include "sysemu.h"
	17	#include "boards.h"
eee48504 PB	18	#include "bitbang_i2c.h"
eee48504 PB	19	#include "sysbus.h"
e69954b9	20
0ef849d7	21	#define SMP_BOOT_ADDR 0xe0000000
eee48504 PB	22
	23	typedef struct {
	24	SysBusDevice busdev;
	25	bitbang_i2c_interface *bitbang;
	26	int out;
	27	int in;
	28	} RealViewI2CState;
	29
	30	static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
	31	{
	32	RealViewI2CState s = (RealViewI2CState )opaque;
	33
	34	if (offset == 0) {
	35	return (s->out & 1) \| (s->in << 1);
	36	} else {
	37	hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
	38	return -1;
	39	}
	40	}
	41
	42	static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
	43	uint32_t value)
	44	{
	45	RealViewI2CState s = (RealViewI2CState )opaque;
	46
	47	switch (offset) {
	48	case 0:
	49	s->out \|= value & 3;
	50	break;
	51	case 4:
	52	s->out &= ~value;
	53	break;
	54	default:
	55	hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
	56	}
	57	bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
	58	s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
	59	}
	60
	61	static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
	62	realview_i2c_read,
	63	realview_i2c_read,
	64	realview_i2c_read
	65	};
	66
	67	static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
	68	realview_i2c_write,
	69	realview_i2c_write,
	70	realview_i2c_write
	71	};
	72
	73	static int realview_i2c_init(SysBusDevice *dev)
	74	{
	75	RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
	76	i2c_bus *bus;
	77	int iomemtype;
	78
	79	bus = i2c_init_bus(&dev->qdev, "i2c");
	80	s->bitbang = bitbang_i2c_init(bus);
	81	iomemtype = cpu_register_io_memory(realview_i2c_readfn,
	82	realview_i2c_writefn, s);
	83	sysbus_init_mmio(dev, 0x1000, iomemtype);
	84	return 0;
	85	}
86
87	static SysBusDeviceInfo realview_i2c_info = {
88	.init = realview_i2c_init,
89	.qdev.name = "realview_i2c",
90	.qdev.size = sizeof(RealViewI2CState),
91	};
92
93	static void realview_register_devices(void)
94	{
95	sysbus_register_withprop(&realview_i2c_info);
96	}
97
e69954b9 PB	98	/* Board init. */
e69954b9 PB	99
f93eb9ff	100	static struct arm_boot_info realview_binfo = {
0ef849d7	101	.smp_loader_start = SMP_BOOT_ADDR,
f93eb9ff AZ	102	};
f93eb9ff AZ	103
be0f204a PB	104	static void secondary_cpu_reset(void *opaque)
	105	{
	106	CPUState *env = opaque;
	107
	108	cpu_reset(env);
	109	/* Set entry point for secondary CPUs. This assumes we're using
	110	the init code from arm_boot.c. Real hardware resets all CPUs
	111	the same. */
0ef849d7	112	env->regs[15] = SMP_BOOT_ADDR;
be0f204a PB	113	}
be0f204a PB	114
f7c70325	115	/* The following two lists must be consistent. */
c988bfad PB	116	enum realview_board_type {
c988bfad PB	117	BOARD_EB,
0ef849d7	118	BOARD_EB_MPCORE,
f7c70325 PB	119	BOARD_PB_A8,
	120	BOARD_PBX_A9,
	121	};
	122
	123	int realview_board_id[] = {
	124	0x33b,
	125	0x33b,
	126	0x769,
	127	0x76d
c988bfad PB	128	};
c988bfad PB	129
c227f099	130	static void realview_init(ram_addr_t ram_size,
3023f332	131	const char *boot_device,
e69954b9	132	const char kernel_filename, const char kernel_cmdline,
c988bfad PB	133	const char initrd_filename, const char cpu_model,
c988bfad PB	134	enum realview_board_type board_type)
e69954b9	135	{
c988bfad	136	CPUState *env = NULL;
c227f099	137	ram_addr_t ram_offset;
0027b06d	138	DeviceState *dev;
c988bfad	139	SysBusDevice *busdev;
fe7e8758 PB	140	qemu_irq *irqp;
fe7e8758 PB	141	qemu_irq pic[64];
e69954b9 PB	142	PCIBus *pci_bus;
e69954b9 PB	143	NICInfo *nd;
eee48504	144	i2c_bus *i2c;
e69954b9	145	int n;
0ef849d7	146	int done_nic = 0;
9ee6e8bb	147	qemu_irq cpu_irq[4];
f7c70325 PB	148	int is_mpcore = 0;
f7c70325 PB	149	int is_pb = 0;
26e92f65	150	uint32_t proc_id = 0;
0ef849d7 PB	151	uint32_t sys_id;
0ef849d7 PB	152	ram_addr_t low_ram_size;
e69954b9	153
f7c70325 PB	154	switch (board_type) {
	155	case BOARD_EB:
	156	break;
	157	case BOARD_EB_MPCORE:
	158	is_mpcore = 1;
	159	break;
	160	case BOARD_PB_A8:
	161	is_pb = 1;
	162	break;
	163	case BOARD_PBX_A9:
	164	is_mpcore = 1;
	165	is_pb = 1;
	166	break;
	167	}
c988bfad	168	for (n = 0; n < smp_cpus; n++) {
9ee6e8bb PB	169	env = cpu_init(cpu_model);
	170	if (!env) {
	171	fprintf(stderr, "Unable to find CPU definition\n");
	172	exit(1);
	173	}
fe7e8758 PB	174	irqp = arm_pic_init_cpu(env);
fe7e8758 PB	175	cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
9ee6e8bb	176	if (n > 0) {
be0f204a	177	qemu_register_reset(secondary_cpu_reset, env);
9ee6e8bb	178	}
aaed909a	179	}
26e92f65	180	if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325 PB	181	if (is_mpcore) {
	182	proc_id = 0x0c000000;
	183	} else {
	184	proc_id = 0x0e000000;
	185	}
26e92f65 PB	186	} else if (arm_feature(env, ARM_FEATURE_V6K)) {
	187	proc_id = 0x06000000;
	188	} else if (arm_feature(env, ARM_FEATURE_V6)) {
	189	proc_id = 0x04000000;
	190	} else {
	191	proc_id = 0x02000000;
	192	}
aaed909a	193
7ffab4d7	194	ram_offset = qemu_ram_alloc(ram_size);
0ef849d7 PB	195	low_ram_size = ram_size;
	196	if (low_ram_size > 0x10000000)
	197	low_ram_size = 0x10000000;
1235fc06	198	/* ??? RAM should repeat to fill physical memory space. */
e69954b9	199	/* SDRAM at address zero. */
0ef849d7 PB	200	cpu_register_physical_memory(0, low_ram_size, ram_offset \| IO_MEM_RAM);
	201	if (is_pb) {
	202	/* And again at a high address. */
	203	cpu_register_physical_memory(0x70000000, ram_size,
	204	ram_offset \| IO_MEM_RAM);
	205	} else {
	206	ram_size = low_ram_size;
	207	}
e69954b9	208
0ef849d7 PB	209	sys_id = is_pb ? 0x01780500 : 0xc1400400;
0ef849d7 PB	210	arm_sysctl_init(0x10000000, sys_id, proc_id);
9ee6e8bb	211
c988bfad	212	if (is_mpcore) {
f7c70325	213	dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
c988bfad PB	214	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	215	qdev_init_nofail(dev);
	216	busdev = sysbus_from_qdev(dev);
f7c70325 PB	217	if (is_pb) {
	218	realview_binfo.smp_priv_base = 0x1f000000;
	219	} else {
	220	realview_binfo.smp_priv_base = 0x10100000;
	221	}
	222	sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
c988bfad PB	223	for (n = 0; n < smp_cpus; n++) {
	224	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	225	}
9ee6e8bb	226	} else {
0ef849d7 PB	227	uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
	228	/* For now just create the nIRQ GIC, and ignore the others. */
	229	dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
fe7e8758 PB	230	}
fe7e8758 PB	231	for (n = 0; n < 64; n++) {
067a3ddc	232	pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb PB	233	}
9ee6e8bb PB	234
86394e96 PB	235	sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
86394e96 PB	236	sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9	237
a7d518a6 PB	238	sysbus_create_simple("pl011", 0x10009000, pic[12]);
	239	sysbus_create_simple("pl011", 0x1000a000, pic[13]);
	240	sysbus_create_simple("pl011", 0x1000b000, pic[14]);
	241	sysbus_create_simple("pl011", 0x1000c000, pic[15]);
e69954b9 PB	242
e69954b9 PB	243	/* DMA controller is optional, apparently. */
b4496b13	244	sysbus_create_simple("pl081", 0x10030000, pic[24]);
e69954b9	245
6a824ec3 PB	246	sysbus_create_simple("sp804", 0x10011000, pic[4]);
6a824ec3 PB	247	sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9	248
2e9bdce5	249	sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
e69954b9	250
aa9311d8	251	sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
a1bb27b1	252
a63bdb31	253	sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2	254
0ef849d7 PB	255	if (!is_pb) {
	256	dev = sysbus_create_varargs("realview_pci", 0x60000000,
	257	pic[48], pic[49], pic[50], pic[51], NULL);
	258	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
	259	if (usb_enabled) {
	260	usb_ohci_init_pci(pci_bus, -1);
	261	}
	262	n = drive_get_max_bus(IF_SCSI);
	263	while (n >= 0) {
	264	pci_create_simple(pci_bus, -1, "lsi53c895a");
	265	n--;
	266	}
e69954b9 PB	267	}
	268	for(n = 0; n < nb_nics; n++) {
	269	nd = &nd_table[n];
0ae18cee	270
0ef849d7 PB	271	if ((!nd->model && !done_nic)
	272	\|\| strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
	273	if (is_pb) {
	274	lan9118_init(nd, 0x4e000000, pic[28]);
	275	} else {
	276	smc91c111_init(nd, 0x4e000000, pic[28]);
	277	}
	278	done_nic = 1;
e69954b9	279	} else {
07caea31	280	pci_nic_init_nofail(nd, "rtl8139", NULL);
e69954b9 PB	281	}
	282	}
	283
eee48504 PB	284	dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
	285	i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
	286	i2c_create_slave(i2c, "ds1338", 0x68);
	287
e69954b9 PB	288	/* Memory map for RealView Emulation Baseboard: */
	289	/* 0x10000000 System registers. */
	290	/* 0x10001000 System controller. */
eee48504	291	/* 0x10002000 Two-Wire Serial Bus. */
e69954b9 PB	292	/* 0x10003000 Reserved. */
	293	/* 0x10004000 AACI. */
	294	/* 0x10005000 MCI. */
	295	/* 0x10006000 KMI0. */
	296	/* 0x10007000 KMI1. */
0ef849d7	297	/* 0x10008000 Character LCD. (EB) */
e69954b9 PB	298	/* 0x10009000 UART0. */
	299	/* 0x1000a000 UART1. */
	300	/* 0x1000b000 UART2. */
	301	/* 0x1000c000 UART3. */
	302	/* 0x1000d000 SSPI. */
	303	/* 0x1000e000 SCI. */
	304	/* 0x1000f000 Reserved. */
	305	/* 0x10010000 Watchdog. */
	306	/* 0x10011000 Timer 0+1. */
	307	/* 0x10012000 Timer 2+3. */
	308	/* 0x10013000 GPIO 0. */
	309	/* 0x10014000 GPIO 1. */
	310	/* 0x10015000 GPIO 2. */
0ef849d7	311	/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2	312	/* 0x10017000 RTC. */
e69954b9 PB	313	/* 0x10018000 DMC. */
	314	/* 0x10019000 PCI controller config. */
	315	/* 0x10020000 CLCD. */
	316	/* 0x10030000 DMA Controller. */
0ef849d7 PB	317	/* 0x10040000 GIC1. (EB) */
	318	/* 0x10050000 GIC2. (EB) */
	319	/* 0x10060000 GIC3. (EB) */
	320	/* 0x10070000 GIC4. (EB) */
e69954b9	321	/* 0x10080000 SMC. */
0ef849d7 PB	322	/* 0x1e000000 GIC1. (PB) */
	323	/* 0x1e001000 GIC2. (PB) */
	324	/* 0x1e002000 GIC3. (PB) */
	325	/* 0x1e003000 GIC4. (PB) */
e69954b9 PB	326	/* 0x40000000 NOR flash. */
	327	/* 0x44000000 DoC flash. */
	328	/* 0x48000000 SRAM. */
	329	/* 0x4c000000 Configuration flash. */
	330	/* 0x4e000000 Ethernet. */
	331	/* 0x4f000000 USB. */
	332	/* 0x50000000 PISMO. */
	333	/* 0x54000000 PISMO. */
	334	/* 0x58000000 PISMO. */
	335	/* 0x5c000000 PISMO. */
	336	/* 0x60000000 PCI. */
	337	/* 0x61000000 PCI Self Config. */
	338	/* 0x62000000 PCI Config. */
	339	/* 0x63000000 PCI IO. */
	340	/* 0x64000000 PCI mem 0. */
	341	/* 0x68000000 PCI mem 1. */
	342	/* 0x6c000000 PCI mem 2. */
	343
7ffab4d7 PB	344	/* ??? Hack to map an additional page of ram for the secondary CPU
	345	startup code. I guess this works on real hardware because the
	346	BootROM happens to be in ROM/flash or in memory that isn't clobbered
	347	until after Linux boots the secondary CPUs. */
	348	ram_offset = qemu_ram_alloc(0x1000);
0ef849d7 PB	349	cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
0ef849d7 PB	350	ram_offset \| IO_MEM_RAM);
7ffab4d7	351
f93eb9ff AZ	352	realview_binfo.ram_size = ram_size;
	353	realview_binfo.kernel_filename = kernel_filename;
	354	realview_binfo.kernel_cmdline = kernel_cmdline;
	355	realview_binfo.initrd_filename = initrd_filename;
c988bfad	356	realview_binfo.nb_cpus = smp_cpus;
f7c70325	357	realview_binfo.board_id = realview_board_id[board_type];
0ef849d7	358	realview_binfo.loader_start = is_pb ? 0x70000000 : 0;
f93eb9ff	359	arm_load_kernel(first_cpu, &realview_binfo);
e69954b9 PB	360	}
e69954b9 PB	361
c988bfad PB	362	static void realview_eb_init(ram_addr_t ram_size,
	363	const char *boot_device,
	364	const char kernel_filename, const char kernel_cmdline,
	365	const char initrd_filename, const char cpu_model)
	366	{
	367	if (!cpu_model) {
	368	cpu_model = "arm926";
	369	}
	370	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	371	initrd_filename, cpu_model, BOARD_EB);
	372	}
	373
	374	static void realview_eb_mpcore_init(ram_addr_t ram_size,
	375	const char *boot_device,
	376	const char kernel_filename, const char kernel_cmdline,
	377	const char initrd_filename, const char cpu_model)
	378	{
	379	if (!cpu_model) {
	380	cpu_model = "arm11mpcore";
	381	}
	382	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	383	initrd_filename, cpu_model, BOARD_EB_MPCORE);
	384	}
	385
0ef849d7 PB	386	static void realview_pb_a8_init(ram_addr_t ram_size,
	387	const char *boot_device,
	388	const char kernel_filename, const char kernel_cmdline,
	389	const char initrd_filename, const char cpu_model)
	390	{
	391	if (!cpu_model) {
	392	cpu_model = "cortex-a8";
	393	}
	394	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	395	initrd_filename, cpu_model, BOARD_PB_A8);
	396	}
	397
f7c70325 PB	398	static void realview_pbx_a9_init(ram_addr_t ram_size,
	399	const char *boot_device,
	400	const char kernel_filename, const char kernel_cmdline,
	401	const char initrd_filename, const char cpu_model)
	402	{
	403	if (!cpu_model) {
	404	cpu_model = "cortex-a9";
	405	}
	406	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	407	initrd_filename, cpu_model, BOARD_PBX_A9);
	408	}
	409
c988bfad PB	410	static QEMUMachine realview_eb_machine = {
c988bfad PB	411	.name = "realview-eb",
c9b1ae2c	412	.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
c988bfad PB	413	.init = realview_eb_init,
	414	.use_scsi = 1,
	415	};
	416
	417	static QEMUMachine realview_eb_mpcore_machine = {
	418	.name = "realview-eb-mpcore",
	419	.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
	420	.init = realview_eb_mpcore_init,
c9b1ae2c	421	.use_scsi = 1,
c988bfad	422	.max_cpus = 4,
e69954b9	423	};
f80f9ec9	424
0ef849d7 PB	425	static QEMUMachine realview_pb_a8_machine = {
	426	.name = "realview-pb-a8",
	427	.desc = "ARM RealView Platform Baseboard for Cortex-A8",
	428	.init = realview_pb_a8_init,
f7c70325 PB	429	};
	430
	431	static QEMUMachine realview_pbx_a9_machine = {
	432	.name = "realview-pbx-a9",
	433	.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
	434	.init = realview_pbx_a9_init,
0ef849d7	435	.use_scsi = 1,
f7c70325	436	.max_cpus = 4,
0ef849d7 PB	437	};
0ef849d7 PB	438
f80f9ec9 AL	439	static void realview_machine_init(void)
f80f9ec9 AL	440	{
c988bfad PB	441	qemu_register_machine(&realview_eb_machine);
c988bfad PB	442	qemu_register_machine(&realview_eb_mpcore_machine);
0ef849d7	443	qemu_register_machine(&realview_pb_a8_machine);
f7c70325	444	qemu_register_machine(&realview_pbx_a9_machine);
f80f9ec9 AL	445	}
	446
	447	machine_init(realview_machine_init);
eee48504	448	device_init(realview_register_devices)