[qemu.git] / hw / realview.c

/*
 * ARM RealView Baseboard System emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "pci.h"
#include "usb-ohci.h"
#include "net.h"
#include "sysemu.h"
#include "boards.h"
#include "bitbang_i2c.h"
#include "sysbus.h"

#define SMP_BOOT_ADDR 0xe0000000

typedef struct {
    SysBusDevice busdev;
    bitbang_i2c_interface *bitbang;
    int out;
    int in;
} RealViewI2CState;

static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    if (offset == 0) {
        return (s->out & 1) | (s->in << 1);
    } else {
        hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
        return -1;
    }
}

static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
                               uint32_t value)
{
    RealViewI2CState *s = (RealViewI2CState *)opaque;

    switch (offset) {
    case 0:
        s->out |= value & 3;
        break;
    case 4:
        s->out &= ~value;
        break;
    default:
        hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
    }
    bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
    s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
}

static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
   realview_i2c_read,
   realview_i2c_read,
   realview_i2c_read
};

static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
   realview_i2c_write,
   realview_i2c_write,
   realview_i2c_write
};

static int realview_i2c_init(SysBusDevice *dev)
{
    RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
    i2c_bus *bus;
    int iomemtype;

    bus = i2c_init_bus(&dev->qdev, "i2c");
    s->bitbang = bitbang_i2c_init(bus);
    iomemtype = cpu_register_io_memory(realview_i2c_readfn,
                                       realview_i2c_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    return 0;
}

static SysBusDeviceInfo realview_i2c_info = {
    .init = realview_i2c_init,
    .qdev.name  = "realview_i2c",
    .qdev.size  = sizeof(RealViewI2CState),
};

static void realview_register_devices(void)
{
    sysbus_register_withprop(&realview_i2c_info);
}

/* Board init.  */

static struct arm_boot_info realview_binfo = {
    .smp_loader_start = SMP_BOOT_ADDR,
};

static void secondary_cpu_reset(void *opaque)
{
  CPUState *env = opaque;

  cpu_reset(env);
  /* Set entry point for secondary CPUs.  This assumes we're using
     the init code from arm_boot.c.  Real hardware resets all CPUs
     the same.  */
  env->regs[15] = SMP_BOOT_ADDR;
}

/* The following two lists must be consistent.  */
enum realview_board_type {
    BOARD_EB,
    BOARD_EB_MPCORE,
    BOARD_PB_A8,
    BOARD_PBX_A9,
};

static const int realview_board_id[] = {
    0x33b,
    0x33b,
    0x769,
    0x76d
};

static void realview_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     enum realview_board_type board_type)
{
    CPUState *env = NULL;
    ram_addr_t ram_offset;
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq *irqp;
    qemu_irq pic[64];
    PCIBus *pci_bus;
    NICInfo *nd;
    i2c_bus *i2c;
    int n;
    int done_nic = 0;
    qemu_irq cpu_irq[4];
    int is_mpcore = 0;
    int is_pb = 0;
    uint32_t proc_id = 0;
    uint32_t sys_id;
    ram_addr_t low_ram_size;

    switch (board_type) {
    case BOARD_EB:
        break;
    case BOARD_EB_MPCORE:
        is_mpcore = 1;
        break;
    case BOARD_PB_A8:
        is_pb = 1;
        break;
    case BOARD_PBX_A9:
        is_mpcore = 1;
        is_pb = 1;
        break;
    }
    for (n = 0; n < smp_cpus; n++) {
        env = cpu_init(cpu_model);
        if (!env) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }
        irqp = arm_pic_init_cpu(env);
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
        if (n > 0) {
            qemu_register_reset(secondary_cpu_reset, env);
        }
    }
    if (arm_feature(env, ARM_FEATURE_V7)) {
        if (is_mpcore) {
            proc_id = 0x0c000000;
        } else {
            proc_id = 0x0e000000;
        }
    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
        proc_id = 0x06000000;
    } else if (arm_feature(env, ARM_FEATURE_V6)) {
        proc_id = 0x04000000;
    } else {
        proc_id = 0x02000000;
    }

    if (is_pb && ram_size > 0x20000000) {
        /* Core tile RAM.  */
        low_ram_size = ram_size - 0x20000000;
        ram_size = 0x20000000;
        ram_offset = qemu_ram_alloc(low_ram_size);
        cpu_register_physical_memory(0x20000000, low_ram_size,
                                     ram_offset | IO_MEM_RAM);
    }

    ram_offset = qemu_ram_alloc(ram_size);
    low_ram_size = ram_size;
    if (low_ram_size > 0x10000000)
      low_ram_size = 0x10000000;
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
    if (is_pb) {
        /* And again at a high address.  */
        cpu_register_physical_memory(0x70000000, ram_size,
                                     ram_offset | IO_MEM_RAM);
    } else {
        ram_size = low_ram_size;
    }

    sys_id = is_pb ? 0x01780500 : 0xc1400400;
    arm_sysctl_init(0x10000000, sys_id, proc_id);

    if (is_mpcore) {
        dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
        qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
        qdev_init_nofail(dev);
        busdev = sysbus_from_qdev(dev);
        if (is_pb) {
            realview_binfo.smp_priv_base = 0x1f000000;
        } else {
            realview_binfo.smp_priv_base = 0x10100000;
        }
        sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
        for (n = 0; n < smp_cpus; n++) {
            sysbus_connect_irq(busdev, n, cpu_irq[n]);
        }
    } else {
        uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
        /* For now just create the nIRQ GIC, and ignore the others.  */
        dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
    }
    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
    sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);

    sysbus_create_simple("pl011", 0x10009000, pic[12]);
    sysbus_create_simple("pl011", 0x1000a000, pic[13]);
    sysbus_create_simple("pl011", 0x1000b000, pic[14]);
    sysbus_create_simple("pl011", 0x1000c000, pic[15]);

    /* DMA controller is optional, apparently.  */
    sysbus_create_simple("pl081", 0x10030000, pic[24]);

    sysbus_create_simple("sp804", 0x10011000, pic[4]);
    sysbus_create_simple("sp804", 0x10012000, pic[5]);

    sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);

    sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);

    sysbus_create_simple("pl031", 0x10017000, pic[10]);

    if (!is_pb) {
        dev = sysbus_create_varargs("realview_pci", 0x60000000,
                                    pic[48], pic[49], pic[50], pic[51], NULL);
        pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
        if (usb_enabled) {
#ifdef TARGET_WORDS_BIGENDIAN
            usb_ohci_init_pci(pci_bus, -1, 1);
#else
            usb_ohci_init_pci(pci_bus, -1, 0);
#endif
        }
        n = drive_get_max_bus(IF_SCSI);
        while (n >= 0) {
            pci_create_simple(pci_bus, -1, "lsi53c895a");
            n--;
        }
    }
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if ((!nd->model && !done_nic)
            || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
            if (is_pb) {
                lan9118_init(nd, 0x4e000000, pic[28]);
            } else {
                smc91c111_init(nd, 0x4e000000, pic[28]);
            }
            done_nic = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }

    dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
    i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Memory map for RealView Emulation Baseboard:  */
    /* 0x10000000 System registers.  */
    /*  0x10001000 System controller.  */
    /* 0x10002000 Two-Wire Serial Bus.  */
    /* 0x10003000 Reserved.  */
    /*  0x10004000 AACI.  */
    /*  0x10005000 MCI.  */
    /* 0x10006000 KMI0.  */
    /* 0x10007000 KMI1.  */
    /*  0x10008000 Character LCD. (EB) */
    /* 0x10009000 UART0.  */
    /* 0x1000a000 UART1.  */
    /* 0x1000b000 UART2.  */
    /* 0x1000c000 UART3.  */
    /*  0x1000d000 SSPI.  */
    /*  0x1000e000 SCI.  */
    /* 0x1000f000 Reserved.  */
    /*  0x10010000 Watchdog.  */
    /* 0x10011000 Timer 0+1.  */
    /* 0x10012000 Timer 2+3.  */
    /*  0x10013000 GPIO 0.  */
    /*  0x10014000 GPIO 1.  */
    /*  0x10015000 GPIO 2.  */
    /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
    /* 0x10017000 RTC.  */
    /*  0x10018000 DMC.  */
    /*  0x10019000 PCI controller config.  */
    /*  0x10020000 CLCD.  */
    /* 0x10030000 DMA Controller.  */
    /* 0x10040000 GIC1. (EB) */
    /*  0x10050000 GIC2. (EB) */
    /*  0x10060000 GIC3. (EB) */
    /*  0x10070000 GIC4. (EB) */
    /*  0x10080000 SMC.  */
    /* 0x1e000000 GIC1. (PB) */
    /*  0x1e001000 GIC2. (PB) */
    /*  0x1e002000 GIC3. (PB) */
    /*  0x1e003000 GIC4. (PB) */
    /*  0x40000000 NOR flash.  */
    /*  0x44000000 DoC flash.  */
    /*  0x48000000 SRAM.  */
    /*  0x4c000000 Configuration flash.  */
    /* 0x4e000000 Ethernet.  */
    /*  0x4f000000 USB.  */
    /*  0x50000000 PISMO.  */
    /*  0x54000000 PISMO.  */
    /*  0x58000000 PISMO.  */
    /*  0x5c000000 PISMO.  */
    /* 0x60000000 PCI.  */
    /* 0x61000000 PCI Self Config.  */
    /* 0x62000000 PCI Config.  */
    /* 0x63000000 PCI IO.  */
    /* 0x64000000 PCI mem 0.  */
    /* 0x68000000 PCI mem 1.  */
    /* 0x6c000000 PCI mem 2.  */

    /* ??? Hack to map an additional page of ram for the secondary CPU
       startup code.  I guess this works on real hardware because the
       BootROM happens to be in ROM/flash or in memory that isn't clobbered
       until after Linux boots the secondary CPUs.  */
    ram_offset = qemu_ram_alloc(0x1000);
    cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
                                 ram_offset | IO_MEM_RAM);

    realview_binfo.ram_size = ram_size;
    realview_binfo.kernel_filename = kernel_filename;
    realview_binfo.kernel_cmdline = kernel_cmdline;
    realview_binfo.initrd_filename = initrd_filename;
    realview_binfo.nb_cpus = smp_cpus;
    realview_binfo.board_id = realview_board_id[board_type];
    realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
    arm_load_kernel(first_cpu, &realview_binfo);
}

static void realview_eb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm926";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB);
}

static void realview_eb_mpcore_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "arm11mpcore";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_EB_MPCORE);
}

static void realview_pb_a8_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a8";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PB_A8);
}

static void realview_pbx_a9_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }
    realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
                  initrd_filename, cpu_model, BOARD_PBX_A9);
}

static QEMUMachine realview_eb_machine = {
    .name = "realview-eb",
    .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
    .init = realview_eb_init,
    .use_scsi = 1,
};

static QEMUMachine realview_eb_mpcore_machine = {
    .name = "realview-eb-mpcore",
    .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
    .init = realview_eb_mpcore_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static QEMUMachine realview_pb_a8_machine = {
    .name = "realview-pb-a8",
    .desc = "ARM RealView Platform Baseboard for Cortex-A8",
    .init = realview_pb_a8_init,
};

static QEMUMachine realview_pbx_a9_machine = {
    .name = "realview-pbx-a9",
    .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
    .init = realview_pbx_a9_init,
    .use_scsi = 1,
    .max_cpus = 4,
};

static void realview_machine_init(void)
{
    qemu_register_machine(&realview_eb_machine);
    qemu_register_machine(&realview_eb_mpcore_machine);
    qemu_register_machine(&realview_pb_a8_machine);
    qemu_register_machine(&realview_pbx_a9_machine);
}

machine_init(realview_machine_init);
device_init(realview_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9 PB	2	* ARM RealView Baseboard System emulation.
e69954b9 PB	3	*
a1bb27b1	4	* Copyright (c) 2006-2007 CodeSourcery.
e69954b9 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "pci.h"
18e08a55	15	#include "usb-ohci.h"
87ecb68b PB	16	#include "net.h"
	17	#include "sysemu.h"
	18	#include "boards.h"
eee48504 PB	19	#include "bitbang_i2c.h"
eee48504 PB	20	#include "sysbus.h"
e69954b9	21
0ef849d7	22	#define SMP_BOOT_ADDR 0xe0000000
eee48504 PB	23
	24	typedef struct {
	25	SysBusDevice busdev;
	26	bitbang_i2c_interface *bitbang;
	27	int out;
	28	int in;
	29	} RealViewI2CState;
	30
	31	static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset)
	32	{
	33	RealViewI2CState s = (RealViewI2CState )opaque;
	34
	35	if (offset == 0) {
	36	return (s->out & 1) \| (s->in << 1);
	37	} else {
	38	hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
	39	return -1;
	40	}
	41	}
	42
	43	static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
	44	uint32_t value)
	45	{
	46	RealViewI2CState s = (RealViewI2CState )opaque;
	47
	48	switch (offset) {
	49	case 0:
	50	s->out \|= value & 3;
	51	break;
	52	case 4:
	53	s->out &= ~value;
	54	break;
	55	default:
	56	hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
	57	}
	58	bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
	59	s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
	60	}
	61
	62	static CPUReadMemoryFunc * const realview_i2c_readfn[] = {
	63	realview_i2c_read,
	64	realview_i2c_read,
	65	realview_i2c_read
	66	};
	67
	68	static CPUWriteMemoryFunc * const realview_i2c_writefn[] = {
	69	realview_i2c_write,
	70	realview_i2c_write,
	71	realview_i2c_write
	72	};
	73
	74	static int realview_i2c_init(SysBusDevice *dev)
	75	{
	76	RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
	77	i2c_bus *bus;
	78	int iomemtype;
	79
	80	bus = i2c_init_bus(&dev->qdev, "i2c");
	81	s->bitbang = bitbang_i2c_init(bus);
	82	iomemtype = cpu_register_io_memory(realview_i2c_readfn,
	83	realview_i2c_writefn, s);
	84	sysbus_init_mmio(dev, 0x1000, iomemtype);
	85	return 0;
	86	}
87
88	static SysBusDeviceInfo realview_i2c_info = {
89	.init = realview_i2c_init,
90	.qdev.name = "realview_i2c",
91	.qdev.size = sizeof(RealViewI2CState),
92	};
93
94	static void realview_register_devices(void)
95	{
96	sysbus_register_withprop(&realview_i2c_info);
97	}
98
e69954b9 PB	99	/* Board init. */
e69954b9 PB	100
f93eb9ff	101	static struct arm_boot_info realview_binfo = {
0ef849d7	102	.smp_loader_start = SMP_BOOT_ADDR,
f93eb9ff AZ	103	};
f93eb9ff AZ	104
be0f204a PB	105	static void secondary_cpu_reset(void *opaque)
	106	{
	107	CPUState *env = opaque;
	108
	109	cpu_reset(env);
	110	/* Set entry point for secondary CPUs. This assumes we're using
	111	the init code from arm_boot.c. Real hardware resets all CPUs
	112	the same. */
0ef849d7	113	env->regs[15] = SMP_BOOT_ADDR;
be0f204a PB	114	}
be0f204a PB	115
f7c70325	116	/* The following two lists must be consistent. */
c988bfad PB	117	enum realview_board_type {
c988bfad PB	118	BOARD_EB,
0ef849d7	119	BOARD_EB_MPCORE,
f7c70325 PB	120	BOARD_PB_A8,
	121	BOARD_PBX_A9,
	122	};
	123
d05ac8fa	124	static const int realview_board_id[] = {
f7c70325 PB	125	0x33b,
	126	0x33b,
	127	0x769,
	128	0x76d
c988bfad PB	129	};
c988bfad PB	130
c227f099	131	static void realview_init(ram_addr_t ram_size,
3023f332	132	const char *boot_device,
e69954b9	133	const char kernel_filename, const char kernel_cmdline,
c988bfad PB	134	const char initrd_filename, const char cpu_model,
c988bfad PB	135	enum realview_board_type board_type)
e69954b9	136	{
c988bfad	137	CPUState *env = NULL;
c227f099	138	ram_addr_t ram_offset;
0027b06d	139	DeviceState *dev;
c988bfad	140	SysBusDevice *busdev;
fe7e8758 PB	141	qemu_irq *irqp;
fe7e8758 PB	142	qemu_irq pic[64];
e69954b9 PB	143	PCIBus *pci_bus;
e69954b9 PB	144	NICInfo *nd;
eee48504	145	i2c_bus *i2c;
e69954b9	146	int n;
0ef849d7	147	int done_nic = 0;
9ee6e8bb	148	qemu_irq cpu_irq[4];
f7c70325 PB	149	int is_mpcore = 0;
f7c70325 PB	150	int is_pb = 0;
26e92f65	151	uint32_t proc_id = 0;
0ef849d7 PB	152	uint32_t sys_id;
0ef849d7 PB	153	ram_addr_t low_ram_size;
e69954b9	154
f7c70325 PB	155	switch (board_type) {
	156	case BOARD_EB:
	157	break;
	158	case BOARD_EB_MPCORE:
	159	is_mpcore = 1;
	160	break;
	161	case BOARD_PB_A8:
	162	is_pb = 1;
	163	break;
	164	case BOARD_PBX_A9:
	165	is_mpcore = 1;
	166	is_pb = 1;
	167	break;
	168	}
c988bfad	169	for (n = 0; n < smp_cpus; n++) {
9ee6e8bb PB	170	env = cpu_init(cpu_model);
	171	if (!env) {
	172	fprintf(stderr, "Unable to find CPU definition\n");
	173	exit(1);
	174	}
fe7e8758 PB	175	irqp = arm_pic_init_cpu(env);
fe7e8758 PB	176	cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
9ee6e8bb	177	if (n > 0) {
be0f204a	178	qemu_register_reset(secondary_cpu_reset, env);
9ee6e8bb	179	}
aaed909a	180	}
26e92f65	181	if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325 PB	182	if (is_mpcore) {
	183	proc_id = 0x0c000000;
	184	} else {
	185	proc_id = 0x0e000000;
	186	}
26e92f65 PB	187	} else if (arm_feature(env, ARM_FEATURE_V6K)) {
	188	proc_id = 0x06000000;
	189	} else if (arm_feature(env, ARM_FEATURE_V6)) {
	190	proc_id = 0x04000000;
	191	} else {
	192	proc_id = 0x02000000;
	193	}
aaed909a	194
21a88941 PB	195	if (is_pb && ram_size > 0x20000000) {
	196	/* Core tile RAM. */
	197	low_ram_size = ram_size - 0x20000000;
	198	ram_size = 0x20000000;
	199	ram_offset = qemu_ram_alloc(low_ram_size);
	200	cpu_register_physical_memory(0x20000000, low_ram_size,
	201	ram_offset \| IO_MEM_RAM);
	202	}
	203
7ffab4d7	204	ram_offset = qemu_ram_alloc(ram_size);
0ef849d7 PB	205	low_ram_size = ram_size;
	206	if (low_ram_size > 0x10000000)
	207	low_ram_size = 0x10000000;
e69954b9	208	/* SDRAM at address zero. */
0ef849d7 PB	209	cpu_register_physical_memory(0, low_ram_size, ram_offset \| IO_MEM_RAM);
	210	if (is_pb) {
	211	/* And again at a high address. */
	212	cpu_register_physical_memory(0x70000000, ram_size,
	213	ram_offset \| IO_MEM_RAM);
	214	} else {
	215	ram_size = low_ram_size;
	216	}
e69954b9	217
0ef849d7 PB	218	sys_id = is_pb ? 0x01780500 : 0xc1400400;
0ef849d7 PB	219	arm_sysctl_init(0x10000000, sys_id, proc_id);
9ee6e8bb	220
c988bfad	221	if (is_mpcore) {
f7c70325	222	dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
c988bfad PB	223	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	224	qdev_init_nofail(dev);
	225	busdev = sysbus_from_qdev(dev);
f7c70325 PB	226	if (is_pb) {
	227	realview_binfo.smp_priv_base = 0x1f000000;
	228	} else {
	229	realview_binfo.smp_priv_base = 0x10100000;
	230	}
	231	sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
c988bfad PB	232	for (n = 0; n < smp_cpus; n++) {
	233	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	234	}
9ee6e8bb	235	} else {
0ef849d7 PB	236	uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
	237	/* For now just create the nIRQ GIC, and ignore the others. */
	238	dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
fe7e8758 PB	239	}
fe7e8758 PB	240	for (n = 0; n < 64; n++) {
067a3ddc	241	pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb PB	242	}
9ee6e8bb PB	243
86394e96 PB	244	sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
86394e96 PB	245	sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9	246
a7d518a6 PB	247	sysbus_create_simple("pl011", 0x10009000, pic[12]);
	248	sysbus_create_simple("pl011", 0x1000a000, pic[13]);
	249	sysbus_create_simple("pl011", 0x1000b000, pic[14]);
	250	sysbus_create_simple("pl011", 0x1000c000, pic[15]);
e69954b9 PB	251
e69954b9 PB	252	/* DMA controller is optional, apparently. */
b4496b13	253	sysbus_create_simple("pl081", 0x10030000, pic[24]);
e69954b9	254
6a824ec3 PB	255	sysbus_create_simple("sp804", 0x10011000, pic[4]);
6a824ec3 PB	256	sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9	257
2e9bdce5	258	sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
e69954b9	259
aa9311d8	260	sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
a1bb27b1	261
a63bdb31	262	sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2	263
0ef849d7 PB	264	if (!is_pb) {
	265	dev = sysbus_create_varargs("realview_pci", 0x60000000,
	266	pic[48], pic[49], pic[50], pic[51], NULL);
	267	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
	268	if (usb_enabled) {
f1698408 BS	269	#ifdef TARGET_WORDS_BIGENDIAN
	270	usb_ohci_init_pci(pci_bus, -1, 1);
	271	#else
	272	usb_ohci_init_pci(pci_bus, -1, 0);
	273	#endif
0ef849d7 PB	274	}
	275	n = drive_get_max_bus(IF_SCSI);
	276	while (n >= 0) {
	277	pci_create_simple(pci_bus, -1, "lsi53c895a");
	278	n--;
	279	}
e69954b9 PB	280	}
	281	for(n = 0; n < nb_nics; n++) {
	282	nd = &nd_table[n];
0ae18cee	283
0ef849d7 PB	284	if ((!nd->model && !done_nic)
	285	\|\| strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
	286	if (is_pb) {
	287	lan9118_init(nd, 0x4e000000, pic[28]);
	288	} else {
	289	smc91c111_init(nd, 0x4e000000, pic[28]);
	290	}
	291	done_nic = 1;
e69954b9	292	} else {
07caea31	293	pci_nic_init_nofail(nd, "rtl8139", NULL);
e69954b9 PB	294	}
	295	}
	296
eee48504 PB	297	dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
	298	i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
	299	i2c_create_slave(i2c, "ds1338", 0x68);
	300
e69954b9 PB	301	/* Memory map for RealView Emulation Baseboard: */
	302	/* 0x10000000 System registers. */
	303	/* 0x10001000 System controller. */
eee48504	304	/* 0x10002000 Two-Wire Serial Bus. */
e69954b9 PB	305	/* 0x10003000 Reserved. */
	306	/* 0x10004000 AACI. */
	307	/* 0x10005000 MCI. */
	308	/* 0x10006000 KMI0. */
	309	/* 0x10007000 KMI1. */
0ef849d7	310	/* 0x10008000 Character LCD. (EB) */
e69954b9 PB	311	/* 0x10009000 UART0. */
	312	/* 0x1000a000 UART1. */
	313	/* 0x1000b000 UART2. */
	314	/* 0x1000c000 UART3. */
	315	/* 0x1000d000 SSPI. */
	316	/* 0x1000e000 SCI. */
	317	/* 0x1000f000 Reserved. */
	318	/* 0x10010000 Watchdog. */
	319	/* 0x10011000 Timer 0+1. */
	320	/* 0x10012000 Timer 2+3. */
	321	/* 0x10013000 GPIO 0. */
	322	/* 0x10014000 GPIO 1. */
	323	/* 0x10015000 GPIO 2. */
0ef849d7	324	/* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2	325	/* 0x10017000 RTC. */
e69954b9 PB	326	/* 0x10018000 DMC. */
	327	/* 0x10019000 PCI controller config. */
	328	/* 0x10020000 CLCD. */
	329	/* 0x10030000 DMA Controller. */
0ef849d7 PB	330	/* 0x10040000 GIC1. (EB) */
	331	/* 0x10050000 GIC2. (EB) */
	332	/* 0x10060000 GIC3. (EB) */
	333	/* 0x10070000 GIC4. (EB) */
e69954b9	334	/* 0x10080000 SMC. */
0ef849d7 PB	335	/* 0x1e000000 GIC1. (PB) */
	336	/* 0x1e001000 GIC2. (PB) */
	337	/* 0x1e002000 GIC3. (PB) */
	338	/* 0x1e003000 GIC4. (PB) */
e69954b9 PB	339	/* 0x40000000 NOR flash. */
	340	/* 0x44000000 DoC flash. */
	341	/* 0x48000000 SRAM. */
	342	/* 0x4c000000 Configuration flash. */
	343	/* 0x4e000000 Ethernet. */
	344	/* 0x4f000000 USB. */
	345	/* 0x50000000 PISMO. */
	346	/* 0x54000000 PISMO. */
	347	/* 0x58000000 PISMO. */
	348	/* 0x5c000000 PISMO. */
	349	/* 0x60000000 PCI. */
	350	/* 0x61000000 PCI Self Config. */
	351	/* 0x62000000 PCI Config. */
	352	/* 0x63000000 PCI IO. */
	353	/* 0x64000000 PCI mem 0. */
	354	/* 0x68000000 PCI mem 1. */
	355	/* 0x6c000000 PCI mem 2. */
	356
7ffab4d7 PB	357	/* ??? Hack to map an additional page of ram for the secondary CPU
	358	startup code. I guess this works on real hardware because the
	359	BootROM happens to be in ROM/flash or in memory that isn't clobbered
	360	until after Linux boots the secondary CPUs. */
	361	ram_offset = qemu_ram_alloc(0x1000);
0ef849d7 PB	362	cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
0ef849d7 PB	363	ram_offset \| IO_MEM_RAM);
7ffab4d7	364
f93eb9ff AZ	365	realview_binfo.ram_size = ram_size;
	366	realview_binfo.kernel_filename = kernel_filename;
	367	realview_binfo.kernel_cmdline = kernel_cmdline;
	368	realview_binfo.initrd_filename = initrd_filename;
c988bfad	369	realview_binfo.nb_cpus = smp_cpus;
f7c70325	370	realview_binfo.board_id = realview_board_id[board_type];
21a88941	371	realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
f93eb9ff	372	arm_load_kernel(first_cpu, &realview_binfo);
e69954b9 PB	373	}
e69954b9 PB	374
c988bfad PB	375	static void realview_eb_init(ram_addr_t ram_size,
	376	const char *boot_device,
	377	const char kernel_filename, const char kernel_cmdline,
	378	const char initrd_filename, const char cpu_model)
	379	{
	380	if (!cpu_model) {
	381	cpu_model = "arm926";
	382	}
	383	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	384	initrd_filename, cpu_model, BOARD_EB);
	385	}
	386
	387	static void realview_eb_mpcore_init(ram_addr_t ram_size,
	388	const char *boot_device,
	389	const char kernel_filename, const char kernel_cmdline,
	390	const char initrd_filename, const char cpu_model)
	391	{
	392	if (!cpu_model) {
	393	cpu_model = "arm11mpcore";
	394	}
	395	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	396	initrd_filename, cpu_model, BOARD_EB_MPCORE);
	397	}
	398
0ef849d7 PB	399	static void realview_pb_a8_init(ram_addr_t ram_size,
	400	const char *boot_device,
	401	const char kernel_filename, const char kernel_cmdline,
	402	const char initrd_filename, const char cpu_model)
	403	{
	404	if (!cpu_model) {
	405	cpu_model = "cortex-a8";
	406	}
	407	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	408	initrd_filename, cpu_model, BOARD_PB_A8);
	409	}
	410
f7c70325 PB	411	static void realview_pbx_a9_init(ram_addr_t ram_size,
	412	const char *boot_device,
	413	const char kernel_filename, const char kernel_cmdline,
	414	const char initrd_filename, const char cpu_model)
	415	{
	416	if (!cpu_model) {
	417	cpu_model = "cortex-a9";
	418	}
	419	realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
	420	initrd_filename, cpu_model, BOARD_PBX_A9);
	421	}
	422
c988bfad PB	423	static QEMUMachine realview_eb_machine = {
c988bfad PB	424	.name = "realview-eb",
c9b1ae2c	425	.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
c988bfad PB	426	.init = realview_eb_init,
	427	.use_scsi = 1,
	428	};
	429
	430	static QEMUMachine realview_eb_mpcore_machine = {
	431	.name = "realview-eb-mpcore",
	432	.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
	433	.init = realview_eb_mpcore_init,
c9b1ae2c	434	.use_scsi = 1,
c988bfad	435	.max_cpus = 4,
e69954b9	436	};
f80f9ec9	437
0ef849d7 PB	438	static QEMUMachine realview_pb_a8_machine = {
	439	.name = "realview-pb-a8",
	440	.desc = "ARM RealView Platform Baseboard for Cortex-A8",
	441	.init = realview_pb_a8_init,
f7c70325 PB	442	};
	443
	444	static QEMUMachine realview_pbx_a9_machine = {
	445	.name = "realview-pbx-a9",
	446	.desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
	447	.init = realview_pbx_a9_init,
0ef849d7	448	.use_scsi = 1,
f7c70325	449	.max_cpus = 4,
0ef849d7 PB	450	};
0ef849d7 PB	451
f80f9ec9 AL	452	static void realview_machine_init(void)
f80f9ec9 AL	453	{
c988bfad PB	454	qemu_register_machine(&realview_eb_machine);
c988bfad PB	455	qemu_register_machine(&realview_eb_mpcore_machine);
0ef849d7	456	qemu_register_machine(&realview_pb_a8_machine);
f7c70325	457	qemu_register_machine(&realview_pbx_a9_machine);
f80f9ec9 AL	458	}
	459
	460	machine_init(realview_machine_init);
eee48504	461	device_init(realview_register_devices)