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Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
[qemu.git] / hw / realview.c
CommitLineData
5fafdf24 1/*
e69954b9
PB
2 * ARM RealView Baseboard System emulation.
3 *
a1bb27b1 4 * Copyright (c) 2006-2007 CodeSourcery.
e69954b9
PB
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GPL.
e69954b9
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8 */
9
2e9bdce5 10#include "sysbus.h"
87ecb68b
PB
11#include "arm-misc.h"
12#include "primecell.h"
13#include "devices.h"
14#include "pci.h"
15#include "net.h"
16#include "sysemu.h"
17#include "boards.h"
d1157ca4 18#include "i2c.h"
2446333c 19#include "blockdev.h"
35e87820 20#include "exec-memory.h"
e69954b9 21
0ef849d7 22#define SMP_BOOT_ADDR 0xe0000000
078758d0 23#define SMP_BOOTREG_ADDR 0x10000030
eee48504 24
e69954b9
PB
25/* Board init. */
26
f93eb9ff 27static struct arm_boot_info realview_binfo = {
0ef849d7 28 .smp_loader_start = SMP_BOOT_ADDR,
078758d0 29 .smp_bootreg_addr = SMP_BOOTREG_ADDR,
f93eb9ff
AZ
30};
31
f7c70325 32/* The following two lists must be consistent. */
c988bfad
PB
33enum realview_board_type {
34 BOARD_EB,
0ef849d7 35 BOARD_EB_MPCORE,
f7c70325
PB
36 BOARD_PB_A8,
37 BOARD_PBX_A9,
38};
39
d05ac8fa 40static const int realview_board_id[] = {
f7c70325
PB
41 0x33b,
42 0x33b,
43 0x769,
44 0x76d
c988bfad
PB
45};
46
c227f099 47static void realview_init(ram_addr_t ram_size,
3023f332 48 const char *boot_device,
e69954b9 49 const char *kernel_filename, const char *kernel_cmdline,
c988bfad
PB
50 const char *initrd_filename, const char *cpu_model,
51 enum realview_board_type board_type)
e69954b9 52{
9077f01b
AF
53 ARMCPU *cpu = NULL;
54 CPUARMState *env;
35e87820
AK
55 MemoryRegion *sysmem = get_system_memory();
56 MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
57 MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
58 MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
59 MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
03a0e944 60 DeviceState *dev, *sysctl, *gpio2, *pl041;
c988bfad 61 SysBusDevice *busdev;
fe7e8758
PB
62 qemu_irq *irqp;
63 qemu_irq pic[64];
26883c69 64 qemu_irq mmc_irq[2];
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PB
65 PCIBus *pci_bus;
66 NICInfo *nd;
eee48504 67 i2c_bus *i2c;
e69954b9 68 int n;
0ef849d7 69 int done_nic = 0;
9ee6e8bb 70 qemu_irq cpu_irq[4];
f7c70325
PB
71 int is_mpcore = 0;
72 int is_pb = 0;
26e92f65 73 uint32_t proc_id = 0;
0ef849d7
PB
74 uint32_t sys_id;
75 ram_addr_t low_ram_size;
e69954b9 76
f7c70325
PB
77 switch (board_type) {
78 case BOARD_EB:
79 break;
80 case BOARD_EB_MPCORE:
81 is_mpcore = 1;
82 break;
83 case BOARD_PB_A8:
84 is_pb = 1;
85 break;
86 case BOARD_PBX_A9:
87 is_mpcore = 1;
88 is_pb = 1;
89 break;
90 }
c988bfad 91 for (n = 0; n < smp_cpus; n++) {
9077f01b
AF
92 cpu = cpu_arm_init(cpu_model);
93 if (!cpu) {
9ee6e8bb
PB
94 fprintf(stderr, "Unable to find CPU definition\n");
95 exit(1);
96 }
4bd74661 97 irqp = arm_pic_init_cpu(cpu);
fe7e8758 98 cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
aaed909a 99 }
9077f01b 100 env = &cpu->env;
26e92f65 101 if (arm_feature(env, ARM_FEATURE_V7)) {
f7c70325
PB
102 if (is_mpcore) {
103 proc_id = 0x0c000000;
104 } else {
105 proc_id = 0x0e000000;
106 }
26e92f65
PB
107 } else if (arm_feature(env, ARM_FEATURE_V6K)) {
108 proc_id = 0x06000000;
109 } else if (arm_feature(env, ARM_FEATURE_V6)) {
110 proc_id = 0x04000000;
111 } else {
112 proc_id = 0x02000000;
113 }
aaed909a 114
21a88941
PB
115 if (is_pb && ram_size > 0x20000000) {
116 /* Core tile RAM. */
117 low_ram_size = ram_size - 0x20000000;
118 ram_size = 0x20000000;
c5705a77
AK
119 memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
120 vmstate_register_ram_global(ram_lo);
35e87820 121 memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
21a88941
PB
122 }
123
c5705a77
AK
124 memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
125 vmstate_register_ram_global(ram_hi);
0ef849d7
PB
126 low_ram_size = ram_size;
127 if (low_ram_size > 0x10000000)
128 low_ram_size = 0x10000000;
e69954b9 129 /* SDRAM at address zero. */
35e87820
AK
130 memory_region_init_alias(ram_alias, "realview.alias",
131 ram_hi, 0, low_ram_size);
132 memory_region_add_subregion(sysmem, 0, ram_alias);
0ef849d7
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133 if (is_pb) {
134 /* And again at a high address. */
35e87820 135 memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
0ef849d7
PB
136 } else {
137 ram_size = low_ram_size;
138 }
e69954b9 139
0ef849d7 140 sys_id = is_pb ? 0x01780500 : 0xc1400400;
26883c69
PM
141 sysctl = qdev_create(NULL, "realview_sysctl");
142 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
26883c69 143 qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
7a65c8cc 144 qdev_init_nofail(sysctl);
26883c69 145 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
9ee6e8bb 146
c988bfad 147 if (is_mpcore) {
a8170e5e 148 hwaddr periphbase;
f7c70325 149 dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
c988bfad
PB
150 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
151 qdev_init_nofail(dev);
152 busdev = sysbus_from_qdev(dev);
f7c70325 153 if (is_pb) {
96eacf64 154 periphbase = 0x1f000000;
f7c70325 155 } else {
96eacf64 156 periphbase = 0x10100000;
f7c70325 157 }
96eacf64 158 sysbus_mmio_map(busdev, 0, periphbase);
c988bfad
PB
159 for (n = 0; n < smp_cpus; n++) {
160 sysbus_connect_irq(busdev, n, cpu_irq[n]);
161 }
96eacf64
PM
162 sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
163 /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */
164 realview_binfo.gic_cpu_if_addr = periphbase + 0x100;
9ee6e8bb 165 } else {
0ef849d7
PB
166 uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
167 /* For now just create the nIRQ GIC, and ignore the others. */
168 dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
fe7e8758
PB
169 }
170 for (n = 0; n < 64; n++) {
067a3ddc 171 pic[n] = qdev_get_gpio_in(dev, n);
9ee6e8bb
PB
172 }
173
03a0e944
PM
174 pl041 = qdev_create(NULL, "pl041");
175 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
176 qdev_init_nofail(pl041);
177 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
178 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]);
179
86394e96
PB
180 sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
181 sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
e69954b9 182
a7d518a6
PB
183 sysbus_create_simple("pl011", 0x10009000, pic[12]);
184 sysbus_create_simple("pl011", 0x1000a000, pic[13]);
185 sysbus_create_simple("pl011", 0x1000b000, pic[14]);
186 sysbus_create_simple("pl011", 0x1000c000, pic[15]);
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PB
187
188 /* DMA controller is optional, apparently. */
b4496b13 189 sysbus_create_simple("pl081", 0x10030000, pic[24]);
e69954b9 190
6a824ec3
PB
191 sysbus_create_simple("sp804", 0x10011000, pic[4]);
192 sysbus_create_simple("sp804", 0x10012000, pic[5]);
e69954b9 193
26883c69
PM
194 sysbus_create_simple("pl061", 0x10013000, pic[6]);
195 sysbus_create_simple("pl061", 0x10014000, pic[7]);
196 gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
197
acb9b722 198 sysbus_create_simple("pl111", 0x10020000, pic[23]);
e69954b9 199
26883c69
PM
200 dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
201 /* Wire up MMC card detect and read-only signals. These have
202 * to go to both the PL061 GPIO and the sysctl register.
203 * Note that the PL181 orders these lines (readonly,inserted)
204 * and the PL061 has them the other way about. Also the card
205 * detect line is inverted.
206 */
207 mmc_irq[0] = qemu_irq_split(
208 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
209 qdev_get_gpio_in(gpio2, 1));
210 mmc_irq[1] = qemu_irq_split(
211 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
212 qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
213 qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
214 qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
a1bb27b1 215
a63bdb31 216 sysbus_create_simple("pl031", 0x10017000, pic[10]);
7e1543c2 217
0ef849d7 218 if (!is_pb) {
7d6e771f
PM
219 dev = qdev_create(NULL, "realview_pci");
220 busdev = sysbus_from_qdev(dev);
221 qdev_init_nofail(dev);
222 sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */
223 sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */
224 sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */
225 sysbus_connect_irq(busdev, 0, pic[48]);
226 sysbus_connect_irq(busdev, 1, pic[49]);
227 sysbus_connect_irq(busdev, 2, pic[50]);
228 sysbus_connect_irq(busdev, 3, pic[51]);
0ef849d7 229 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
094b287f 230 if (usb_enabled(false)) {
afb9a60e 231 pci_create_simple(pci_bus, -1, "pci-ohci");
0ef849d7
PB
232 }
233 n = drive_get_max_bus(IF_SCSI);
234 while (n >= 0) {
235 pci_create_simple(pci_bus, -1, "lsi53c895a");
236 n--;
237 }
e69954b9
PB
238 }
239 for(n = 0; n < nb_nics; n++) {
240 nd = &nd_table[n];
0ae18cee 241
e6b3c8ca
PM
242 if (!done_nic && (!nd->model ||
243 strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
0ef849d7
PB
244 if (is_pb) {
245 lan9118_init(nd, 0x4e000000, pic[28]);
246 } else {
247 smc91c111_init(nd, 0x4e000000, pic[28]);
248 }
249 done_nic = 1;
e69954b9 250 } else {
07caea31 251 pci_nic_init_nofail(nd, "rtl8139", NULL);
e69954b9
PB
252 }
253 }
254
d1157ca4 255 dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
eee48504
PB
256 i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
257 i2c_create_slave(i2c, "ds1338", 0x68);
258
e69954b9
PB
259 /* Memory map for RealView Emulation Baseboard: */
260 /* 0x10000000 System registers. */
261 /* 0x10001000 System controller. */
eee48504 262 /* 0x10002000 Two-Wire Serial Bus. */
e69954b9
PB
263 /* 0x10003000 Reserved. */
264 /* 0x10004000 AACI. */
265 /* 0x10005000 MCI. */
266 /* 0x10006000 KMI0. */
267 /* 0x10007000 KMI1. */
0ef849d7 268 /* 0x10008000 Character LCD. (EB) */
e69954b9
PB
269 /* 0x10009000 UART0. */
270 /* 0x1000a000 UART1. */
271 /* 0x1000b000 UART2. */
272 /* 0x1000c000 UART3. */
273 /* 0x1000d000 SSPI. */
274 /* 0x1000e000 SCI. */
275 /* 0x1000f000 Reserved. */
276 /* 0x10010000 Watchdog. */
277 /* 0x10011000 Timer 0+1. */
278 /* 0x10012000 Timer 2+3. */
279 /* 0x10013000 GPIO 0. */
280 /* 0x10014000 GPIO 1. */
281 /* 0x10015000 GPIO 2. */
0ef849d7 282 /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */
7e1543c2 283 /* 0x10017000 RTC. */
e69954b9
PB
284 /* 0x10018000 DMC. */
285 /* 0x10019000 PCI controller config. */
286 /* 0x10020000 CLCD. */
287 /* 0x10030000 DMA Controller. */
0ef849d7
PB
288 /* 0x10040000 GIC1. (EB) */
289 /* 0x10050000 GIC2. (EB) */
290 /* 0x10060000 GIC3. (EB) */
291 /* 0x10070000 GIC4. (EB) */
e69954b9 292 /* 0x10080000 SMC. */
0ef849d7
PB
293 /* 0x1e000000 GIC1. (PB) */
294 /* 0x1e001000 GIC2. (PB) */
295 /* 0x1e002000 GIC3. (PB) */
296 /* 0x1e003000 GIC4. (PB) */
e69954b9
PB
297 /* 0x40000000 NOR flash. */
298 /* 0x44000000 DoC flash. */
299 /* 0x48000000 SRAM. */
300 /* 0x4c000000 Configuration flash. */
301 /* 0x4e000000 Ethernet. */
302 /* 0x4f000000 USB. */
303 /* 0x50000000 PISMO. */
304 /* 0x54000000 PISMO. */
305 /* 0x58000000 PISMO. */
306 /* 0x5c000000 PISMO. */
307 /* 0x60000000 PCI. */
308 /* 0x61000000 PCI Self Config. */
309 /* 0x62000000 PCI Config. */
310 /* 0x63000000 PCI IO. */
311 /* 0x64000000 PCI mem 0. */
312 /* 0x68000000 PCI mem 1. */
313 /* 0x6c000000 PCI mem 2. */
314
7ffab4d7
PB
315 /* ??? Hack to map an additional page of ram for the secondary CPU
316 startup code. I guess this works on real hardware because the
317 BootROM happens to be in ROM/flash or in memory that isn't clobbered
318 until after Linux boots the secondary CPUs. */
c5705a77
AK
319 memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
320 vmstate_register_ram_global(ram_hack);
35e87820 321 memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
7ffab4d7 322
f93eb9ff
AZ
323 realview_binfo.ram_size = ram_size;
324 realview_binfo.kernel_filename = kernel_filename;
325 realview_binfo.kernel_cmdline = kernel_cmdline;
326 realview_binfo.initrd_filename = initrd_filename;
c988bfad 327 realview_binfo.nb_cpus = smp_cpus;
f7c70325 328 realview_binfo.board_id = realview_board_id[board_type];
21a88941 329 realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
3aaa8dfa 330 arm_load_kernel(arm_env_get_cpu(first_cpu), &realview_binfo);
e69954b9
PB
331}
332
5f072e1f 333static void realview_eb_init(QEMUMachineInitArgs *args)
c988bfad 334{
5f072e1f
EH
335 ram_addr_t ram_size = args->ram_size;
336 const char *cpu_model = args->cpu_model;
337 const char *kernel_filename = args->kernel_filename;
338 const char *kernel_cmdline = args->kernel_cmdline;
339 const char *initrd_filename = args->initrd_filename;
340 const char *boot_device = args->boot_device;
c988bfad
PB
341 if (!cpu_model) {
342 cpu_model = "arm926";
343 }
344 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
345 initrd_filename, cpu_model, BOARD_EB);
346}
347
5f072e1f 348static void realview_eb_mpcore_init(QEMUMachineInitArgs *args)
c988bfad 349{
5f072e1f
EH
350 ram_addr_t ram_size = args->ram_size;
351 const char *cpu_model = args->cpu_model;
352 const char *kernel_filename = args->kernel_filename;
353 const char *kernel_cmdline = args->kernel_cmdline;
354 const char *initrd_filename = args->initrd_filename;
355 const char *boot_device = args->boot_device;
c988bfad
PB
356 if (!cpu_model) {
357 cpu_model = "arm11mpcore";
358 }
359 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
360 initrd_filename, cpu_model, BOARD_EB_MPCORE);
361}
362
5f072e1f 363static void realview_pb_a8_init(QEMUMachineInitArgs *args)
0ef849d7 364{
5f072e1f
EH
365 ram_addr_t ram_size = args->ram_size;
366 const char *cpu_model = args->cpu_model;
367 const char *kernel_filename = args->kernel_filename;
368 const char *kernel_cmdline = args->kernel_cmdline;
369 const char *initrd_filename = args->initrd_filename;
370 const char *boot_device = args->boot_device;
0ef849d7
PB
371 if (!cpu_model) {
372 cpu_model = "cortex-a8";
373 }
374 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
375 initrd_filename, cpu_model, BOARD_PB_A8);
376}
377
5f072e1f 378static void realview_pbx_a9_init(QEMUMachineInitArgs *args)
f7c70325 379{
5f072e1f
EH
380 ram_addr_t ram_size = args->ram_size;
381 const char *cpu_model = args->cpu_model;
382 const char *kernel_filename = args->kernel_filename;
383 const char *kernel_cmdline = args->kernel_cmdline;
384 const char *initrd_filename = args->initrd_filename;
385 const char *boot_device = args->boot_device;
f7c70325
PB
386 if (!cpu_model) {
387 cpu_model = "cortex-a9";
388 }
389 realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
390 initrd_filename, cpu_model, BOARD_PBX_A9);
391}
392
c988bfad
PB
393static QEMUMachine realview_eb_machine = {
394 .name = "realview-eb",
c9b1ae2c 395 .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
c988bfad
PB
396 .init = realview_eb_init,
397 .use_scsi = 1,
398};
399
400static QEMUMachine realview_eb_mpcore_machine = {
401 .name = "realview-eb-mpcore",
402 .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
403 .init = realview_eb_mpcore_init,
c9b1ae2c 404 .use_scsi = 1,
c988bfad 405 .max_cpus = 4,
e69954b9 406};
f80f9ec9 407
0ef849d7
PB
408static QEMUMachine realview_pb_a8_machine = {
409 .name = "realview-pb-a8",
410 .desc = "ARM RealView Platform Baseboard for Cortex-A8",
411 .init = realview_pb_a8_init,
f7c70325
PB
412};
413
414static QEMUMachine realview_pbx_a9_machine = {
415 .name = "realview-pbx-a9",
416 .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
417 .init = realview_pbx_a9_init,
0ef849d7 418 .use_scsi = 1,
f7c70325 419 .max_cpus = 4,
0ef849d7
PB
420};
421
f80f9ec9
AL
422static void realview_machine_init(void)
423{
c988bfad
PB
424 qemu_register_machine(&realview_eb_machine);
425 qemu_register_machine(&realview_eb_mpcore_machine);
0ef849d7 426 qemu_register_machine(&realview_pb_a8_machine);
f7c70325 427 qemu_register_machine(&realview_pbx_a9_machine);
f80f9ec9
AL
428}
429
430machine_init(realview_machine_init);